HCPL-2612#500 [AVAGO]
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8;
| 型号： | HCPL-2612#500 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8 输出元件 光电 |
| 文件： | 总16页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-2602,HCPL-2612
HighCMRLineReceiverOptocouplers
DataSheet
Description
Features
TheHCPL-2602/12areopticallycoupledlinereceivers
that combine a GaAsP light emitting diode, an input
current regulator and an integrated high gain photo
detector. The input regulator serves as a line
termination for line receiver applications. It clamps
the line voltage and regulates the LED current so line
reflections do not interfere with circuit performance.
• 1000 V/ µs minimum Common Mode Rejection (CMR) at
VCM = 50 V for HCPL-2602 and 3.5 kV/ µs minimum
CMR at VCM = 300 V for HCPL-2612
• Line termination included – no extra circuitry required
• Accepts a broad range of drive conditions
• LED protection minimizes LED efficiency degradation
• High speed: 10 MBd (limited by transmission line in
many applications)
The regulator allows a typical LED current of 8.5 mA
before it starts to shunt excess current. The output
ofthedetectorICisanopencollectorSchottkyclamped
• Guaranteed AC and DC performance over temperature:
0°C to 70°C
transistor. An enable input gates the detector. The • External base lead allows “LED peaking” and LED
internal detector shield provides a guaranteed
common mode transient immunity specification of
1000 V/ms for the 2602, and 3500 V/ms for the 2612.
current adjustment
• Safety approval
UL recognized – 3750 V rms for 1 Minute
CSA approved
DC specifications are defined similar to TTL logic.
The optocoupler ac and dc operational parameters
are guaranteed from 0°C to 70°C allowing trouble-
free interfacing with digital logic circuits. An input
current of 5 mA will sink an eight gate fan-out (TTL)
at the output.
• MIL-PRF-38534 hermetic version available (HCPL-1930/ 1)
Applications
• Isolated line receiver
• Computer-peripheral interface
• Microprocessor system interface
• Digital isolation for A/ D, D/ A conversion
• Current sensing
• Instrument input/ output isolation
• Ground loop elimination
• Pulse transformer replacement
• Power transistor isolation in motor drives
Functional Diagram
TRUTH TABLE
(POSITIVE LOGIC)
V
1
2
8
7
NC
IN+
CC
LED ENABLE OUTPUT
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
V
E
V
IN–
3
4
6
5
O
GND
CATHODE
H
SHIELD
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
The HCPL-2602/12 are useful as line receivers in
high noise environments that conventional line
receivers cannot tolerate. The higher LED threshold
voltage provides improved immunity to differential
noise and the internally shielded detector provides
orders of magnitude improvement in common mode
rejection with little or no sacrifice in speed.
Selection Guide
Widebody
Hermetic
Minimum CMR
8-Pin DIP (300 Mil)
Small-Outline SO-8(400 Mil)
Hermetic
Input
On-
Current
(mA)
Single
Dual
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Single and
Dual Channel
Packages
dV/ dt
V
CM
Output
Enable
Channel
Package
Channel
Package
(V/ µs)
(V)
NA
NA
5
YES
NO
YES
NO
YES
NO
YES
YES
YES
NO
YES
6N137
HCPL-0600
HCPL-0601
HCPL-0611
HCNW137
HCNW2601
HCNW2611
HCPL-2630
HCPL-2631
HCPL-4661
HCPL-0630
HCPL-0631
HCPL-0661
5,000
10,000
50
HCPL-2601
HCPL-2611
1,000
1,000
3,500
1,000
50
300
50
HCPL-2602[1]
HCPL-2612[1]
HCPL-261A
3
HCPL-061A
HCPL-061N
HCPL-263A
HCPL-263N
HCPL-063A
HCPL-063N
1,000[2]
1,000
1,000
50
HCPL-261N
NO
[3]
12.5
HCPL-193X
HCPL-56XX
HCPL-66XX
Notes:
1. HCPL-2602/ 2612 devices include input current regulator.
2. 15 kV/ µs with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
2
Ordering Information
HCPL-2602/HCPL-2612 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
non RoHS
Surface
Mount
Gull
Wing
Tape
& Reel
Compliant Compliant Package
Quantity
HCPL-2602 -000E
HCPL-2612 -300E
-500E
no option
#300
300 mil DIP-8
50 per tube
50 per tube
1000 per reel
X
X
X
X
#500
X
To order, choose a part number from the part number column and combine with the desired option from the
option column to form an order entry.
Example 1:
HCPL-2602-500E to order product of Gull Wing Surface Mount package in Tape and Reel packaging and RoHS
compliant.
Example 2:
HCPL-2612 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for
information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15,
2001 and RoHS compliant will use ‘–XXXE.’
Schematic
+
V
V
CC
I
I
F
I
I
8
6
2
CC
I
O
O
V
I
90 Ω
–
3
GND
5
SHIELD
I
E
7
V
E
4
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS REQUIRED (SEE NOTE 1).
3
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
DATE CODE
A XXXXZ
YYWW
U R
UL
1
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2
3
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
4
Solder Reflow Thermal Profile
Regulatory Information
The HCPL-2602/2612 have been
approved by the following
organizations:
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
UL
200
100
0
2.5°C ± 0.5°C/SEC.
Recognized under UL 1577,
Component Recognition Program,
File E55361.
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
CSA
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
150 - 200 °C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
Note: Non-halide flux should be used.
Insulation and Safety Related Specifications
Parameter
Symbol
Value Units Conditions
Min. External Air Gap
(External Clearance)
L(I01)
7.1
mm
mm
mm
Measured from input terminals to output terminals,
shortest distance through air.
Min. External Tracking
Path (External Creepage)
L(I02)
CTI
7.4
Measured from input terminals to output terminals,
shortest distance path along body.
Min. Internal Plastic
Gap (Internal Clearance)
0.08
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
Tracking Resistance
(Comparative Tracking
Index)
200
IIIa
V
DIN IEC 112/ VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/ 89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
5
Absolute Maximum Ratings (No Derating Required up to 85°C)
Parameter
Symbol
Min.
-55
Max.
125
85
Units
°C
Storage Temperature
T
S
Operating Temperature
T
A
-40
°C
Forward Input Current
I
60
mA
mA
mA
V
I
Reverse Input Current
I
IR
60
Input Current, Pin 4
-10
10
Supply Voltage (1 Minute Maximum)
V
CC
7
Enable Input Voltage (Not to Exceed V by
V
E
V + 0.5
CC
V
CC
more than 500 mV)
Output Collector Current
I
50
7
mA
V
O
Output Collector Voltage (Selection for Higher
Output Voltages up to 20 V is Available.)
V
O
Output Collector Power Dissipation
Lead Solder Temperature
P
40
mW
O
T
LS
260°C for 10 sec., 1.6 mm below
seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
Min.
0
Max.
250
60
Units
µA
mA
V
Input Current, Low Level
Input Current, High Level
Supply Voltage, Output
High Level Enable Voltage
Low Level Enable Voltage
Fan Out (@ RL = 1 kΩ)
Output Pull-up Resistor
Operating Temperature
I
IL
IIH
5*
4.5
2.0
0
V
CC
5.5
V
EH
V
CC
V
V
EL
0.8
5
V
N
TTL Loads
RL
330
0
4 K
70
Ω
T
A
°C
*The initial switching threshold is 5 mA or less. It is recommended that an input current between
6.3 mA and 10 mA be used to obtain best performance and to provide at least 20% LED degradation
guardband.
6
Electrical Characteristics
Over recommended temperature (TA = 0°C to +70°C) unless otherwise specified. See note 1.
Parameter
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
High Level Output
Current
IOH
5.5
100
µA
V = 5.5 V, V = 5.5 V,
1
CC
O
I = 250 µA, V = 2.0 V
I
E
Low Level Output
Voltage
V
OL
0.35
0.6
V
V = 5.5 V, II = 5 mA,
2, 4,
CC
V = 2.0 V,
E
5, 14
IOL (Sinking) = 13 mA
High Level Supply
Current
ICCH
ICCL
IEH
7.5
10
10
13
mA
mA
mA
mA
V
V = 5.5 V, II = 0 mA,
CC
V = 0.5 V
E
Low Level Supply
Current
V = 5.5 V, I = 60 mA,
CC
I
V = 0.5 V
E
High Level Enable
Current
-0.7
-0.9
-1.6
-1.6
V = 5.5 V, V = 2.0 V
CC E
Low Level Enable
Current
IEL
V = 5.5 V, V = 0.5 V
CC E
High Level Enable
Voltage
V
EH
2.0
10
Low Level Enable
Voltage
V
EL
0.8
V
2.0
2.3
2.4
2.7
I = 5 mA
I
Input Voltage
V
V
V
3
I
I = 60 mA
I
Input Reverse
Voltage
V
R
0.75
0.95
IR = 5 mA
Input Capacitance
C
IN
90
pF
V = 0 V, f = 1 MHz
I
*All typicals at V = 5 V, TA = 25°C.
CC
7
Switching Specifications
Over recommended temperature (TA = 0°C to +70°C), V = 5 V, I = 7.5 mA, unless otherwise specified.
CC
I
Parameter
Symbol
Device
Min.
Typ.* Max. Units
Test Conditions
TA = 25°C
Fig. Note
Propagation Delay
Time to High Output
Level
75
ns
tPLH
20
48
6,7, 8
3
100
75
ns
ns
Propagation Delay
Time to Low Output
Level
TA = 25°C
tPHL
25
50
6,7, 8
9
4
100
35
ns
ns
RL = 350 Ω
CL = 15 pF
Pulse Width
Distortion
| tPHL-tPLH
|
3.5
13
Propagation Delay
Skew
tPSK
tr
40
ns
ns
ns
ns
12,
13
Output Rise Time
(10-90%)
24
10
30
12
12
Output Fall Time
(90-10%)
tf
Propagation Delay
Time of Enable from
tELH
RL = 350 Ω, CL = 15 pF,
V = 0 V, VEH = 3 V
EL
10, 11
10, 11
5
6
V
EH to V
EL
Propagation Delay
Time of Enable from
V to V
tEHL
| CMH|
| CML|
20
ns
RL = 350 Ω, CL = 15 pF,
V = 0 V, VEH = 3 V
EL
EL
EH
Common Mode
Transient
Immunity at High
HCPL-2602
HCPL-2612
1000 10,000
3500 15,000
V
CM = 50 V
CM = 300 V
CM = 50 V
CM = 300 V
VO(MIN) = 2 V,
RL = 350 Ω,
II = 0 mA,
V/ µs
V/ µs
13
13
7, 9,
10
V
Output Level
TA = 25°C
Common Mode
Transient
Immunity at Low
HCPL-2602
HCPL-2612
1000 10,000
3500 15,000
V
VO(MAX) = 0.8V,
RL = 350 Ω,
II = 7.5 mA,
TA = 25°C
8, 9
10
V
Output Level
*All typicals at V = 5 V, TA = 25°C.
CC
Package Characteristics
All Typicals at T = 25°C
A
Parameter
Sym.
Min.
Typ. Max. Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
V
ISO
3750
V rms RH ≤ 50%, t = 1 min.,
2, 11
T = 25°C
A
Input-Output Resistance
Input-Output Capacitance
R
1012
0.6
Ω
V = 500 Vdc
2
2
I-O
I-O
C
I-O
pF
f = 1 MHz
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/ EN/ DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
8
Notes:
1. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 15. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
2. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
3. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
4. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
5. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge
of the output pulse.
6. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge
of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V).
9. For sinusoidal voltages,
| dvCM
––––––
dt max
10. No external pull up is required for a high logic state on the enable input. If the V pin is not used, tying V to VCC will result in improved CMR
|
= πfCMVCM (p-p)
E
E
performance.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage of ≥ 4500 for one second (leakage detection
current limit, Ii-o ≤ 5 µA).
12. tPSK is equal to the worst case difference in tPHL and/ or tPLH that will be seen between units at any given temperature within the operating condition
range.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
15
10
2.6
2.4
0.5
0.4
V
V
= 5.5 V
CC
= 2 V
V
V
V
= 5.5 V
= 5.5 V
= 2 V
CC
O
E
0°C
E
I = 5 mA
I
25°C
70°C
2.2
2.0
1.8
1.6
I = 250 µA
I
I
= 12.8 mA
O
I
= 16 mA
= 6.4 mA
O
0.3
0.2
0.1
5
0
I
O
1.4
I
= 9.6 mA
O
1.2
1.0
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
0
10
20
30
40
50
60
T
– TEMPERATURE – °C
I – INPUT CURRENT – mA
A
T
– TEMPERATURE – °C
I
A
Figure 1. Typical high level output current vs.
temperature.
Figure 2. Typical low level output voltage vs.
temperature.
Figure 3. Typical input characteristics.
6
70
V
T
= 5 V
V
V
V
= 5 V
= 2 V
= 0.6 V
CC
= 25 °C
CC
E
OL
A
5
4
3
2
60
50
I = 10-15 mA
I
R
= 350 Ω
L
R
= 1 KΩ
L
R
= 4 KΩ
I = 5.0 mA
I
L
40
20
1
0
0
1
2
3
4
6
5
-60 -40 -20
0
20 40
80 100
60
I
– FORWARD INPUT CURRENT – mA
F
T
– TEMPERATURE – °C
A
Figure 4. Typical output voltage vs. forward
input current.
Figure 5. Typical low level output current vs.
temperature.
9
+5 V
I
I
PULSE GEN.
= 50 Ω
V
1
2
3
4
8
7
6
5
CC
Z
O
t
= t = 5 ns
r
f
0.1µF
BYPASS
R
L
100
80
OUTPUT V
MONITORING
NODE
INPUT
MONITORING
NODE
O
V
I
= 5 V
CC
I = 7.5 mA
*C
L
t
, R = 4 KΩ
L
PLH
R
M
GND
t
, R = 350 Ω
L
PHL
1 KΩ
4 KΩ
60
40
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
t
, R = 1 KΩ
L
PLH
I
= 7.50 mA
= 3.75 mA
I
I
t
, R = 350 Ω
L
PLH
INPUT
20
0
I
I
I
t
t
PHL
PLH
-60 -40 -20
0
20 40
80 100
60
OUTPUT
V
O
1.5 V
T
– TEMPERATURE – °C
A
Figure 6. Test circuit for tPHL and tPLH
.
Figure 7. Typical propagation delay vs.
temperature.
105
90
40
30
20
10
V
T
= 5 V
CC
= 25°C
R
= 4 kΩ
L
A
t
, R = 4 KΩ
L
PLH
V
I
= 5 V
CC
I = 7.5 mA
75
60
t
, R = 350 Ω
L
R
= 350 kΩ
PLH
L
t
, R = 1 KΩ
L
PLH
45
30
0
t
, R = 350 Ω
PHL
L
R
= 1 kΩ
L
1 KΩ
4 KΩ
-10
5
7
9
11
13
15
-60 -40 -20
0
20 40
80 100
60
I – PULSE INPUT CURRENT – mA
T
– TEMPERATURE – °C
I
A
Figure 8. Typical propagation delay vs. pulse
input current.
Figure 9. Typical pulse width distortion vs.
temperature.
PULSE GEN.
Z
= 50 Ω
r
O
INPUT V
MONITORING NODE
E
t
= t = 5 ns
f
+5 V
V
CC
1
8
7
6
5
7.5 mA
0.1 µF
BYPASS
R
L
2
3
4
I
I
120
OUTPUT V
MONITORING
NODE
O
V
V
V
= 5 V
= 3 V
= 0 V
CC
EH
EL
*C
L
I = 7.5 mA
I
90
60
GND
t
, R = 4 kΩ
L
ELH
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
t
, R = 1 kΩ
ELH
L
3.0 V
1.5 V
INPUT
30
0
t
, R = 350 Ω
ELH
L
V
E
t
t
EHL
ELH
t
, R = 350 Ω, 1 kΩ, 4 kΩ
L
EHL
OUTPUT
-60 -40 -20
0
20 40 60 80 100
V
O
1.5 V
T
– TEMPERATURE – °C
A
Figure 10. Test circuit for tEHL and tELH
.
Figure 11. Typical enable propagation delay
vs. temperature.
10
I
I
V
= 5 V
t
t
CC
I = 7.5 mA
RISE
FALL
V
1
2
3
4
8
7
6
5
+5 V
CC
I
B
A
0.1 µF
BYPASS
350 Ω
OUTPUT V
R
= 4 kΩ
= 1 kΩ
300
290
60
L
O
MONITORING
NODE
R
L
GND
40
V
CM
R
R
= 350 Ω
L
20
0
+
–
PULSE
GENERATOR
= 50 Ω
= 350 Ω, 1 kΩ, 4 kΩ
L
0
-60 -40 -20
20 40 60 80 100
Z
O
T
– TEMPERATURE – °C
A
V
(PEAK)
CM
SWITCH AT A: I = 0 mA
V
CM
0 V
5 V
I
Figure 12. Typical rise and fall time vs.
temperature.
CM
H
V
O
V
(MIN.)
O
SWITCH AT B: I = 7.5 mA
I
V
(MAX.)
O
V
O
0.5 V
CM
L
Figure 13. Test circuit for common mode transient immunity and typical waveforms.
GND BUS (BACK)
V
BUS (FRONT)
NC
CC
V
V
= 5.0 V
CC
= 0.6 V
5
4
3
O
ENABLE
(IF USED)
0.1µF
R
= 350 Ω
L
NC
NC
OUTPUT 1
2
1
0
R
R
= 1 kΩ
= 4 kΩ
L
L
ENABLE
(IF USED)
0.1µF
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
A
NC
OUTPUT 2
Figure 14. Typical input threshold current vs.
temperature.
10 mm MAX.
(SEE NOTE 1)
Figure 15. Recommended printed circuit board layout.
11
Using the HCPL-2602/ 12 Line
Receiver Optocouplers
interfere with circuit perform-
ance because the regulator
inputs are then connected in
ANTI-SERIES; however, because
of the higher steady-state termina-
tion voltage, in comparison to the
single HCPL-2602/12 termination,
the forward current in the
substrate diode is lower and
consequently there is less junction
charge to deal with when
clamps the line voltage. At longer
line lengths, tPLH increases faster
than tPHL since the switching
threshold is not exactly halfway
between asymptotic line
conditions. If optimum data rate
is desired, a series resistor and
peaking capacitor can be used to
equalize tPLH and tPHL. In general,
the peaking capacitance should be
as large as possible; however, if it
is too large it may keep the
The primary objectives to fulfill
when connecting an optocoupler
to a transmission line are to
provide a minimum, but not
excessive, LED current and to
properly terminate the line. The
internal regulator in the HCPL-
2602/12 simplifies this task.
Excess current from variable
drive conditions such as line
length variations, line driver
differences, and power supply
fluctuations are shunted by the
regulator. In fact, with the LED
current regulated, the line current
can be increased to improve the
immunity of the system to
differential-mode-noise and to
enhance the data rate capability.
The designer must keep in mind
the 60 mA input current
maximum rating of the HCPL-
2602/12 in such cases, and may
need to use series limiting or
shunting to prevent overstress.
switching.
Closing switch B with A open is
done mainly to enhance common
mode rejection, but also reduces
propagation delay slightly because
line-to-line capacitance offers a
slight peaking effect. With
switches A and B both CLOSED,
the shield acts as a current return
path which prevents either input
substrate diode from becoming
reversed biased. Thus the data
rate is optimized as shown in
Figure (c).
regulator from achieving turn-off
during the negative (or zero)
excursions of the input signal. A
safe rule:
make C ≤16t
where:
C = peaking capacitance in
picofarads
t = data bit interval in
nanoseconds
Improved Noise Rejection
Use of additional logic at the
output of two HCPL-2602/12s,
operated in the split phase
termination, will greatly improve
system noise rejection in addition
to balancing propagation delays
as discussed earlier.
Polarity Reversing Drive
Design of the termination circuit
is also simplified; in most cases
the transmission line can simply
be connected directly to the input
terminals of the HCPL-2602/12
without the need for additional
series or shunt resistors. If
reversing line drive is used it may
be desirable to use two HCPL-
2602/12 or an external Schottky
diode to optimize data rate.
A single HCPL-2602/12 can also
be used with polarity reversing
drive (Figure b). Current reversal
is obtained by way of the
substrate isolation diode
(substrate to collector). Some
reduction of data rate occurs,
however, because the substrate
diode stores charge, which must
be removed when the current
changes to the forward direction.
A NAND flip-flop offers infinite
common mode rejection (CMR)
for NEGATIVELY sloped common
mode transients but requires tPHL
> tPLH for proper operation. A NOR
flip-flop has infinite CMR for
The effect of this is a longer tPHL
.
Polarity Non-Reversing Drive
This effect can be eliminated and
data rate improved considerably
by use of a Schottky diode on the
input of the HCPL-2602/12.
POSITIVELY sloped transients
but requires tPHL < tPLH for proper
operation. An exclusive-OR flip-
flop has infinite CMR for common
mode transients of EITHER
High data rates can be obtained
with the HCPL-2602/12 with
polarity non-reversing drive.
Figure (a) illustrates how a
74S140 line driver can be used
with the HCPL-2602/12 and
shielded, twisted pair or coax
cable without any additional
components. There are some
reflections due to the “active
termination,” but they do not
For optimum noise rejection as
well as balanced delays, a split-
phase termination should be used
along with a flip-flop at the output
(Figure c). The result of current
reversal in split-phase operation
is seen in Figure (c) with switches
A and B both OPEN. The coupler
polarity and operates with either
tPHL > tPLH or tPHL < tPLH
.
With the line driver and
transmission line shown in Figure
(c), tPHL > tPLH, so NAND gates are
preferred in the R-S flip-flop. A
higher drive amplitude or
12
Figure a. Polarity non-reversing.
Figure b. Polarity reversing, single ended.
< 1
< 1
Figure c. Polarity reversing, split phase.
Figure d. Flip-flop configurations.
13
different circuit configuration
could make tPHL < tPLH, in which
case NOR gates would be pre-
ferred. If it is not known whether
tPHL > tPLH or tPHL < tPLH, or if the
drive conditions may vary over the the exact figure depends on the
boundary for these conditions, the particular application (RS232,
exclusive-OR flip-flop of Figure (d) RS422, T-1, etc.).
should be used.
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
both the clock and the data lines
being sent through optocouplers.
The figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
minimum pulse width is tolerable;
Propagation delay skew, tPSK, is an
RS-422 and RS-423
important parameter to consider
in parallel data applications
where synchronization of signals
on parallel data lines is a concern.
If the parallel data is being sent
through a group of optocouplers,
differences in propagation delays
will cause the data to arrive at the
outputs of the optocouplers at
different times. If this difference
in propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Line drivers designed for RS-422
and RS-423 generally provide
adequate voltage and current for
operating the HCPL-2602/12. Most
drivers also have characteristics
allowing the HCPL-2602/12 to be
connected directly to the driver
terminals. Worst case drive
conditions, however, would
require current shunting to
prevent overstress of the HCPL-
2602/12.
Propagation delay skew
represents the uncertainty of
where an edge might be after
being sent through an
optocoupler. Figure 17 shows that
there will be uncertainty in both
the data and the clock lines. It is
important that these two areas of
uncertainty not overlap,
otherwise the clock signal might
arrive before all of the data
outputs have settled, or some of
the data outputs may start to
change before the clock signal has
arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew
Propagation delay is a figure of
merit which describes how quickly
a logic signal propagates through a
system. The propagation delay
from low to high (tPLH) is the
amount of time required for an
input signal to propagate to the
output, causing the output to
change from low to high. Similarly,
the propagation delay from high to
low (tPHL) is the amount of time
required for the input signal to
propagate to the output, causing
the output to change from high to
low (see Figure 6).
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either tPLH or
tPHL, for any given group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
uncertainty in the rest of the
circuit does not cause a problem.
operating temperature). As
illustrated in Figure 16, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the
difference between the shortest
propagation delay, either tPHL or
tPHL, and the longest propagation
The tPSK specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulse-width
distortion and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
Pulse-width distortion (PWD)
results when tPLH and tPHL differ in
value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
delay, either tPLH or tPHL
.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 17
is the timing diagram of a typical
parallel data application with
14
DATA
INPUTS
I
I
50%
50%
CLOCK
1.5 V
V
O
DATA
I
I
OUTPUTS
CLOCK
t
PSK
V
1.5 V
O
t
PSK
t
PSK
Figure 17. Parallel data transmission example.
Figure 16. Illustration of propagation delay skew - tPSK
.
15
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2154EN
AV01-0568EN July 18, 2007
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