HCPL-261A#020 [ETC]
LOGIC-GATE-OUTPUT OPTOCOUPLER ; 逻辑门，输出光电耦合器\n
| 型号： | HCPL-261A#020 |
| 厂家： | 
ETC |
| 描述： | LOGIC-GATE-OUTPUT OPTOCOUPLER
|
| 文件： | 总16页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCMOS Compatible, High CMR,
10 MBd Optocouplers
Technical Data
HCPL-261A HCPL-061A
HCPL-263A HCPL-063A
HCPL-261N HCPL-061N
HCPL-263N HCPL-063N
Features
• HCMOS/LSTTL/TTL
• Computer-Peripheral
Interface
compatible input current. This
allows direct interface to all
common circuit topologies without
additional LED buffer or drive
components. The AlGaAs LED
used allows lower drive currents
and reduces degradation by using
the latest LED technology. On the
single channel parts, an enable
output allows the detector to be
strobed. The output of the detector
IC is an open collector schottky-
clamped transistor. The internal
shield provides a minimum
Performance Compatible
• 1000 V/µs Minimum
Common Mode Rejection
(CMR) at VCM = 50 V (HCPL-
261A Family) and 15 kV/µs
• Digital Isolation for A/D,
D/A Conversion
• Switching Power Supplies
• Instrumentation
Input/Output Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
Minimum CMR at VCM
=
1000 V (HCPL-261N Family)
• High Speed: 10 MBd Typical
• AC and DC Performance
Specified over Industrial
Temperature Range -40°C to
+85°C
• Available in 8 Pin DIP,
SOIC-8 Packages
Description
The HCPL-261A family of optically
coupled gates shown on this data
sheet provide all the benefits of the
industry standard 6N137 family
with the added benefit of HCMOS
common mode transient immunity
of 1000 V/µs for the HCPL-261A
family and 15000 V/µs for the
HCPL-261N family.
• Safety Approval
UL Recognized per UL1577
2500 V rms for 1 minute and
5000 V rms for 1 minute
(Option 020)
Functional Diagram
HCPL-261A/261N
HCPL-061A/061N
HCPL-263A/263N
HCPL-063A/063N
CSA Approved
VDE 0884 Approved with
NC
ANODE
CATHODE
NC
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
CC
CC
O1
O2
1
1
VIORM = 630 V peak for
E
HCPL-261A/261N
Option 060
V
3
4
6
5
3
4
6
5
O
2
2
GND
GND
SHIELD
SHIELD
Applications
• Low Input Current (3.0 mA)
HCMOS Compatible Version
of 6N137 Optocoupler
• Isolated Line Receiver
• Simplex/Multiplex Data
Transmission
TRUTH TABLE
(POSITIVE LOGIC)
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
LED OUTPUT
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
ON
L
OFF
H
H
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is required.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Selection Guide
Widebody
(400 Mil)
Minimum CMR
8-Pin DIP (300 Mil)
Small-Outline SO-8
Hermetic
Input
On-
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
HCPL-0600[1]
HCPL-0601[1]
HCPL-0611[1]
Dual
Channel
Package
Single
Channel
Package
HCNW137[1]
HCNW2601[1]
HCNW2611[1]
Single and
Dual Channel
Packages
dV/dt
(V/µs)
VCM
(V)
Current Output
(mA)
Enable
YES
NO
NA
NA
5
6N137[1]
HCPL-2630[1]
HCPL-2631[1]
HCPL-4661[1]
HCPL-0630[1]
HCPL-0631[1]
HCPL-0661[1]
5,000
50
YES
NO
HCPL-2601[1]
HCPL-2611[1]
10,000 1,000
YES
NO
1,000
3,500
1,000
50
300
50
YES
YES
YES
NO
HCPL-2602[1]
HCPL-2612[1]
HCPL-261A
3
HCPL-061A
HCPL-061N
HCPL-263A
HCPL-263N
HCPL-063A
HCPL-063N
1,000[2] 1,000
YES
HCPL-261N
NO
[3]
1,000
50
12.5
HCPL-193X[1]
HCPL-56XX[1]
HCPL-66XX[1]
Notes:
1. Technical data are on separate Agilent publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using Agilent application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-261A#XXX
020 = 5000 V rms/1 minute UL Rating Option*
060 = VDE 0884 VIORM = 630 Vpeak Option**
300 = Gull Wing Surface Mount Option***
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Agilent sales representative or authorized distributor for
information.
*For HCPL-261A/261N/263A/263N (8-pin DIP products) only.
**For HCPL-261A/261N only. Combination of Option 020 and Option 060 is not available.
HCPL-263A/263N
***Gull wing surface mount option applies to through hole parts only.
HCPL-063A/063N
I
CC
V
V
CC
Schematic
8
7
1
+
I
HCPL-261A/261N
HCPL-061A/061N
F1
I
O1
O1
I
F
I
CC
V
V
V
F1
CC
8
6
2+
I
O
–
2
O
SHIELD
3
–
I
F2
V
F
I
O2
V
–
3
O2
6
5
GND
5
SHIELD
V
F2
I
E
7
E
V
+
4
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16).
GND
SHIELD
3
HCPL-261A/261N/263A/263N Outline Drawing
Pin Location (for reference only)
9.40 (0.370)
9.90 (0.390)
8
1
7
6
5
TYPE NUMBER
0.20 (0.008)
0.33 (0.013)
OPTION CODE*
DATE CODE
6.10 (0.240)
6.60 (0.260)
A XXXXZ
YYWW
7.36 (0.290)
7.88 (0.310)
5° TYP.
2
3
4
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
DIMENSIONS IN MILLIMETERS AND (INCHES).
4.70 (0.185) MAX.
0.51 (0.020) MIN.
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.92 (0.115) MIN.
0.76 (0.030)
1.40 (0.056)
0.65 (0.025) MAX.
2.28 (0.090)
2.80 (0.110)
Figure 1. 8-Pin Dual In-Line Package Device Outline Drawing.
PIN LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.02 (0.040)
1.19 (0.047)
7
6
5
8
1
4.83
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
2
3
4
0.38 (0.015)
0.64 (0.025)
1.19 (0.05)
1.78 (0.07)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
4.19
MAX.
(0.165)
0.635 ± 0.25
(0.025 ± 0.010)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
(0.025 ± 0.005)
12° NOM.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
Figure 2. Gull Wing Surface Mount Option #300.
4
HCPL-061A/061N/063A/063N Outline Drawing
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
3.937 ± 0.127
(0.155 ± 0.005)
YWW
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
1
2
3
4
PIN ONE
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSG
0.432
(0.017)
*
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
Figure 3. 8-Pin Small Outline Package Device Drawing.
Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount
Option 300 Parts)
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of Nonchlorine Activated Fluxes is Recommended.
Regulatory Information
CSA
The HCPL-261A and HCPL-261N
families have been approved by
the following organizations:
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
UL
VDE
Recognized under UL 1577,
Component Recognition
Program, File E55361.
Approved according to VDE
0884/06.92. (HCPL-261A/261N
Option 060 only)
5
Insulation and Safety Related Specifications
8-Pin DIP
(300 Mil) SO-8
Parameter
Symbol
Value
Value Units
Conditions
Minimum External Air
Gap (External
Clearance)
Minimum External
Tracking (External
Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
L(101)
7.1
4.9
mm
mm
mm
Measured from input terminals to
output terminals, shortest distance
through air.
Measured from input terminals to
output terminals, shortest distance
path along body.
Through insulation distance, conductor
to conductor, usually the direct
distance between the photoemitter and
photodetector inside the optocoupler
cavity.
L(102)
7.4
4.8
0.08
0.08
Tracking Resistance
(Comparative Tracking
Index)
CTI
200
IIIa
200
IIIa
Volts DIN IEC 112/ VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89,
Table 1)
Option 300 – surface mount classification is Class A in accordance with CECC 00802.
VDE 0884 Insulation Related Characteristics
(HCPL-261A/261N Option 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
I-IV
I-III
Climatic Classification
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
IORM
630
Vpeak
Vpeak
V
IORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
1181
945
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec,
Vpeak
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
IOTM
6000
Vpeak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
≥ 109
°C
mA
mW
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
6
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Average Input Current
Reverse Input Voltage
Supply Voltage
Enable Input Voltage
Output Collector Current (Each Channel)
Output Power Dissipation (Each Channel)
Output Voltage (Each channel)
Symbol
Min.
-55
-40
Max.
125
+85
10
3
7
5.5
50
60
Units
°C
°C
Note
TS
T
A
IF(AVG)
VR
VCC
VE
IO
PO
mA
1
2
Volts
Volts
Volts
mA
mW
Volts
-0.5
-0.5
3
VO
-0.5
7
Lead Solder Temperature
(Through Hole Parts Only)
260°C for 10 s, 1.6 mm Below Seating Plane
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
VFL
IFH
Min.
-3
3.0
4.5
2.0
0
Max.
0.8
10
5.5
VCC
0.8
5
Units
V
mA
Input Voltage, Low Level
Input Current, High Level
Power Supply Voltage
High Level Enable Voltage
Low Level Enable Voltage
Fan Out (at RL = 1 kΩ)
Output Pull-up Resistor
Operating Temperature
VCC
VEH
VEL
N
RL
TA
Volts
Volts
Volts
TTL Loads
Ω
330
-40
4k
85
°C
7
Electrical Specifications
Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified.
A
Parameter
High Level Output
Current
Symbol Min. Typ.* Max. Units
Test Conditions
VCC = 5.5 V, VO = 5.5 V,
VF = 0.8 V, VE = 2.0 V
Fig. Note
18
IOH
3.1
100
µA
4
Low Level Output
Voltage
VOL
0.4
0.6
V
VCC = 5.5 V, IOL = 13 mA
(sinking), IF = 3.0 mA,
VE = 2.0 V
5, 8 4, 18
High Level Supply
Current
ICCH
7
9
10
15
mA VE = 0.5 V**
VCC = 5.5 V
IF = 0 mA
4
Dual Channel
Products***
Low Level Supply
Current
ICCL
8
12
13
21
mA
VE = 0.5 V**
Dual Channel
Products***
VCC = 5.5 V
IF = 3.0 mA
High Level Enable
Current**
Low Level Enable
Current**
Input Forward
Voltage
Temperature Co-
efficient of Forward
Voltage
IEH
IEL
-0.6
-0.9
1.3
-1.6
-1.6
1.6
mA VCC = 5.5 V, VE = 2.0 V
mA VCC = 5.5 V, VE = 0.5 V
VF
1.0
3
V
IF = 4 mA
6
4
4
∆VF/∆T
-1.25
mV/°C IF = 4 mA
A
Input Reverse
Breakdown Voltage
Input Capacitance
BVR
CIN
5
V
IR = 100 µA
4
60
pF
f = 1 MHz, VF = 0 V
*All typical values at TA = 25°C, VCC = 5 V
**Single Channel Products only (HCPL-261A/261N/061A/061N)
***Dual Channel Products only (HCPL-263A/263N/063A/063N)
8
Switching Specifications
Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified
A
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Input Current Threshold
High to Low
ITHL
1.5
3.0
mA VCC = 5.5 V, VO = 0.6 V, 7, 10 18
IO >13 mA (Sinking)
Propagation Delay
Time to High Output
Level
Propagation Delay
Time to Low Output
Level
tPLH
52
100
ns
ns
ns
IF = 3.5 mA
VCC = 5.0 V,
VE = Open,
CL = 15 pF,
RL = 350 Ω
9, 11, 4, 9,
12 18
tPHL
53
11
100
9, 11, 4, 10,
12 18
Pulse Width Distortion
PWD
|tPHL - tPLH
45
60
9, 13 17, 18
|
Propagation Delay Skew
Output Rise Time
Output Fall Time
Propagation Delay
Time of Enable
from VEH to VEL
Propagation Delay
Time of Enable
from VEL to VEH
tPSK
tR
tF
ns
ns
ns
ns
24 11, 18
9, 14 4, 18
9, 14 4, 18
42
12
19
tEHL
IF = 3.5 mA
VCC = 5.0 V,
VEL = 0 V, VEH = 3 V,
CL = 15 pF,
15,
16
12
tELH
30
ns
15,
16
12
RL = 350 Ω
*All typical values at TA = 25°C, VCC = 5 V.
Common Mode Transient Immunity Specifications, All values at T = 25°C
A
Parameter
Device
Symbol Min. Typ. Max. Units
Test Conditions
Fig. Note
Output High
Level Common HCPL-061A
Mode Transient HCPL-263A
HCPL-261A |CMH|
1
5
kV/µs VCM = 50 V
V
CC = 5.0 V,
17 4, 13,
15, 18
RL = 350 Ω,
IF = 0 mA,
TA = 25°C
VO(MIN) = 2 V
Immunity
HCPL-063A
HCPL-261N
HCPL-061N
1
15
1
5
25
5
kV/µs VCM = 1000 V
kV/µs
HCPL-263N
HCPL-063N
Using Agilent
App Circuit
20 4, 13,
15
Output Low
Level Common HCPL-061A
Mode Transient HCPL-263A
HCPL-261A |CML|
kV/µs VCM = 50 V
VCC = 5.0 V,
17 4, 14,
15, 18
RL = 350 Ω,
IF = 3.5 mA,
Immunity
HCPL-063A
VO(MAX) = 0.8 V
TA = 25°C
HCPL-261N
HCPL-061N
1
5
kV/µs VCM = 1000 V
kV/µs
HCPL-263N
HCPL-063N
15
25
Using Agilent
App Circuit
20 4, 14,
15
9
Package Characteristics
All Typicals at TA = 25°C
Parameter
Sym.
Package*
Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output
Momentary With-
stand Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage Current
Resistance
V
2500
V rms RH ≤ 50%,
5, 6
5, 7
4, 8
ISO
t = 1 min.,
OPT 020†
5000
T = 25°C
A
RI-O
CI-O
II-I
1012
0.6
Ω
VI-O = 500 Vdc
pF
µA
f = 1 MHz,
4, 8
19
T = 25°C
A
Dual Channel
Dual Channel
0.005
RH ≤ 45%,
t = 5 s,
V = 500 V
I-I
RI-I
1011
Ω
19
19
(Input-Input)
Capacitance
(Input-Input)
CI-I Dual 8-pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
*Ratings apply to all devices except otherwise noted in the Package column.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.
Notes:
14. Common mode transient immunity in
a Logic Low level is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state (i.e., VO < 0.8 V).
8. Measured between the LED anode and
cathode shorted together and pins 5
through 8 shorted together.
9. The tPLH propagation delay is
measured from the 1.75 mA point on
the falling edge of the input pulse to
the 1.5 V point on the rising edge of
the output pulse.
10. The tPHL propagation delay is
measured from the 1.75 mA point on
the rising edge of the input pulse to
the 1.5 V point on the falling edge of
the output pulse.
11. Propagation delay skew (tPSK) is
equal to the worst case difference in
tPLH and/or tPHL that will be seen
between any two units under the
same test conditions and operating
temperature.
1. Peaking circuits may be used which
produce transient input currents up
to 30 mA, 50 ns maximum pulse
width, provided the average current
does not exceed 10 mA.
2. 1 minute maximum.
15. For sinusoidal voltages
3. Derate linearly above 80°C free-air
temperature at a rate of 2.7 mW/°C
for the SOIC-8 package.
(|dVCM/dt|)max = πfCM VCM(P-P)
.
16. Bypassing of the power supply line is
required with a 0.1 µF ceramic disc
capacitor adjacent to each optocoup-
ler as shown in Figure 19. Total lead
length between both ends of the
capacitor and the isolator pins should
not exceed 10 mm.
17. Pulse Width Distortion (PWD) is
defined as the difference between
tPLH and tPHL for any given device.
18. No external pull up is required for a
high logic state on the enable input of
a single channel product. If the VE pin
is not used, tying VE to VCC will result
in improved CMR performance.
19. Measured between pins 1 and 2
shorted together, and pins 3 and 4
shorted together. For dual channel
parts only.
4. Each channel.
5. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
6. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristics
Table, if applicable.
7. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 6000 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
12. Single channel products only (HCPL-
261A/261N/061A/061N).
13. Common mode transient immunity in
a Logic High level is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., Vo > 2.0 V).
10
15
10
80
100.0
V
V
V
V
= 5.5 V
= 5.5 V
= 2 V
V
V
V
I
= 5 V
= 2 V
= 0.6 V
= 3.5 mA
CC
CC
E
OL
F
O
E
F
= 0.8 V
60
40
10.0
1.0
T
= 85 °C
A
T
T
= 40 °C
= 25 °C
A
A
5
0
20
0
0.1
I
+
F
V
F
–
0.01
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
1.0
1.1
V – FORWARD VOLTAGE – V
F
1.2
1.3
1.4
1.5
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 4. Typical High Level Output
Current vs. Temperature.
Figure 5. Low Level Output Current
vs. Temperature.
Figure 6. Typical Diode Input
Forward Current Characteristic.
HCPL-261A fig 5
0.6
5.0
4.0
V
V
I
= 5.5 V
CC
= 2 V
E
= 3.0 mA
F
0.5
R
= 350 Ω
L
I
I
= 16 mA
O
O
3.0
2.0
= 12.8 mA
R
= 1 kΩ
L
0.4
0.3
0.2
R
= 4 kΩ
L
I
I
= 9.6 mA
= 6.4 mA
1.0
0
O
O
-60 -40 -20
0
20 40 60 80 100
0
I
0.5
1.0
1.5
2.0
T
– TEMPERATURE – °C
– FORWARD INPUT CURRENT – mA
A
F
Figure 7. Typical Output Voltage vs.
Forward Input Current.
Figure 8. Typical Low Level Output
Voltage vs. Temperature.
HCPL-261A/261N
+5 V
I
F
PULSE GEN.
= 50 Ω
1
2
3
4
V
8
CC
Z
O
t
= t = 5 ns
r
f
0.1 µF
BYPASS
R
7
6
5
L
OUTPUT V
INPUT
MONITORING
NODE
O
MONITORING
NODE
*C
L
R
M
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
V
OH
I
= 3.5 mA
F
90%
90%
INPUT
I
= 1.75 mA
I
F
F
10%
10%
t
t
PHL
PLH
V
OL
OUTPUT
V
O
t
rise
t
fall
1.5 V
Figure 9. Test Circuit for tPHL and tPLH
.
11
2.0
1.5
120
120
TPLH
= 4 k
TPLH
R = 4 kΩ
L
R
L
100
80
100
80
R
R
= 350 Ω
= 1 kΩ
L
TPLH
= 1 kΩ
L
R
TPLH
= 1 k
L
60
1.0
0.5
0
60
R
L
TPLH
= 350 Ω
TPHL
= 350 Ω, 1 kΩ, 4 kΩ
R
40
R
= 4 kΩ
40
L
L
TPHL
= 350 Ω, 1 kΩ, 4 kΩ
R
L
R
L
TPLH
= 350 k
V
V
= 5 V
20
0
20
0
CC
= 0.6 V
R
L
V
I
= 5 V
V
T
= 5 V
= 25 °C
CC
= 3.5 mA
CC
A
O
F
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
0
2
4
6
8
10
12
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
I
– PULSE INPUT CURRENT – mA
A
A
F
Figure 12. Typical Propagation Delay
vs. Pulse Input Current.
Figure 10. Typical Input Threshold
Current vs. Temperature.
Figure 11. Typical Propagation Delay
vs. Temperature.
60
160
V
I
= 5 V
t
t
CC
= 3.5 mA
rise
fall
R
= 4 kΩ
L
F
50
40
30
20
140
120
60
V
= 5 V
= 3.5 mA
CC
R
= 4 kΩ
L
I
F
R
R
= 1 kΩ
L
40
= 350 Ω
L
R
= 1 kΩ
L
10
0
20
0
R
= 350 Ω
L
R
= 350 Ω, 1 kΩ, 4 kΩ
L
0
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
20 40 60 80 100
T
– TEMPERATURE – °C
T – TEMPERATURE – °C
A
A
Figure 13. Typical Pulse Width
Distortion vs. Temperature.
Figure 14. Typical Rise and Fall Time
vs. Temperature.
12
120
PULSE GEN.
= 50 Ω
V
V
V
I
= 5 V
= 3 V
= 0 V
CC
EH
EL
Z
O
t
= t = 5 ns
r
f
INPUT
V
E
= 3.5 mA
MONITORING NODE
HCPL-261A/261N
V
F
90
60
t
, R = 4 kΩ
L
ELH
+5 V
1
2
3
4
8
7
6
5
CC
t
, R = 1 kΩ
ELH
L
3.5 mA
0.1 µF
BYPASS
R
L
I
F
30
0
t
, R = 350 Ω
ELH
L
OUTPUT V
MONITORING
NODE
O
t
, R = 350 Ω, 1k Ω, 4 kΩ
L
EHL
*C
L
-60 -40 -20
0
20 40 60 80 100
GND
T
– TEMPERATURE – °C
A
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
Figure 16. Typical Enable Propaga-
tion Delay vs. Temperature. HCPL-
261A/-261N/-061A/-061N Only.
PROBE AND STRAY WIRING CAPACITANCE.
3.0 V
1.5 V
INPUT
V
E
t
t
EHL
ELH
OUTPUT
V
O
1.5 V
Figure 15. Test Circuit for tEHL and tELH
.
HCPL-261A/261N OPTION 060 ONLY
800
P
(mW)
S
700
600
500
400
300
200
100
0
I
(mA)
S
HCPL-261A/261N
1
2
3
4
V
8
+5 V
CC
V
0.1 µF
BYPASS
CM
350 Ω
OUTPUT V
7
6
5
I
F
O
MONITORING
NODE
A
B
V
GND
FF
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
T
S
_
+
PULSE GEN.
Z
= 50 Ω
O
Figure 18. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
V
(PEAK)
CM
V
CM
0 V
5 V
SWITCH AT A:
SWITCH AT B:
I
= 0 mA
F
CM
CM
H
V
O
V
(min.)
(max.)
O
I
= 3.5 mA
F
V
O
V
O
0.5 V
L
Figure 17. Test Circuit for Common Mode Transient Immunity and
Typical Waveforms.
13
SINGLE CHANNEL PRODUCTS
Application Information
Common-Mode Rejection for
HCPL-261A/HCPL-261N
Families:
Figure 20 shows the recom-
mended drive circuit for the
HCPL-261N/-261A for optimal
common-mode rejection
performance. Two main points to
note are:
GND BUS (BACK)
V
BUS (FRONT)
N.C.
CC
ENABLE
(IF USED)
0.1µF
OUTPUT 1
N.C.
N.C.
1. The enable pin is tied to VCC
rather than floating (this
applies to single-channel parts
only).
ENABLE
(IF USED)
0.1µF
2. Two LED-current setting
resistors are used instead of
one. This is to balance ILED
variation during common-
mode transients.
N.C.
OUTPUT 2
10 mm MAX. (SEE NOTE 16)
DUAL CHANNEL PRODUCTS
If the enable pin is left floating, it
is possible for common-mode
transients to couple to the enable
pin, resulting in common-mode
failure. This failure mechanism
only occurs when the LED is on
and the output is in the Low
State. It is identified as occurring
when the transient output voltage
rises above 0.8 V. Therefore, the
enable pin should be connected
to either VCC or logic-level high
for best common-mode
GND BUS (BACK)
V
BUS (FRONT)
CC
OUTPUT 1
OUTPUT 2
0.1µF
10 mm MAX. (SEE NOTE 16)
performance with the output low
(CMRL). This failure mechanism
is only present in single-channel
parts (HCPL-261N, -261A,
-061N, -061A) which have the
enable function.
Figure 19. Recommended Printed Circuit Board Layout.
HCPL-261A/261N
*
1
8
7
V
V
V
CC
CC+
0.01 µF
357 Ω
(MAX.)
350 Ω
2
3
4
Also, common-mode transients
can capacitively couple from the
LED anode (or cathode) to the
output-side ground causing
current to be shunted away from
the LED (which can be bad if the
LED is on) or conversely cause
current to be injected into the
LED (bad if the LED is meant to
be off). Figure 21 shows the
parasitic capacitances which
exists between LED
357 Ω
(MAX.)
6
5
O
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
GND
SHIELD
*
GND1
GND2
*
HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
Figure 20. Recommended Drive Circuit for HCPL-261A/-261N Families for High-
CMR (Similar for HCPL-263A/-263N).
*Higher CMR May Be Obtainable by Connecting Pins 1, 4 to Input Ground (Gnd1).
14
anode/cathode and output ground
(CLA and CLC). Also shown in
Figure 21 on the input side is an
AC-equivalent circuit. Table 1
indicates the directions of ILP and
ILN flow depending on the
direction of the common-mode
transient.
CMR with Other Drive
Circuits
CMR performance with drive
circuits other than that shown in
Figure 20 may be enhanced by
following these guidelines:
circuit which can be used with
any totem-pole-output TTL/
LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the
circuit to be used with logic
devices which have low current-
sinking capability. It also helps
maintain the driving-gate power-
supply current at a constant level
to minimize ground shifting for
other devices connected to the
input-supply ground.
1. Use of drive circuits where
current is shunted from the
LED in the LED “off” state (as
shown in Figures 22 and 23).
This is beneficial for good
CMRH.
For transients occurring when the
LED is on, common-mode rejec-
tion (CMRL, since the output is in
the “low” state) depends upon the
amount of LED current drive (IF).
For conditions where IF is close
to the switching threshold (ITH),
CMRL also depends on the extent
which ILP and ILN balance each
other. In other words, any
condition where common-mode
transients cause a momentary
decrease in IF (i.e. when
dVCM/dt>0 and |IFP| > |IFN|,
referring to Table 1) will cause
common-mode failure for
2. Use of IFH > 3.5 mA. This is
good for high CMRL.
When using an open-collector
TTL or open-drain CMOS logic
gate, the circuit in Figure 23 may
be used. When using a CMOS
gate to drive the optocoupler, the
circuit shown in Figure 24 may
be used. The diode in parallel
with the RLED speeds the turn-off
of the optocoupler LED.
Using any one of the drive
circuits in Figures 22-24 with
IF = 10 mA will result in a typical
CMR of 8 kV/µs for the HCPL-
261N family, as long as the PC
board layout practices are
followed. Figure 22 shows a
1
2
8
7
V
+
CC
transients which are fast enough.
1/2 R
1/2 R
0.01 µF
LED
350 Ω
Likewise for common-mode
transients which occur when the
LED is off (i.e. CMRH, since the
output is “high”), if an imbalance
between ILP and ILN results in a
transient IF equal to or greater
than the switching threshold of
the optocoupler, the transient
“signal” may cause the output to
spike below 2 V (which consti-
tutes a CMRH failure).
I
LP
LED
C
I
LA
LN
3
4
6
5
V
O
15 pF
C
LC
GND
SHIELD
+
–
V
CM
Figure 21. AC Equivalent Circuit for HCPL-261X.
V
CC
By using the recommended
circuit in Figure 20, good CMR
can be achieved. (In the case of
the -261N families, a minimum
CMR of 15 kV/µs is guaranteed
using this circuit.) The balanced
ILED-setting resistors help equalize
ILP and ILN to reduce the amount
by which ILED is modulated from
transient coupling through CLA
and CLC.
HCPL-261X
1
2
420 Ω
(MAX)
2N3906
(ANY PNP)
74L504
(ANY
TTL/CMOS
GATE)
LED
3
4
Figure 22. TTL Interface Circuit for the HCPL-261A/-
261N Families.
15
V
CC
V
CC
HCPL-261X
HCPL-261A/261N
1
2
1N4148
1
2
820 Ω
750 Ω
74HC00
(OR ANY
74HC04
(OR ANY
LED
LED
OPEN-COLLECTOR/
OPEN-DRAIN
TOTEM-POLE
OUTPUT LOGIC
GATE)
3
4
3
4
LOGIC GATE)
Figure 23. TTL Open-Collector/Open Drain Gate Drive Circuit
for HCPL-261A/-261N Families.
Figure 24. CMOS Gate Drive Circuit for HCPL-261A/-
261N Families.
Table 1. Effects of Common Mode Pulse Direction on Transient ILED
If |ILP| < |ILN|,
LED IF Current
Is Momentarily:
If |ILP| > |ILN|,
LED IF Current
Is Momentarily:
If dVCM/dt Is:
then ILP Flows:
and ILN Flows:
positive (>0)
away from LED
away from LED
increased
decreased
anode through CLA
cathode through CLC
negative (<0)
toward LED
toward LED
decreased
increased
anode through CLA
cathode through CLC
Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
maximum rate at which parallel
data can be sent through the
optocouplers.
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically,
PWD on the order of 20-30% of
the minimum pulse width is
tolerable; the exact figure
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
Propagation delay skew is defined
as the difference between the
minimum and maximum propaga-
tion delays, either tPLH or tPHL, for
any given group of optocouplers
which are operating under the
same conditions (i.e., the same
drive current, supply voltage,
output load, and operating
temperature). As illustrated in
Figure 25, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, tPSK is the difference
tion delay from low to high (tPLH
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 9).
)
depends on the particular appli-
cation (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is
an important parameter to con-
sider in parallel data applications
where synchronization of signals
on parallel data lines is a con-
cern. If the parallel data is being
sent through a group of opto-
couplers, differences in propaga-
tion delays will cause the data to
arrive at the outputs of the opto-
couplers at different times. If this
difference in propagation delay is
large enough it will determine the
between the shortest propagation
delay, either tPLH or tPHL, and the
longest propagation delay, either
Pulse-width distortion (PWD)
results when tPLH and tPHL differ
in value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
tPLH or tPHL
.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 26
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
I
F
50%
50%
1.5 V
V
O
TPHL
TPLH
I
F
V
1.5 V
O
t
PSK
Figure 25. Illustration of Propagation Delay Skew – tPSK
.
Propagation delay skew repre-
sents the uncertainty of where an
edge might be after being sent
through an optocoupler. Figure
26 shows that there will be
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncer-
tainty not overlap, otherwise the
clock signal might arrive before
all of the data outputs have
settled, or some of the data
outputs may start to change
before the clock signal has
DATA
INPUTS
CLOCK
DATA
OUTPUTS
t
PSK
CLOCK
t
PSK
arrived. From these considera-
tions, the absolute minimum
pulse width that can be sent
through optocouplers in a parallel
application is twice tPSK. A
Figure 26. Parallel Data Transmission Example.
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
The tPSK specified optocouplers
offer the advantages of guaran-
teed specifications for propaga-
tion delays, pulse-width
distortion, and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5965-3593E
5968-1087E (11/99)
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