ACPL-P343-560E [AVAGO]
4.0 Amp Output Current IGBT Gate Drive Optocoupler; 4.0安培输出电流IGBT栅极驱动光电耦合器
| 型号： | ACPL-P343-560E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 4.0 Amp Output Current IGBT Gate Drive Optocoupler |
| 文件： | 总20页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-P343 and ACPL-W343
4.0 Amp Output Current IGBT Gate Drive Optocoupler
with Rail-to-Rail Output Voltage in Stretched SO6
Data Sheet
Description
Features
The ACPL-P343/W343 contains an AlGaAs LED, which is 4.0 A maximum peak output current
optically coupled to an integrated circuit with a power
output stage. This optocoupler is ideally suited for driving
power IGBTs and MOSFETs used in motor control inverter
3.0 A minimum peak output current
Rail-to-rail output voltage
applications. The high operating voltage range of the 200 ns maximum propagation delay
output stage provides the drive voltages required by gate
controlled devices. The voltage and high peak output
current supplied by this optocoupler make it ideally
100 ns maximum propagation delay difference
LED current input with hysteresis
suited for direct driving IGBT with ratings up to 1200 V 35 kV/s minimum Common Mode Rejection (CMR) at
/ 200 A. For IGBTs with higher ratings, this optocoupler
can be used to drive a discrete power stage which drives
the IGBT gate. The ACPL-P343 and ACPL-W343 have the
V
= 1500 V
CM
I = 3.0 mA maximum supply current
CC
Under Voltage Lock-Out protection (UVLO) with
highest insulation voltage of V
= 891 V and V
peak IORM
IORM
hysteresis
= 1140 V
respectively in the IEC/EN/DIN EN 60747-5-2.
peak
Wide operating V Range: 15 to 30 V
CC
Functional Diagram
Industrial temperature range: -40° C to 105° C
Safety Approval:
ANODE
1
6
5
4
VCC
– UL Recognized 3750/5000 V
for 1 min.
RMS
– CSA
– IEC/EN/DIN EN 60747-5-2 V
= 891/1140 V
IORM
peak
NC
2
3
VOUT
Applications
CATHODE
VEE
IGBT/MOSFET gate drive
AC and Brushless DC motor drives
Renewable energy inverters
Industrial inverters
Note: A 1 F bypass capacitor must be connected between
pins V and V
.
CC
EE
Truth Table
Switching power supplies
V
– V
V – V
CC EE
CC
EE
“POSITIVE GOING”
(i.e., TURN-ON)
0 – 30 V
“NEGATIVE GOING”
(i.e., TURN-OFF)
0 – 30 V
LED
OFF
ON
ON
ON
V
O
LOW
LOW
0 – 12.1 V
12.1 – 13.5 V
13.5 – 30 V
0 – 11.1 V
11.1 – 12.4 V
12.4 – 30 V
TRANSITION
HIGH
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P343 is UL Recognized with 3750 V
ACPL-W343 is UL Recognized with 5000 V
for 1 minute per UL1577.
RMS
for 1 minute per UL1577.
RMS
Option
IEC/EN/DIN
Part number
RoHS Compliant
-000E
Package
Surface Mount
Tape & Reel
EN 60747-5-2
Quantity
ACPL-P343
ACPL-W343
Stretched
SO-6
X
X
X
X
100 per tube
1000 per reel
100 per tube
1000 per reel
-500E
X
X
-060E
X
X
-560E
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P343-560E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-W343-000E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-P343 Stretched SO-6 Package (7 mm clearance)
4.580 –+ 0.254
Land Pattern Recommendation
0
1.27 (0.050) BSG
0.381 0.127
(0.015 0.005)
0.180 + 0.010
(
)
–
0.000
0.76 (0.03)
1.27 (0.05)
2.16
(0.085)
10.7
(0.421)
7.62 (0.300)
6.81 (0.268)
1.590 0.127
(0.063 0.005)
3.180 0.127
(0.125 0.005)
0.45 (0.018)
45°
7°
7°
7°
0.254 0.050
(0.010 0.002)
0.20 0.10
(0.008 0.004)
7°
1
0.250
5° NOM.
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
(0.040 0.010)
9.7 0.250
(0.382 0.010)
Lead Coplanarity = 0.1 mm (0.004 Inches)
ACPL-W343 Stretched SO-6 Package (8 mm clearance)
4.580 –+ 0.254
0
0.180 + 0.010
(
)
–
0.000
Land Pattern Recommendation
1.27 (0.050) BSG
0.381 0.127
0.76 (0.03)
1.27 (0.05)
(0.015 0.005)
1
2
3
6
5
4
1.905
(0.075)
7.62 (0.300)
6.807 –+ 0.127
12.65
(0.5)
0
0.268 + 0.005
(
)
–
0.000
1.590 0.127
(0.063 0.005)
3.180 0.127
(0.125 0.005)
45°
0.45 (0.018)
7°
7°
0.20 0.10
(0.008 0.004)
0.254 0.050
(0.010 0.002)
0.750 0.250
(0.0295 0.010)
35° NOM.
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
11.500 0.25
(0.453 0.010)
Lead Coplanarity = 0.1 mm (0.004 Inches)
3
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.
Regulatory Information
The ACPL-P343/W343 is approved by the following organizations:
UL
Recognized under UL 1577, component recognition program up to V = 3750 V
(ACPL-P343) and V = 5000 V
ISO RMS
ISO
RMS
(ACPL-W343) expected prior to product release.
CSA
CSA Component Acceptance Notice #5, File CA 88324
IEC/EN/DIN EN 60747-5-2 (Option 060 Only)
Maximum Working Insulation Voltage V
= 891 V
(ACPL-P343) and V
= 1140 V (ACPL-W343)
peak
IORM
peak
IORM
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* (Option 060 – Under Evaluation)
ACPL-P343
ACPL-W343
Option 060
Description
Symbol
Option 060
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
I – IV
I – IV
I – III
I – III
I – IV
I – IV
I – IV
I – IV
I – III
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
Climatic Classification
55/100/21
55/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
2
VIORM
VPR
891
1671
1140
2137
Vpeak
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VPR
1426
6000
1824
8000
Vpeak
V
IORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
Highest Allowable Overvoltage
VIOTM
Vpeak
(Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in the event
of a failure.
TS
175
230
600
175
230
600
°C
mA
mW
Case Temperature
Input Current
Output Power
IS, INPUT
PS, OUTPUT
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
Note:
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-P343
ACPL-W343
Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
CTI
8.0
8.0
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
>175
IIIa
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Notes:
Material Group (DIN VDE 0110, 1/89, Table 1)
1. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board,
minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance
path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended
Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which
may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending
on factors such as pollution degree and insulation level.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
-55
-40
Max.
125
105
125
25
Units
°C
Note
Storage Temperature
Operating Temperature
Output IC Junction Temperature
Average Input Current
TA
°C
TJ
°C
IFꢀAVGꢁ
IFꢀTRANꢁ
mA
A
1
Peak Transient Input Current
1
(<1 s pulse width, 300 pps)
Reverse Input Voltage
VR
5
V
“High”Peak Output Current
“Low”Peak Output Current
Total Output Supply Voltage
Input Current (Rise/Fall Time)
Output Voltage
IOH(PEAK)
IOL(PEAK)
(VCC - VEE
4.0
4.0
35
A
2
2
A
)
0
V
tr(IN) / tf(IN)
VO(PEAK)
PO
500
VCC
700
745
ns
V
-0.5
Output IC Power Dissipation
Total Power Dissipation
Lead Solder Temperature
mW
mW
3
4
PT
260° C for 10 sec., 1.6 mm below seating plane
Table 4. Recommended Operating Conditions
Parameter
Symbol
TA
Min.
-40
15
Max.
105
30
Units
°C
Note
Operating Temperature
Output Supply Voltage
Input Current (ON)
Input Voltage (OFF)
(VCC - VEE
IF(ON)
)
V
7
16
mA
V
VF(OFF)
-3.6
0.8
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values are at T = 25° C, V - V = 30 V, V = Ground; all minimum and maximum
A
CC
EE
EE
specifications are at recommended operating conditions (T = -40 to 105° C, I
= 7 to 16 mA, V
= -3.6 to 0.8 V,
A
F(ON)
F(OFF)
V
= Ground, V = 15 to 30 V).
EE
CC
Parameter
Symbol
Min.
-1.0
-3.0
1.0
Typ.
Max.
Units
A
Test Conditions
VO = VCC – 4 V
VCC - VO ≤ 15 V
VO = VEE + 2.5 V
VO - VEE ≤ 15 V
IOH = -3.0 A
Fig.
Note
High Level Peak Output
Current
IOH
-2.8
3, 4, 20
5
6
5
7
8
A
Low Level Peak Output
Current
IOL
3.5
A
6, 7, 21
3.0
A
High Output Transistor
RDS(ON)
RDS,OH
RDS,OL
1.4
0.6
2.5
1.5
8
9
Low Output Transistor
RDS(ON)
IOL = 3.0 A
8
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Supply Current
VOH
VOH
VOL
ICCH
Vcc – 0.3 Vcc – 0.2
V
IO = -100 mA
2, 4, 22
1
9, 10
Vcc
0.1
1.9
V
IO = 0 mA, IF = 10 mA
IO = 100 mA
0.2
3.0
V
5, 7, 23
10, 11
mA
Rg = 10 ,
Cg = 25 nF, IF = 10 mA
Low Level Supply Current
ICCL
IFLH
VFHL
1.9
3.0
4.0
mA
mA
V
Rg = 10 ,
Cg = 25 nF, VF = 0 V
Threshold Input Current
Low to High
1.5
Rg = 10 ,
Cg = 25 nF, VO > 5 V
12, 13, 24
19
Threshold Input Voltage
High to Low
0.8
Input Forward Voltage
VF
1.2
1.55
-1.7
1.95
V
IF = 10 mA
Temperature Coefficient
of Input Forward Voltage
VF/TA
mV/°C IF = 10 mA
Input Reverse Breakdown
Voltage
BVR
5
V
IR = 100 A
Input Capacitance
UVLO Threshold
CIN
70
pF
V
f = 1 MHz, VF = 0 V
VO > 5 V, IF = 10 mA
VUVLO+
VUVLO-
12.1
11.1
12.8
11.8
13.5
12.4
25
UVLO Hysteresis
UVLOHYS
1.0
V
6
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values are at T = 25° C, V - V = 30 V, V = Ground; all minimum and maximum
A
CC
EE
EE
specifications are at recommended operating conditions (T = -40 to 105° C, I
= 7 to 16 mA, V
= -3.6 to 0.8 V,
A
F(ON)
F(OFF)
V
= Ground, V = 15 to 30 V).
EE
CC
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time to
High Output Level
tPLH
50
98
200
ns
Rg = 10 , Cg = 25 nF,
f = 20 kHz,
Duty Cycle = 50%,
IF = 7 mA to 16 mA,
VCC = 15 V to 30 V
14, 15,
16, 17,
18, 26
Propagation Delay Time to
Low Output Level
tPHL
50
95
22
200
ns
Pulse Width Distortion
PWD
70
ns
ns
11
12
Propagation Delay Difference
Between Any Two Parts
PDD
(tPHL - tPLH
-100
100
33, 34
26
)
Rise Time
Fall Time
tR
43
40
50
ns
Vcc = 30 V
tF
ns
Output High Level Common
Mode Transient Immunity
|CMH|
35
35
kV/s
TA = 25° C, IF = 10 mA,
VCC = 30 V, VCM = 1500 V
with split resistors
27
13, 14
13, 15
Output Low Level Common
Mode Transient Immunity
|CML|
50
kV/s
TA = 25° C, VF = 0 V,
VCC = 30 V, VCM = 1500 V
with split resistors
Table 7. Package Characteristics
Unless otherwise noted, all typical values are at T = 25° C; all minimum/maximum specifications are at recommended
A
operating conditions.
Parameter
Symbol
Device
Min. Typ.
Max. Units Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
VISO
ACPL-P343 3750
VRMS RH < 50%, t = 1 min.,
TA = 25° C
16,18
ACPL-W343 5000
VRMS RH < 50%, t = 1 min.,
TA = 25° C
17,18
18
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
R11
>5012
0.6
V
I-O = 500 VDC
pF
f =1 MHz
LED-to-Ambient Thermal
Resistance
135
°C/W
19
LED-to-Detector Thermal
Resistance
R12
R21
R22
27
39
47
Detector-to-LED Thermal
Resistance
Detector-to-Ambient
Thermal Resistance
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074
entitled “Optocoupler Input-Output Endurance Voltage.”
7
Notes:
1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 s.This value is intended to allow for component tolerances for designs with I peak minimum = 3.0 A. See applications
O
section for additional details on limiting I peak.
OH
3. Derate linearly above 85° C free-air temperature at a rate of 16.9 mW/°C .
4. Derate linearly above 85° C free-air temperature at a rate of 15.3 mW/°C . The maximum LED junction temperature should not exceed 125° C.
5. Maximum pulse width = 50 s.
6. Output is sourced at -3.0 A with a maximum pulse width = 10 s. V -V is measured to ensure 15 V or below.
CC
O
7. Output is sourced at 3.0 A with a maximum pulse width = 10 s. V -V is measured to ensure 15 V or below.
O
EE
8. Output is sourced at -3.0 A/3.0 A with a maximum pulse width = 10 s.
9. In this test V is measured with a DC load current. When driving capacitive loads, V will approach V as I approaches zero amps.
OH
OH
CC
OH
10. Maximum pulse width = 1 ms.
11. Pulse Width Distortion (PWD) is defined as |t -t | for any given device.
PHL PLH
12. The difference between t
and t
between any two ACPL-P343 parts under the same test condition.
PHL
PLH
13. Pin 2 needs to be connected to LED common.
14. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in the high state (i.e., V > 15.0 V).
O
15. Common mode transient immunity in a low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the output
CM
CM
will remain in a low state (i.e., V < 1.0 V).
16. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 4500 V
O
for 1 second (leakage detection
RMS
current limit, I < 5 A).
I-O
17. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 6000 V
for 1 second (leakage detection
RMS
current limit, I < 5 A).
I-O
18. Device considered a two-terminal device: pins 1, 2, and 3 shorted together and pins 4, 5 and 6 shorted together.
19. The device was mounted on a high conductivity test board as per JEDEC 51-7
8
29.84
29.83
29.82
29.81
29.8
0
-0.05
-0.1
IF = 7 to 16 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
IF = 10 mA
IOUT = 0 mA
VCC = 30 V
VEE = 0 V
-0.15
-0.2
29.79
29.78
29.77
-0.25
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 1. High output rail voltage vs. temperature
Figure 2. VOH vs. temperature
0.5
0
-0.5
-1
0
-0.5
-1
IF = 7 to 16 mA
VOUT = VCC 4 V
VCC = 15 to 30 V
VEE = 0 V
IF = 7 to 16 mA
VCC = 15 to 30 V
VEE = 0 V
TA = 25° C
-1.5
-2
-1.5
-2
-2.5
-3
-2.5
-3
-3.5
-4
-3.5
-4
-4.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
0
1
2
3
4
5
6
(VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V
Figure 3. IOH vs. temperature
Figure 4. IOH vs. VOH
0.14
0.12
0.1
4.5
4
3.5
3
0.08
0.06
0.04
0.02
0
2.5
2
1.5
1
VF (OFF) = 0 V
VF (OFF) = 0 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
VOUT = 2.5 V
VCC = 15 to 30 V
VEE = 0 V
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
Figure 5.VOL vs. temperature
Figure 6. IOL vs. temperature
9
5
4.5
4
2.5
2
3.5
3
1.5
1
2.5
2
IF = 7 to 16 mA
IOUT = -3 A
VF (OFF) = 0 V
VCC = 15 to 30 V
VEE = 0 V
1.5
1
0.5
0
VCC = 15 to 30 V
VEE = 0 V
0.5
0
TA = 25° C
0
0.5
1
1.5
2
2.5
3
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
VOL - OUTPUT LOW VOLTAGE - V
Figure 7. IOL vs. VOL
Figure 8. RDS,OH vs. temperature
2.5
2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1
VF (OFF) = 0 V
IOUT = 3 A
IF = 10 mA for ICCH
VF = 0 V for ICCL
0.5
ICCH
ICCL
VCC = 15 to 30 V
VEE = 0 V
VCC = 30 V
VEE = 0 V
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 9. RDS,OL vs. temperature
Figure 10. ICC vs. temperature
2.5
2
34
TA = 25° C
VCC = 30 V
VEE = 0 V
29
24
19
14
9
1.5
1
IF = 10 mA for ICCH
VF = 0 V for ICCL
0.5
IFLH ON
IFLH OFF
ICCL
ICCH
TA = 25° C
VEE = 0 V
4
0
-1
15
20
25
30
0
0.5
1
1.5
2
2.5
3
V
CC - SUPPLY VOLTAGE - V
I
FLH - LOW TO HIGH CURRENT THRESHOLD - mA
Figure 11. ICC vs. VCC
Figure 12. IFLH hysteresis
10
2.4
2.2
2
1.8
1.6
1.4
1.2
1
120
110
100
90
IF = 7 mA
0.8
0.6
0.4
0.2
0
80
TA = 25° C
Rg = 10 7, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
TPLH
TPHL
IFLH ON
IFLH OFF
70
VCC = 15 to 30 V
VEE = 0 V
60
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
15
20
25
30
VCC - SUPPLY VOLTAGE - V
Figure 13. IFLH vs. temperature
Figure 14. Propagation delays vs. VCC
120
110
100
90
120
110
100
90
IF = 7 mA
80
VCC = 30 V, VEE = 0 V
80
VCC = 30 V, VEE = 0 V
TA = 25° C
Rg = 10 7, Cg = 25 nF
Rg = 10 7, Cg = 25 nF
TPLH
TPHL
TPLH
TPHL
70
70
DUTY CYCLE = 50%
f = 20 kHz
DUTY CYCLE = 50%
f = 20 kHz
60
60
6
8
10
12
14
16
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
IF - FORWARD LED CURRENT - mA
Figure 15. Propagation delays vs. IF
Figure 16. Propagation delays vs. temperature
105
100
95
110
105
100
95
90
85
80
75
70
65
60
90
85
80
IF = 7 mA, TA = 25° C
IF = 7 mA, TA = 25° C
VCC = 30 V, VEE = 0 V
75
VCC = 30 V, VEE = 0 V
Cg = 25 nF
R
g = 10 7
70
TPLH
TPHL
TPLH
TPHL
DUTY CYCLE = 50%
DUTY CYCLE = 50%
f = 20 kHz
65
f = 20 kHz
60
10
15
20
25
30
35
40
45
50
10
15
20
25
30
35
40
45
50
Cg - SERIES LOAD CAPACITANCE - nF
R
g - SERIES LOAD RESISTANCE - 7
Figure 17. Propagation delay vs. Rg
Figure 18. Propagation delay vs. Cg
11
100
10
1
0.1
1.4
1.45
1.5
1.55
1.6
1.65
VF - FORWARD VOLTAGE - V
Figure 19. Input current vs. forward voltage
4 V Pulsed
1
6
5
4
+
_
IF = 7 to 16 mA
1 MF
V
CC = 15 to 30 V
+
2
_
IOH
3
Figure 20. IOH test circuit
1
6
5
4
1 MF
VCC = 15 to 30 V
+
_
2
3
IOL
+
_
2.5 V Pulsed
Figure 21. IOL test circuit
12
1
6
5
4
IF = 7 to 16 mA
1 MF
VCC = 15 to 30 V
VOH
+
2
3
_
100 mA
Figure 22. VOH test circuit
1
6
5
4
100 mA
1 MF
VCC = 15 to 30 V
+
2
3
_
VOL
Figure 23. VOL test circuit
1
6
5
4
1 MF
VCC = 15 to 30 V
VO > 5 V
IF
+
2
_
10 7
25 nF
3
Figure 24. IFLH test circuit
13
1
6
5
4
IF = 7 to 16 mA
1 MF
VCC
VO > 5 V
+
2
3
_
Figure 25. UVLO test circuit
1
6
5
4
1 MF
VCC = 15 to 30 V
IF = 7 to 16 mA,
20 kHz, 50% Duty Cycle
VO
+
2
3
_
10 7
25 nF
Figure 26. tPHL, tPHL, tr and tf test circuit and waveforms
205 7
1
6
+
1 MF
5 V
VCC = 30 V
_
VO
+
2
3
5
4
_
137 7
10 mA
VCM = 1500 V
Figure 27. CMR test circuit with split resistors network and waveforms
14
Application Information
Product Overview Description
Recommended Application Circuit
The recommended application circuit shown in Figure 28
illustrates a typical gate drive implementation using the
ACPL-P343. The following describes about driving IGBT.
However, it is also applicable to MOSFET. Designers will
The ACPL-P343/W343 is an optically isolated power output
stage capable of driving IGBTs of up to 200 A and 1200 V.
Based on BCDMOS technology, this gate drive optocou-
pler delivers higher peak output current, better rail-to-rail
output voltage performance and two times faster speed
than the previous generation products.
need to adjust the V supply voltage, depending on the
CC
MOSFET or IGBT gate threshold requirements (Recom-
mended V = 15 V for IGBT and 12 V for MOSFET).
CC
The high peak output current and short propagation delay
are needed for fast IGBT switching to reduce dead time
and improve system overall efficiency. Rail-to-rail output
voltage ensures that the IGBT’s gate voltage is driven to
the optimum intended level with no power loss across
IGBT. This helps the designer lower the system power
which is suitable for bootstrap power supply operation.
The supply bypass capacitors (1 F) provide the large
transient currents necessary during a switching transition.
Because of the transient nature of the charging currents, a
low current (3.0 mA) power supply will be enough to power
the device. The split resistors (in the ratio of 1.5:1) across
the LED will provide a high CMR response by providing a
balanced resistance network across the LED.
It has very high CMR(common mode rejection) rating
which allows the microcontroller and the IGBT to operate
at very large common mode noise found in industrial
motor drives and other power switching applications. The
input is driven by direct LED current and has a hysteresis
that prevents output oscillation if insufficient LED driving
current is applied. This will eliminates the need of addi-
tional Schmitt trigger circuit at the input LED.
The gate resistor RG serves to limit gate charge current
and controls the IGBT collector voltage rise and fall times.
In PC board design, care should be taken to avoid routing
the IGBT collector or emitter traces close to the ACPL-P343
input as this can result in unwanted coupling of transient
signals into ACPL-P343 and degrade performance.
The stretched SO6 package which is up to 50% smaller
than conventional DIP package facilitates smaller more
compact design. These stretched packages are compliant
to many industrial safety standards such as IEC/EN/DIN EN
60747-5-2, UL 1577 and CSA.
ANODE
1
VCC
6
R
VCC = 15 V
+
1 MF
Rg
_
+ HVDC
NC
2
VOUT
5
+
+
_
VCE
_
Q1
Q2
3-HVDC
AC
+
_
CATHODE
3
VEE
4
R
VEE = 5 V
+
VCE
_
-HVDC
Figure 28. Recommended application circuit with split resistors LED drive
15
Rail-to-Rail Output
Figure 29 shows a typical gate driver’s high current output ACPL-P343 uses a power PMOS to deliver the large current
stage with 3 bipolar transistors in darlington configuration. and pull it to V to achieve rail-to-rail output voltage
CC
During the output high transition, the output voltage rises
rapidly to within 3 diode drops of V . To ensure the V
as shown in Figure 30. This ensures that the IGBT’s gate
voltage is driven to the optimum intended level with no
CC
OUT
is at V in order to achieve IGBT rated V
voltage. The power loss across IGBT even when an unstable power
CC
CE(ON)
level of V will be need to be raised to beyond V +3(V )
supply is used.
CC
CC
BE
to account for the diode drops. And to limit the output
voltage to V , a pull-down resistor, R between
CC
PULL-DOWN
the output andV is recommended to sink a static current
EE
while the output is high.
VCC
1
2
8
7
ANODE
NC
RG
VOUT
RPULL-DOWN
CATHODE
NC
3
4
6
5
VEE
Figure 29. Typical gate driver with output stage in darlington configuration
ANODE
NC
1
6
5
4
VCC
2
3
VOUT
CATHODE
VEE
Figure 30. ACPL-P343/W343 with PMOS and NMOS output stage for rail-to-rail output voltage
16
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the I peak specification. The IGBT and Rg in Figure 28 can be analyzed as a simple
OL
RC circuit with a voltage supplied by ACPL-P343/W343.
V
I
– V – V
OL
CC
EE
Rg ≥
OLPEAK
15 V + 5 V – 2.9 V
4A
=
= 4.3 5
The V value of 2.9 V in the previous equation is the V at the peak current of 4.0 A (see Figure 7).
OL
OL
Step 1: Check the ACPL-P343/W343 power dissipation and increase Rg if necessary. The ACPL-P343/W343 total power
dissipation (P ) is equal to the sum of the emitter power (P ) and the output power (P ).
T
E
O
P
P
P
= P + P
E O
T
= I • V • Duty Cycle
E
F
F
= P
+ P
O(SWITCHING)
O
O(BIAS)
= I • (V -V ) + E (Rg;Cg) • f
CC
CC EE
SW
Using I (worst case) = 16 mA, Rg = 5 , Max Duty Cycle = 80%, Cg = 25 nF, f = 25 kHz and T max = 85° C:
F
A
P
P
= 16 mA • 1.95 V • 0.8 = 25 mW
= 3 mA • 20 V + 5 J • 25 kHz
= 60 mW + 125 mW
E
O
= 185 mW < 700 mW (P
@ 85° C)
O(MAX)
The value of 3 mA for I in the previous equation is the maximum I over the entire operating temperature range.
CC
CC
Since P is less than P
, Rg = 5 is alright for the power dissipation.
O(MAX)
O
3.0E-05
2.5E-05
2.0E-05
1.5E-05
1.0E-05
5.0E-06
0.0E+00
VCC = 30 V
VCC = 20 V
VCC = 15 V
0
2
4
6
8
10
Rg - Gate Resistance - 7
Figure 31. Energy Dissipated in the ACPL-P343/W343 for each IGBT switching
cycle
17
LED Drive Circuit Considerations for High CMR Performance
Figure 32 shows the recommended drive circuit for the if an imbalance between I and I results in a transient
LP
LN
ACPL-P343/W343 that gives optimum common-mode I equal to or greater than the switching threshold of the
F
rejection. The two current setting resistors balance the optocoupler, the transient “signal” may cause the output
common mode impedances at the LED’s anode and to spike above 1 V, which constitutes a CM failure. The
L
cathode. Common-mode transients can be capacitive balanced I -setting resistors help equalize the common
LED
coupled from the LED anode, through C (or cathode mode voltage change at the anode and cathode. The
LA
through C ) to the output-side ground causing current shunt drive input circuit will also help to achieve high CM
LC
L
to be shunted away from the LED (which is not wanted performance by shunting the LED in the off state.
when the LED should be on) or conversely cause current
to be injected into the LED (which is not wanted when the
LED should be off).
VDD = 5.0 V:
R1 = 205 7 1%
R2 = 137 7 1%
R1/R2 ≈ 1.5
+5 V
Table 8 shows the directions of I and I depend on the
LP
LN
R1
ILP
ANODE
1
polarity of the common-mode transient. For transients
occurring when the LED is on, common-mode rejection
6
5
4
VCC
CLA
(CM , since the output is at “high” state) depends on
H
LED current (I ). For conditions where I is close to the
F
F
2
3
VOUT
switching threshold (I ), CM also depends on the
FLH
H
extent to which I and I balance each other. In other
LP
LN
ILN
CLC
R2
words, any condition where a common-mode transient
causes a momentary decrease in I (i.e. when dV /dt > 0
VEE
F
CM
CATHODE
and |I | > |I |, referring to Table 8) will cause a common-
LP
LN
mode failure for transients which are fast enough.
Likewise for a common-mode transient that occurs when
Figure 32. Recommended high-CMR drive circuit for the ACPL-P343/W343
the LED is off (i.e. CM , since the output is at “low” state),
L
Table 8. Common Mode Pulse Polarity and LED current Transients
If |I | < |I |,
I is momentarily
F
If |I | > |I |,
LP LN
I is momentarily
F
LP
LN
dV /dt
CM
I
Direction
I
Direction
LP
LP
Positive (>0)
Away from LED anode
through CLA
Away from LED cathode
through CLC
Increase
Decrease
Negative(<0)
Toward LED anode
through CLA
Toward LED cathode
through CLC
Decrease
Increase
18
Dead Time and Propagation Delay Specifications
The ACPL-P343/W343 includes a Propagation Delay Dif-
ference (PDD) specification intended to help designers
minimize“dead time”in their power inverter designs. Dead
time is the time period during which both the high and
low side power transistors (Q1 and Q2 in Figure 28) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 34. The maximum dead time for the ACPL-P343/
W343 is 200 ns (= 100 ns – (-100 ns)) over an operating
temperature range of -40° C to 105° C.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 33. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propa-
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
gation delay difference specification, PDD
, which is
MAX
specified to be 100 ns over the operating temperature
range of 40° C to 105° C.
Figure 33. Minimum LED skew for zero dead time
Figure 34. Waveforms for dead time
19
Ambient Temperature: Junction to Ambient Thermal Re-
sistances were measured approximately 1.25 cm above
optocoupler at ~23° C in still air
LED Current Input with Hysteresis
The detector has optical receiver input stage with built in
Schmitt trigger to provide logic compatible waveforms,
eliminating the need for additional wave shaping. The
hysteresis (Figure 12) provides differential mode noise
immunity and minimizes the potential for output signal
chatter.
Thermal Resistance
°C/W
135
27
R11
R12
R21
R22
39
Under Voltage Lockout
47
The ACPL-P343/W343 Under Voltage Lockout (UVLO)
feature is designed to prevent the application of insuffi-
cient gate voltage to the IGBT by forcing the ACPL-P343/
W343 output low during power-up. IGBTs typically require
This thermal model assumes that an 6-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB) per JEDEC standards.
The temperature at the LED and Detector junctions of
the optocoupler can be calculated using the equations
below.
gate voltages of 15 V to achieve their rated V
At gate voltages below 13 V typically, the V
voltage.
voltage
CE(ON)
CE(ON)
increases dramatically, especially at higher currents. At
very low gate voltages (below 10 V), the IGBT may operate
in the linear region and quickly overheat. The UVLO
function causes the output to be clamped whenever
T = (R * P + R * P ) + Ta
(1)
(2)
1
11
1
12
2
T = (R * P + R * P ) + Ta
2
21
1
22
2
insufficient operating supply (V ) is applied. Once V
CC
CC
Using the given thermal resistances and thermal model
formula in this datasheet, we can calculate the junction
temperature for both LED and the output detector. Both
junction temperature should be within the absolute
maximum rating.
exceeds V
(the positive-going UVLO threshold), the
UVLO+
UVLO clamp is released to allow the device output to turn
on in response to input signals.
Thermal Model for ACPL-P343/W343 Stretched SO6
Package Optocoupler
For example, given P = 25 mW, P = 185 mW, Ta = 85° C:
1
2
Definitions:
LED junction temperature,
T = (R * P + R * P ) + Ta
= (135 * 0.025 + 27 * 0.185) + 85
= 93.4° C
R
: Junction to Ambient Thermal Resistance of LED due
1
11
1
12
2
11
to heating of LED
R
: Junction to Ambient Thermal Resistance of LED due
12
to heating of Detector (Output IC)
Output IC junction temperature,
T = (R * P + R * P ) + Ta
= (39 *0.025 + 47 * 0.185) + 85
= 94.7° C
2
21
1
22
2
R
: Junction to Ambient Thermal Resistance of Detector
21
(Output IC) due to heating of LED.
R
22
: Junction to Ambient Thermal Resistance of Detector
T and T should be limited to 125° C based on the board
(Output IC) due to heating of Detector (Output IC).
1
2
layout and part placement.
P : Power dissipation of LED (W).
1
Related Application Noted
P : Power dissipation of Detector / Output IC (W).
2
AN5336 – Gate Drive Optocoupler Basic Design for IGBT/
MOSFET
T : Junction temperature of LED (°C).
1
T : Junction temperature of Detector (°C).
2
AN1043 – Common-Mode Noise: Sources and Solutions
Ta: Ambient temperature.
AV02-0310EN – Plastics Optocouplers Product ESD and
Moisture Sensitivity
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2928EN - November 14, 2011
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