ACPL-5731L-300 [AVAGO]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, HERMETIC SEALED, CERAMIC, DIP-8;
| 型号： | ACPL-5731L-300 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, HERMETIC SEALED, CERAMIC, DIP-8 输出元件 光电 |
| 文件： | 总11页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-570XL, ACPL-573XL, ACPL-177XL, 5962-08227
Hermetically Sealed 3.3V, Low I , Wide V , High Gain Optocouplers
F
CC
Data Sheet
Description
Features
These devices are single, dual, and quad channel, hermeti- Low power consumption
cally sealed optocouplers. The products are capable of
operation and storage over the full military temperature
3.3V Supply voltages
Dual marked with device part number and DLA
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from DLA Drawing 5962-08227. All devices are manufac-
tured and tested on a MIL-PRF-38534 certified line and are
included in the DLA Qualified Products Database Supple-
mental Information Sheets QPDSIS-38534 as Hybrid Mi-
crocircuits.
drawing number
Manufactured and tested on a MIL-PRF-38534 Certified
Line
QPDSIS-38534, Class H and K
Three hermetically sealed package configurations
Performance guaranteed over full military temperature
range: -55°C to +125°C
Each channel contains a GaAsP light emitting diode which
is optically coupled to an integrated high gain photon
detector. The high gain output stage features an open
collector output providing both lower saturation voltage
and higher signaling speed than possible with conven-
tional photo-Darlington optocouplers.
Low input current requirement: 0.5 mA
High current transfer ratio: 1500% typical @ I = 0.5 mA
Low output saturation voltage: 0.11 V typical
1500 Vdc withstand test voltage
HCPL-4701/31, -070A/31 function compatibility
F
The supply voltage can be operated as low as 3.0V without
adversely affecting the parametric performance.
Applications
These devices have a 300% minimum CTR at an input
current of only 0.5 mA making them ideal for use in low
input current applications such as MOS, CMOS, low power
logic interfaces or line receivers.
Military and aerospace
High reliability systems
Telephone ring detection
Microprocessor system interface
Transportation, medical, and life critical systems
Isolated input line receiver
EIA RS-232-C line receiver
Voltage level shifting
Isolated input line receiver
Isolated output line driver
Logic ground isolation
Harsh industrial environments
Current loop receiver
System test equipment isolation
Process control input/output isolation
The connection of a 0.1 F bypass capacitor between V and GND is recommended.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Package styles for these parts are 8 and 16 pin DIP through
hole (case outlines P and E respectively). Devices may be
purchased with a variety of lead bend and plating options.
See Selection Guide table for details. Standard Military
Drawing (SMD) parts are available for each package and
lead style.
Functional Diagram
Multiple Channel Devices Available
8
1
2
7
6
5
Because the same electrical die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operating conditions, electrical specifications, and perfor-
mance characteristics shown in the figures are similar for
all parts except as noted. Additionally, the same package
assembly processes and materials are used in all devices.
These similarities justify the use of a common data base for
die related reliability.
3
4
Truth Table
(Positive Logic)
Input
Output
On (H)
Off (L)
L
H
Selection Guide – Package Styles and Lead Configuration Options
Package
Lead Style
16 Pin DIP
Through Hole
4
8 Pin DIP
Through Hole
1
8 Pin DIP
Through Hole
2
Channels
Common Channel Wiring
Avago Part # & Options
Commercial
VCC, GND
None
VCC, GND
ACPL-1770L
ACPL-1772L
ACPL-177KL
Gold Plate
ACPL-5700L
ACPL-5701L
ACPL-570KL
Gold Plate
ACPL-5730L
ACPL-5731L
ACPL-573KL
Gold Plate
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped*
Option -200
Option -100
Option -300
Option -200
Option -100
Option -300
Option -200
Option -100
Option -300
Butt Cut/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Gold Plate
5962-
5962-
5962-
0822703HEC
0822703HEA
0822703HUC
0822703HUA
0822703HTA
0822701HPC
0822701HPA
0822701HYC
0822701HYA
0822701HXA
0822702HPC
0822702HPA
0822702HYC
0822702HYA
0822702HXA
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Gold Plate
5962-
5962-
5962-
0822703KEC
0822703KEA
0822703KUC
0822703KUA
0822703KTA
0822701KPC
0822701KPA
0822701KYC
0822701KYA
0822701KXA
0822702KPC
0822702KPA
0822702KYC
0822702KYA
0822702KXA
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
* Solder contains lead.
2
Functional Diagrams
16 pin DIP
8 pin DIP
8 pin DIP
Through Hole
4 Channels
Through Hole
1 Channel
Through Hole
2 Channels
16
15
14
13
12
11
10
9
8
8
7
1
2
1
2
1
2
7
6
5
3
4
5
6
3
4
3
4
6
5
7
8
Outline Drawings
16 Pin DIP Through Hole, 4 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Device Marking
8 Pin DIP Through Hole, 1 and 2 Channel
Avago LOGO
Avago P/N
DLA SMD*
DLA SMD*
PIN ONE/
A QYYWWZ
COMPLIANCE INDICATOR,*
V
8
CC
I
XXXXXX
XXXXXXX
XXX XXX
DATE CODE, SUFFIX (IF NEEDED)
I
CC
F
2
+
COUNTRY OF MFR.
Avago CAGE CODE*
ANODE
50434
t
ESD IDENT
V
*QUALIFIED PARTS ONLY
F
I
–
3
O
6
5
CATHODE
V
O
GND
Note: Dimensions in Millimeters (Inches).
3
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on com-
mercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
Note: Dimensions in Millimeters (Inches).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and
16 pin DIP. DLA Drawing part numbers contain provisions for lead finish.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on
commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped
leads.
4.57 (0.180)
MAX.
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
1.07 (0.042)
1.32 (0.052)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Note: Dimensions in Millimeters (Inches).
Solder contains lead.
4
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
-65
-55
Max.
Units
°C
Notes
Storage Temperature
+150
Operating Temperature
TA
+125
°C
Case Temperature
TC
+170
°C
Junction Temperature
TJ
+175
°C
Lead Solder Temperature
260 for 10 sec
°C
Output Current (each channel)
Output Voltage (each channel)
Supply Voltage
IO
40
20
20
50
20
10
5
mA
V
VO
VCC
-0.5
-0.5
1
V
1
2
Output Power Dissipation (each channel)
Peak Input Current (each channel, <1 ms duration)
Average Input Current (each channel)
Reverse Input Voltage (each channel)
Package Power Dissipation (each channel)
mW
mA
mA
V
IF
3
VR
PD
200
mW
8 Pin Ceramic DIP Single Channel Schematic
V
8
CC
I
I
CC
F
2
+
ANODE
V
F
I
–
3
O
6
5
CATHODE
V
O
GND
ESD Classification
(MIL-STD-883, Method 3015)
ACPL-5700L/01L/0KL
ACPL-5730L/31L/3KL
ACPL-1770L/2L/KL
(
(
(
), Class 2
A), Class 3A
B), Class 3B
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
2.0
5
Units
A
mA
V
Input Current, Low Level (Each Channel)
IF(OFF)
IF(ON)
VCC
Input Current, High Level (Each Channel)
Supply Voltage
0.5
3.0
3.0
7.0
7.0
Output Voltage
VO
V
5
Electrical Characteristics, T = -55°C to +125°C, unless otherwise specified
A
Limits
Typ.*
[13]
Group A
Parameter
Symbol
Test Conditions
Subgroup
Min.
Max.
Units
Fig.
Note
Current Transfer
Ratio
CTR
IF = 0.5 mA, VO = 0.4 V,
VCC = 3.0 V
1, 2, 3
300
1500
1300
800
%
3
4, 5
IF = 1.6 mA, VO = 0.4 V,
300
200
V
CC = 3.0 V
IF =5 mA, VO = 0.4 V,
VCC = 3.0 V
Logic Low Output VOL
Voltage
IF = 0.5 mA, IOL = 1.5 mA, 1, 2, 3
CC = 3.0 V
0.05
0.06
0.09
1.0
0.4
0.4
0.4
V
2
4
4
4
V
IF = 1.6 mA, IOL = 4.8 mA,
VCC = 3.0 V
IF =5 mA, IOL = 10 mA,
VCC = 3.0 V
Logic High Output IOH
IF =2 A, VO = 7 V,
1, 2, 3
1, 2, 3
100
100
2
A
A
mA
4
Current
VCC = 7 V
IOHX
4, 6
Logic
Single
ICCL
IF =1.6 mA, VCC = 7 V
0.8
Low
Channel
Supply
Current
Dual
Channel
I
F1 =IF2 = 1.6 mA,
0.8
4
4
VCC = 7 V
Quad
Channel
IF1 = IF2 =IF3 =IF4 =1.6 mA,
VCC = 7 V
1.3
4
Logic
High
Supply
Current
ICCH
IF =0 mA, VCC = 7 V
1, 2, 3
0.01
20
40
A
Single
Channel
I
F1 =IF2 = 0 mA,
CC = 7 V
Dual
Channel
V
Quad
Channel
I
F1 = IF2 =IF3 =IF4 =0 mA,
40
VCC = 7 V
Input
Forward
Voltage
VF
IF = 1.6 mA
1, 2, 3
1, 2, 3
1
1.0
5
1.4
1.8
V
1
4
Input Reverse
Breakdown
Voltage
BVR
II-O
CI-O
IR = 10 A
V
4
Input-Output
Insulation Leakage
Current
≤65% Relative Humidity
TA =25°C, t = 5 s,
VI-O = 1500 VDC
1.0
4
A
pF
7, 12
4, 8, 14
Capacitance
Between
f = 1 MHz, TA =25°C
4
Input-Output
*
All typical values are at V = 3.3 V, T = 25°C.
CC A
6
Electrical Characteristics (cont), T = -55°C to +125°C, unless otherwise specified
A
Limits
Typ.*
[13]
Group A
Parameter
Symbol
Test Conditions
Subgroup
Min.
Max.
Units
Fig.
Note
Propagation Delay tPHL
Time to Logic Low
IF = 0.5 mA, RL = 2.2 k,
VCC = 3.3 V
9, 10, 11
40
100
s
5, 6,
7, 8
4
at Output
tPHL
IF = 1.6 mA, RL = 680 ,
9, 10, 11
9
30
4
4
VCC = 3.3 V
tPHL
IF =5 mA, RL = 330 ,
VCC = 3.3 V
9
2
5
10, 11
9, 10, 11
10
60
Propagation Delay tPLH
Time to Logic High
at Output
IF = 0.5 mA, RL = 2.2 k,
10
8
s
5, 6,
7, 8
4
4
4
V
CC = 3.3 V
tPLH
IF = 1.6 mA, RL = 680 ,
VCC = 3.3 V
9, 10, 11
50
tPLH
IF =5 mA, RL = 330 ,
VCC = 3.3 V
9
6
20
30
10, 11
9, 10, 11
Common Mode
Transient
Immunity at Low
Output Level
|CML|
VCC = 3.3 V, IF = 1.6 mA
RL = 680 k
|VCM|= 50 VP-P
500
500
1000
1000
V/s
V/s
9
9
4, 10
11, 14
Common Mode
Transient
|CMH|
VCC = 3.3 V , IF =0 mA
RL = 680 k
9, 10, 11
4, 10
11, 14
Immunity at High
Output Level
|VCM|= 50 VP-P
*
All typical values are at V = 3.3 V, T = 25°C.
CC A
Typical Characteristics, T =25°C
A
Parameter
Sym.
Typ.
60
Units
Test Conditions
VF =0 V, f = 1 MHz
IF = 1.6 mA
Note
Input Capacitance
CIN
pF
4
4
Input Diode Temperature
Coefficient
VF/TA
-1.8
mV/°C
Resistance (Input-Output)
Capacitance (Input-Output)
Dual and Quad Channel Product Only
Input-Input Leakage Current
RI-O
CI-O
1012
2.0
VI-O = 500 V
f = 1 MHz
4, 8
4, 8
pF
II-I
0.5
nA
Relative Humidity = ≤65%,
I-I = 500 V, t = 5 s
9
V
Resistance (Input-Input)
Capacitance (Input-Input)
RI-I
CI-I
1012
1.0
VI-I = 500 V
f = 1 MHz
9
9
pF
7
Notes:
1. GND Pin should be the most negative voltage at the detector side.
11. In applications where dV/dt may exceed 50,000 V/s (such as
Keeping V as low as possible, but greater than 2.0 V, will provide
a static discharge) a series resistor, R , should be included to
CC
CC
lowest total I over temperature.
protect the detector ICs from destructively high surge currents. The
recommended value is:
OH
2. Output power is collector output power plus total supply power for
the single channel device. For the dual channel device, output power
is collector output power plus one half the total supply power. For
the quad channel device, output power is collector output power
plus one fourth of total supply power. Derate at 1.66 mW/°C above
110°C.
1 (V)
R
=————— k
CC
0.15 I (mA)
F
for single channel;
1 (V)
3. Derate I at 0.33 mA/°C above 110°C.
F
R
=————— k
CC
4. Each channel.
0.3 I (mA)
F
5. CURRENT TRANSFER RATIO is defined as the ratio of output collector
for dual channel;
current, I , to the forward LED input current, I , times 100%.
O
F
1 (V)
6.
I
is the leakage current resulting from channel to channel optical
OHX
R
=————— k
CC
crosstalk. I =2 μA for channel under test. For all other channels,
I =10mA.
F
F
0.6 I (mA)
F
for quad channel.
7. All devices are considered two-terminal devices; measured between
all input leads or terminals shorted together and all output leads or
terminals shorted together.
8. Measured between each input pair shorted together and all output
connections for that channel shorted together.
12. This is a momentary withstand test, not an operating condition.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and
9). SMD and 883B parts receive 100% testing at 25,125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
9. Measured between adjacent input pairs shorted together for each
multi-channel device.
14. Parameters tested as part of device initial characterization and
after design and process changes. Parameters guaranteed to limits
specified for all lots not specifically tested.
10. CM is the maximum rate of rise of the common mode voltage that
L
can be sustained with the output voltage in the logic low state
(V <0.8 V). CM is the maximum rate of fall of the common mode
O
H
voltage that can be sustained with the output voltage in the logic
high state (V > 2.0 V).
O
8
8
7
6
5
4
3
2
1
0
VCC = 3.3V
A = 25°C
T
5.0 mA
4.5 mA
4.0 mA
3.5 mA
3.0 mA
2.5 mA
2.0 mA
1.5 mA
1.0 mA
NOMINALIZED AT:
IO AT IF = 0.5 mA
IF = 0.5 mA
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Vo - OUTPUT VOLTAGE - V
Figure 1. Input Diode Forward Current vs. Forward Voltage.
Figure 2. Normalized DC Transfer Characteristics.
1.5
100
10
NORMINALIZED AT:
TA = 0°C
A = 25°C
CTR AT IF = 0.5 mA
TA = 25°C
T
VCC = 3.3V
VO = 0.4V
1.0
0.5
0.0
V
CC = 18V
TA = 100°C
VCC = 3.3V
T
A = 125°C
1
0.1
NORMINALIZED AT:
ICC AT IF = 1.6 mA
(ALL CHANNELS)
VCC = 18V
TA = 55°C
TA = 25°C
0.01
0.1
1
10
0.1
1
10
100
IF-INPUT DIODE FORWARD CURRENT mA
IF - INPUT DIODE FORWARD CURRENT mA
Figure 3. Normalized Current Transfer Ratio vs. Input Diode Forward Current.
Figure 4. Normalized Supply Current vs. Input Diode Forward Current.
100
10
1
IF = 0.5 mA, RL = 2.2 Kohm
IF = 1.6 mA, RL = 680 ohm
IF = 5.0 mA, RL = 330 ohm
VCC = 3.3V
TA = 25°C
WIDTH = 50 μs
0.1
0.1
1
10
100
T - INPUT PULSE PERIOD ms
Figure 5. Propagation Delay to Logic Low vs. Input Pulse Period.
9
60
50
40
30
20
10
0
45
40
35
30
25
20
15
10
5
IF = 0.5mA, RL = 2.2kohm
IF = 1.6mA, RL = 680ohm
IF = 5.0mA, RL=330ohm
VCC = 3.2V
TA = 25°C
tPHL, RL = 330ohm TO 2.2Kohm
TPHL
TPLH
PULSE WIDTH = 50 s
PERIOD = 10ms
TPLH
TPLH
tPLH, RL = 2.2Kohm
tPLH, RL = 680ohm
tPLH, RL = 330ohm
TPHL
TPHL
0
0
2
4
6
8
10
12
-80 -60 -40 -20
0
20 40 60 80 100 120 140 160
TA - TEMPERATURE°C
IF - INPUT DIODE FORWARD CURRENT mA
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Propagation Delay vs. Input Diode Forward Current.
PULSE GEN.
RCC*
56
IF
Z
O = 50
B
+3 V
VO
tr, tf = 5.0 ns
f = 100 Hz
tPULSE = 0.5ms
RCC*
56
8
1
2
RL
IF
+3 V
VO
1.0 F
A
8
1
2
RL
1.0 F
7
6
5
7
6
5
IF MONITOR
3
4
CL**
Rm
3
4
VFF
VCM
+
–
PULSE GEN.
* SEE NOTE 11
* SEE NOTE 11
** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
Figure 8. Switching Test Circuit.
Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.
10
MIL-PRF-38534 Class H, Class K, and
DLA SMD Test Program
VCC
R1
R2
Avago’s Hi-Rel Optocouplers are in compliance with MIL-
PRF-38534 Class H and K. Class H and Class K devices are
also in compliance with DLA drawing 5962-08227.
ILEAK
8
1
2
Testing consists of 100% screening and quality confor-
mance inspection to MIL-PRF-38534.
2.4 VF
IF
VCC VF IF R2
IF + ILEAK
R2
R1
≥
≤
7
6
5
3
4
VCC + 18 V
8
1
2
VOC
0.01 F
(EACH INPUT)
7
6
5
+
VIN
–
3
4
R2 MAY BE OMITTED
IF ADDITIONAL FANOUT
IS NOT USED.
(EACH OUTPUT)
CONDITIONS: IF = 5 mA
IO = 10 mA
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.
TA = +125°C
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 11. Operating Circuit for Burn-In and Steady State Life Tests.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-1819EN - October 2, 2012
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