ACPL-772L-000E [AVAGO]
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 25Mbps, ROHS COMPLIANT, DIP-8;
| 型号： | ACPL-772L-000E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 25Mbps, ROHS COMPLIANT, DIP-8 输出元件 光电 |
| 文件： | 总11页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-772L and ACPL-072L
3.3V/5V High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
• Dual voltage operation (3.3V and 5V)
Available in either an 8-pin DIP or SO-8 style respectively,
the ACPL-772L or ACPL-072L optocouplers utilize the • Allow level shifting functionality
latest CMOS IC technology to achieve outstanding speed
performance of minimum 25MBd data rate and 6ns
maximum pulse width distortion.
• Support high Speed datarate of 25 MBd
• Wide Temperature operation
• CMOS output and buffer input
Basic building blocks of this family of products are a
CMOS LED driver IC, a high speed LED and a CMOS
detector IC. A CMOS logic input signal controls the LED
driver IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
• Compatible with CMOS and TTL logic level
• Lower power consumption with 3.3V supply
• Good AC performance with lower pulse width
distortion
• Lead-free option available
Specifications
Functional Diagram
• 3.3V and 5V CMOS Compatibility
• High Speed: DC to 25 MBd
**V
DD1
1
2
8
7
V
**
• 6ns max. Pulse Width Distortion
• 40 ns max. Prop. Delay
• 20 ns max. Prop. Delay Skew
• 10 kV/ms min. Common Mode Rejection
• -40 °C to 105 °C Temperature Range
DD2
V
NC*
I
I
O
3
4
6
5
NC*
V
O
LED1
• Safety and Regulatory Approvals:
UL Recognised
GND
GND
1
2
SHIELD
-
5000V for 1 min. per UL1577 for ACPL-772L
rms
for option 020
*
Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed datasheet performance. Pin 7 is not connected
internally.
-
3750V for 1 min. per UL1577 for ACPL-072L
rms
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-2
** A 0.1uF bypass capacitor must be connected between pins 1 and 4,
and 5 and 8.
– V
= 630 V
for ACPL-772L Option 060
IORM
peak
– V
= 560 V
for ACPL-072L Option 060
IORM
peak
TRUTH TABLE (POSITIVE LOGIC)
Applications
V , INPUT
LED1
OFF
ON
V , OUTPUT
I
O
• Digital Fieldbus Isolation: DeviceNet, Profibus, SDS
• Multiplexed Data Transmission
• General Instrument and Data Acquisition
• Computer Peripheral interface
H
L
H
L
• Microprocessor System Interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Device Selection Guide
8-Pin DIP
(300 Mil)
Small Outline
SO-8
ACPL-772L
ACPL-072L
Ordering Information
ACPL-072L and ACPL-772L are UL Recognized with 3750 Vrms for 1 minute per UL1577.
UL 5000
Vrms/ 1
Option
IEC/EN/DIN
EN 60747-
5-2
Part
RoHS
Compliant
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-500E
-060E
-560E
Non RoHS
Compliant
Surface Gull
Tape
& Reel rating
Minute
number
Package
Mount
Wing
Quantity
-
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
-
X
X
X
X
-
X
X
X
-
300mil
DIP-8
ACPL-772L
-
X
X
X
X
-
X
X
-
X
X
X
-
-
X
X
X
X
X
X
X
X
X
X
X
No option
-500
ACPL-072L
SO-8
-060
X
X
-560
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-772L-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-072L to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Dimensions
ACPL-772L 8-Pin DIP Package
9.65 0.25
(0.380 0.010)
7.62 0.25
(0.300 0.010)
OPTION 060 CODE*
DATE CODE
TYPE NUMBER
8
1
7
6
5
6.35 0.25
(0.250 0.010)
A XXXXV
YYWW
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
3.56 0.13
(0.140 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*OPTION 300 AND 500 NOT MARKED.
1.080 0.320
(0.043 0.013)
0.65 (0.025) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 0.25
(0.100 0.010)
ACPL-772L Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 0.25
(0.380 0.010)
1.016 (0.040)
6
8
1
7
5
6.350 0.25
(0.250 0.010)
10.9 (0.430)
3
2
4
2.0 (0.080)
1.27 (0.050)
9.65 0.25
1.780
(0.070)
MAX.
(0.380 0.010)
1.19
(0.047)
MAX.
7.62 0.25
(0.300 0.010)
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 0.320
(0.043 0.013)
0.635 0.25
(0.025 0.010)
12 ° NOM.
0.635 0.130
(0.025 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3
ACPL-072L Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
5.994 0.203
(0.236 0.008)
XXXV
YWW
3.937 0.127
(0.155 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
3
4
PIN ONE
1.9 (0.075)
0.406 0.076
(0.016 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
(0.017)
*
7 °
5.080 0.127
(0.200 0.005)
45 ° X
3.175 0.127
(0.125 0.005)
0 ~ 7 °
0.228 0.025
(0.009 0.001)
1.524
(0.060)
0.203 0.102
(0.008 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 0.254 (0.205 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
4
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1 ˚C/- 0.5 ˚C/SEC.
REFLOW HEATING RATE 2.5˚C 0.5 ˚C/SEC.
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
PEAK
TEMP.
230˚C
200
100
2.5˚ C 0.5˚C/SEC.
SOLDERING
TIME
200˚C
30
160 ˚C
150 ˚C
140 ˚C
SEC.
30
SEC.
3˚C + 1 ˚C/- 0.5 ˚C
PREHEATING TIME
150 ˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
200
250
Note: Non-halide flux should be used
Recommended Pb-Free IR Profile
TIMEWITHIN 5 ˚C of ACTUAL
PEAKTEMPERATURE
t
p
20-40 SEC.
260 +0/-5
˚
C
T
T
p
L
217 ˚C
RAMP-UP
˚C/SEC. MAX.
RAMP-DOWN
3
6 ˚C/SEC. MAX.
150 - 200 ˚C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60to180SEC.
25
t 25 ˚C to PEAK
TIME
NO TES:
THE TIME FROM 25
= 200 C, T
˚
C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 150
smin
T
˚
˚C
smax
Note: Non-halide flux should be used
Regulatory Information
Both ACPL-072L and ACPL-772L are approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
(option 060 only)
UL
Approved under UL 1577, component recognition
program up, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
5
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
ACPL-772L
ACPL-072L
Description
Symbol
Option 060 Option 060 Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
I – IV
I – IV
I – III
I – IV
I – III
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
Climatic Classification
55/105/21 55/105/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
2
2
VIORM
VPR
630
1181
560
1050
Vpeak
Vpeak
Input to Output Test Voltage, Method b**
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
Input to Output Test Voltage, Method a**
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
VPR
945
840
Vpeak
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec)
VIOTM
6000
4000
Safety-limiting values – maximum values allowed in the event of a failure,
also see Figure 2.
Case Temperature
Input Current
TS
175
230
600
150
150
600
°C
mA
mW
IS, INPUT
PS, OUTPUT
Output Power
W
Insulation Resistance at TS, VIO = 500 V
RIO
>109
>109
*
Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
Table 2. Insulation and Safety Related Specifications
Value
ACPL-
Parameter
Symbol
772L
ACPL-072L
Units
Conditions
Minimum External
Air Gap (Clearance)
L(101)
7.1
4.9
mm
Measured from input terminals to output termi-
nals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
7.4
4.8
mm
mm
Measured from input terminals to output termi-
nals, shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
0.08
Through insulation distance conductor to con-
ductor, usually the straight line distance thickness
between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI
>175
IIIa
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as
a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board,
minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance
path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered.
There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances.
Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
6
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
–55
–40
0
Max.
Units
°C
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltages
TS
+125
TA
+105
°C
VDD1, VDD2
6.0
Volts
Volts
Volts
mA
Input Voltage
VI
–0.5
–0.5
VDD1 +0.5
VDD2 +0.5
10
Output Voltage
VO
IO
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 sec., 1.6 mm below seating plane
Please See Solder Reflow Temperature Profile Section
Table 4. Recommended Operating Conditions
Parameter
Symbol
TA
Min.
–40
3.0
Max.
+105
3.6
Units
°C
V
Ambient Operating Temperature
Supply Voltages ( 3.3V operation)
Supply Voltages ( 5V operation)
Logic High Input Voltage
Logic Low Input Voltage
VDD1, VDD2
VDD1, VDD2
VIH
4.5
5.5
V
2.0
VDD1
0.8
V
VIL
0.0
V
Input Signal Rise and Fall Times
tr, tf
1.0
ms
Table 5. Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
The following specifications cover the following power supply combinations: (4.5V≤V ≤5.5V, 4.5V≤V ≤5.5V),
DD1
DD2
(3V≤V ≤3.6V, 3V≤V ≤3.6V), (4.5V≤V ≤5.5V, 3V≤V ≤3.6V) and (3V≤V ≤3.6V, 4.5V≤V ≤5.5V).
DD1
DD2
DD1
DD2
DD1
DD2
All typical specifications are at T =+25°C , V
= V = +3.3V.
DD2
A
DD1
Parameter
Symbol
IDD1L
IDD1H
IDD2L
IDD2H
II
Min.
Typ.
8.8
1.4
4.3
4.5
Max.
Units
mA
mA
mA
mA
mA
V
Test Conditions
Logic Low Input Supply Current[2]
Logic High Input Supply Current[2]
Output Supply Current
15
5
VI = 0 V
VI = VDD1
10
10
10
Input Current
–10
Logic High Output Voltage
VOH
VDD2 -0.4
VDD2 -1.4
VDD2
VDD2 -0.4
0
IO = –20 mA, VI = VIH
IO = –4 mA, VI = VIH
IO = 20 mA, VI = VIL
IO = 4 mA, VI = VIL
V
Logic Low Output Voltage
VOL
0.1
1.0
V
0.35
V
7
Table 6. Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
The following specifications cover the following power supply combinations: (4.5V≤V ≤5.5V, 4.5V≤V ≤5.5V),
DD1
DD2
(3V≤V ≤3.6V, 3V≤V ≤3.6V), (4.5V≤V ≤5.5V, 3V≤V ≤3.6V) and (3V≤V ≤3.6V, 4.5V≤V ≤5.5V).
DD1
DD2
DD1
DD2
DD1
DD2
All typical specifications are at T =+25°C, V
= V = +3.3V.
DD2
A
DD1
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Propogation Delay Time
to Logic Low Output [3]
tPHL
23.5
40
ns
CL = 15 pF, CMOS Signal Levels
Propogation Delay Time
to Logic High Output [3]
tPLH
tPW
25.5
40
ns
CL = 15 pF, CMOS Signal Levels
Pulse Width [4]
40
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
Maximum Data Rate [5]
Pulse Width Distortion [6]
25
6
MBd
ns
|PWD |
2
| tPHL - tPLH
|
Propagation Delay Skew [7]
tPSK
tR
20
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
Output Rise Time
(10% – 90%)
9
Output Fall Time
(90% - 10%)
tF
8
ns
CL = 15 pF, CMOS Signal Levels
Common Mode Transient
| CMH
|
10
10
20
20
kV/ms VCM = 1000 V, TA = 25°C,
Immunity at Logic High Output [8]
VI = VDD1, VO > 0.8 VDD1
Common Mode Transient
Immunity at Logic Low Output [8]
| CML |
kV/ms VCM = 1000 V, TA = 25°C,
VI = 0 V, VO < 0.8 V
Table 7. Package Characteristics
All typical specifications are at T = 25°C.
A
Parameters
Symbol
Min.
Typ.
Max. Units Test Conditions
Input-Output Momentary
With-stand Voltage [7,8,9]
072L
772L
VISO
3750
3750
5000
V rms RH ≤ 50%, t = 1 min, TA = 25°C
772L with
020 option
Input-Output Resistance [9]
Input-Output Capacitance
Input Capacitance [12]
R I-O
C I-O
C I
1012
0.6
V I-O = 500 V dc
f = 1 MHz
W
pF
pF
3.0
Input IC Junction-to-Case
Thermal Resistance
772L
072L
772L
072L
PPD
qjci
145
160
140
135
°C/W Thermocouple located at center
underside of package
Output IC Junction-to-Case
Thermal Resistance
qjco
°C/W
Package Power Dissipation
150
mW
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when V is low and OFF when V is high.
I
I
3.
t propagation delay is measured from the 50% level on the falling edge of the V signal to the 50% level of the falling edge of the V signal. t
PHL I O PLH
propagation delay is measured from the 50% level on the rising edge of the V signal to the 50% level of the rising edge of the V signal.
I
O
4. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
5. The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
6. PWD is defined as |t - t |. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
PHL PLH
7.
t
PSK
is equal to the magnitude of the worst case difference in t
and/or t
that will be seen between units at any given temperature within the
PHL
PLH
recommended operating conditions.
8
8. CM is the maximum common mode voltage slew rate that can be sustained while maintaining V > 0.8 V . CML is the maximum common
H
O
DD2
mode voltage slew rate that can be sustained while maintaining V < 0.8 V. The common mode voltage slew rates apply to both rising and falling
O
common mode voltage edges.
9. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
10. In accordance with UL1577, each ACPL-072L is proof tested by applying an insulation test voltage ≥ 4500 V
for 1 second (leakage detection
RMS
current limit, I ≤ 5 mA). Each ACPL-772L is proof tested by applying an insulation test voltage ≥ 4500 V
for 1 second (leakage detection current
I-O
RMS
limit, I ≤ 5 mA).
I-O
11. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refers to your equipment level safety specification or Avago Technologies Application Note 1074
entitled “Optocoupler Input-Output Endurance Voltage.”
12. C is the capacitance measured at pin 2 (V ).
I
I
31
29
27
25
23
21
19
17
15
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
PWD
Tplh
Tphl
-20
0
20
40
60
80
100
-20
0
20
40
T A ( o C)
60
80
100
o
T A
( C)
Figure 1. Typical propagation delays vs temperature
Figure 2. Typical pulse width distortion vs temperature
12
11
10
9
32
30
28
26
24
8
7
6
Tplh
Tphl
Rise Time
Fall Time
22
20
5
4
-20
15
25
35
C (pF)
L
45
55
0
20
40
60
80
100
o
T A ( C)
Figure 4. Typical propagation delays vs load capacitance
Figure 3. Typical rise and fall time vs temperature
6
5
4
3
2
1
0
PWD
Surface Mount SO-8 Product
Standard 8-pin DIP Product
1,000
1000
Is (mA)
Is (mA)
800
600
400
200
800
600
400
200
0
Ps (mW)
Ps (mW)
0
0
25
50
75
100 125 150 175
15
25
35
(pF)
45
55
0
25 50
75 100 125 150 175
T
A
- Case Temperature - C
TA - Case Temperature - °C
C L
Figure 6. Thermal derating curve, dependence of safety limiting value with
case temperature per IEC/EN/DIN EN 60747-5-2
Figure 5. Typical pulse width distortion vs load capacitance
9
Application Information
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Bypassing and PC Board Layout
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The ACPL-x72L optocouplers are extremely easy to use.
No external interface circuitry is required because ACPL-
x72L uses high speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
The propagation delay from a low to high (t ) is the
PLH
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(t ) is the amount of time required for the input signal
to propagate to the output, causing the output to change
from high to low. Please see Figure 9.
PHL
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01mF and 0.1mF.
For each capacitor, the total lead length between both
ends of the capacitor and power supply pins should not
exceed 20mm. Figure 8 illustrates the recommended
printed circuit board layout for ACPL-x72L.
INPUT
5 V CMOS
0 V
V I
50%
tPLH
90%
tPHL
V OH
2.5 V CMOS
V
OUTPUT
V O
90%
10%
10%
V DD1
V I
8
V DD2
1
2
3
4
C1
C2
7 NC
Figure 9. Signal plot shows how propagation delay is defined
NC
6
5
V O
Pulse-width distortion (PWD) is the difference between
and t and often determines the maximum data
t
PHL
PLH
GND1
GND 2
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD specification for ACPL-x72L
is 6ns (15%) maximum across recommended operating
conditions.
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended Circuit Diagram
V DD1
VDD2
V I
C1
C2
V
O
GND 1
GND 2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 8. Recommended Printed Circuit Board Layout
10
Propagation delay skew, t , is an important parameter As mentioned earlier, t
can determine the maximum
PSK
PSK
to consider in parallel data applications where parallel data transmission rate. Figure 11 is the timing
synchronization of signals on parallel data lines is a diagram of a typical parallel data application with
concern. If the parallel data is sent through a group both the clock and data lines being sent through the
of optocouplers, differences in propagation delays optocouplers. The figure shows data and clock signals at
will cause the data to arrive at the outputs of the the inputs and outputs of the optocouplers. In this case
optocouplers at different times. If this difference in the data is assumes to be clocked off of the rising edge of
propagation delay is large enough it will determine the the clock.
maximum rate at which parallel data can be sent through
the optocouplers.
DATA
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
INPUTS
CLOCK
delays, either t
or t
for any given group of
PLH
PHL
optocouoplers which are operating under the same
conditions (i.e., the same drive current, supply voltage,
output load, and operating temperature). As illustrated
in Figure 10, if the inputs of a group of optocouplers are
DATA
switched either ON or OFF at the same time, t
difference between the shortest propagation delay,
is the
PSK
OUTPUTS
CLOCK
tPSK
either t
either t
or t
and t
and the longest propagation delay,
PLH
PLH
PHL
PHL
.
tPSK
V I
50%
Figure 11. Parallel data transmission example.
Propagation delay skew represents the uncertainty
of where an edge might be after being sent through
an optocoupler. Figure 11 shows that there will be
uncertainty in both the data and clock lines. It is
important that these two areas of uncertainty not
overlap, otherwise the clock signal might arrive before
all the data outputs have settled, or some of the data
outputs may start to change before the clock signal
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through
2.5 V,
CMOS
V O
tPSK
V I
50%
2.5 V,
CMOS
V O
optocouplers in a parallel application is twice t . A
PSK
cautious design should use a slightly longer pulse width
to ensure that any additional uncertainty in the rest of
the circuit does not cause a problem.
Figure 10. Propagation delay skew waveform
The ACPL-x72L optocoupler offers the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0462EN
AV02-0324EN - January 19, 2010
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