SAM-D20G_14 [ATMEL]
SMART ARM-Based Microcontroller;
| 型号： | SAM-D20G_14 |
| 厂家： | 
ATMEL |
| 描述： | SMART ARM-Based Microcontroller 微控制器 |
| 文件： | 总32页 (文件大小：979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel SAM D20J / SAM D20G / SAM D20E
SMART ARM-Based Microcontroller
DATASHEET SUMMARY
Description
The Atmel® | SMART™ SAM D20 is a series of low-power microcontrollers using the 32-bit
ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and
32KB of SRAM. The SAM D20 devices operate at a maximum frequency of 48MHz and
reach 2.14 Coremark/MHz. They are designed for simple and intuitive migration with
identical peripheral modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All devices include
intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and
support for capacitive touch button, slider and wheel user interfaces.
The Atmel | SMART SAM D20 devices provide the following features: In-system
programmable Flash, eight-channel Event System, programmable interrupt controller, up to
52 programmable I/O pins, 32-bit real-time clock and calendar, up to eight 16-bit
Timer/Counters (TC). The timer/counters can be configured to perform frequency and
waveform generation, program execution timing or input capture with time and frequency
measurement of digital signals. The TCs can operate in 8- or 16-bit mode, or be cascaded
to form a 32-bit TC. The series provide up to six Serial Communication Modules (SERCOM)
that each can be configured to act as an USART, UART, SPI and I2C up to 400kHz; up to
twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling
and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog
comparators with window mode, Peripheral Touch Controller supporting up to 256 buttons,
sliders, wheels, and proximity sensing; programmable Watchdog Timer, brown-out detector
and power-on reset, and two-pin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can
be used as a source for the system clock. Different clock domains can be independently
configured to run at different frequencies while enabling power saving by running each
peripheral at its optimal clock frequency.
The Atmel | SMART SAM D20 devices have two software-selectable sleep modes, idle and
standby. In idle mode the CPU is stopped while all other functions can be kept running. In
standby all clocks and functions are stopped expect those selected to continue running. The
device supports SleepWalking. This feature allows the peripheral to wake up from sleep
based on predefined conditions, and thus allows the CPU to wake up only when needed,
e.g. when a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send
events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface.
The same interface can be used for non-intrusive on-chip debug of application code. A boot
loader running in the device can use any communication interface to download and upgrade
the application program in the Flash memory.
The Atmel | SMART SAM D20 devices are supported with a full suite of program and system
development tools, including C compilers, macro assemblers, program
debugger/simulators, programmers and evaluation kits.
Atmel-42129LS–SAM-D20_Summary–09/2014
SMART
Features
z
z
z
Processor
z ARM Cortex-M0+ CPU running at up to 48MHz
z
Single-cycle hardware multiplier
Memories
z 16/32/64/128/256KB in-system self-programmable flash
z 2/4/8/16/32KB SRAM
System
z Power-on reset (POR) and brown-out detection (BOD)
z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)
z External Interrupt Controller (EIC)
z 16 external interrupts
z One non-maskable interrupt
z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
z Idle and standby sleep modes
z SleepWalking peripherals
Peripherals
z
z
z 8-channel Event System
z Up to eight 16-bit Timer/Counters (TC), configurable as either:
z
z
z
One 16-bit TC with compare/capture channels
One 8-bit TC with compare/capture channels
One 32-bit TC with compare/capture channels, by using two TCs
z 32-bit Real Time Counter (RTC) with clock/calendar function
z Watchdog Timer (WDT)
z CRC-32 generator
z Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
z
z
z
USART with full-duplex and single-wire half-duplex configuration
I2C up to 400kHz
SPI
z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
z
z
z
z
Differential and single-ended channels
1/2x to 16x gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
z 10-bit, 350ksps Digital-to-Analog Converter (DAC)
z Two Analog Comparators with window compare function
z Peripheral Touch Controller (PTC)
z
256-Channel capacitive touch and proximity sensing
z
z
I/O
z Up to 52 programmable I/O pins
Packages
z 64-pin TQFP, QFN
z 64-ball UFBGA
z 48-pin TQFP, QFN
z 45-ball WLCSP
z 32-pin TQFP, QFN
z
z
Operating Voltage
z 1.62V – 3.63V
Power Consumption
z Down to 70µA/MHz in active mode
z Down to 8µA running the Peripheral Touch Controller
Atmel | SMART SAM D20 [DATASHEET Summary]
2
Atmel-42129LS–SAM-D20_Summary–09/2014
1.
Configuration Summary
SAM D20J
SAM D20G
SAM D20E
Number of pins
64
52
48
32
26
General Purpose I/O-pins (GPIOs)
Flash
38
256/128/64/32/16KB
32/16/8/4/2KB
256/128/64/32/16KB
256/128/64/32/16KB
32/16/8/4/2KB
SRAM
32/16/8/4/2KB
Maximum CPU frequency
Event System channels
Timer Counter (TC)
Waveform output channels for TC
48MHz
8
8
2
8
6
2
8
6
2
Serial Communication Interface
(SERCOM)
6
6
4
Analog-to-Digital Converter (ADC)
channels
20
2
14
2
10
2
Analog comparators
Digital-to-Analog Converter (DAC)
channels
1
1
1
Real-Time Counter (RTC)
RTC alarms
Yes
1
Yes
1
Yes
1
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
RTC compare values
External Interrupt lines
16
16
16
Peripheral Touch Controller (PTC) X
and Y lines
16x16
12x10
10x6
QFN
TQFP
UFBGA
QFN
TQFP
WLCSP
QFN
TQFP
Packages
Oscillators
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHzinternal oscillator (OSC32K)
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
SW Debug Interface
Yes
Yes
Yes
Yes
Yes
Yes
Watchdog Timer (WDT)
Atmel | SMART SAM D20 [DATASHEET Summary]
3
Atmel-42129LS–SAM-D20_Summary–09/2014
2.
Ordering Information
SAMD 20 E 14 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
20 = Cortex M0+ CPU, Basic Feature Set
Package Grade
O
U = -40 - 85 C Matte Sn Plating
Pin Count
E = 32 Pins
G = 48 Pins
J = 64 Pins
O
N = -40 - 105 C Matte Sn Plating
Package Type
Flash Memory Density
A = TQFP
M = QFN
C = UFBGA
U = WLCSP
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Default Variant
2.1
SAM D20E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E14A-AU
ATSAMD20E14A-AN
ATSAMD20E14A-AUT
ATSAMD20E14A-ANT
ATSAMD20E14A-MU
ATSAMD20E14A-MN
ATSAMD20E14A-MUT
ATSAMD20E14A-MNT
Tray
TQFP32
Tape & Reel
Tray
16K
2K
QFN32
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
4
Atmel-42129LS–SAM-D20_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E15A-AU
ATSAMD20E15A-AN
ATSAMD20E15A-AUT
ATSAMD20E15A-ANT
ATSAMD20E15A-MU
ATSAMD20E15A-MN
ATSAMD20E15A-MUT
ATSAMD20E15A-MNT
ATSAMD20E16A-AU
ATSAMD20E16A-AN
ATSAMD20E16A-AUT
ATSAMD20E16A-ANT
ATSAMD20E16A-MU
ATSAMD20E16A-MN
ATSAMD20E16A-MUT
ATSAMD20E16A-MNT
ATSAMD20E17A-AU
ATSAMD20E17A-AN
ATSAMD20E17A-AUT
ATSAMD20E17A-ANT
ATSAMD20E17A-MU
ATSAMD20E17A-MN
ATSAMD20E17A-MUT
ATSAMD20E17A-MNT
ATSAMD20E18A-AU
ATSAMD20E18A-AN
ATSAMD20E18A-AUT
ATSAMD20E18A-ANT
ATSAMD20E18A-MU
ATSAMD20E18A-MN
ATSAMD20E18A-MUT
ATSAMD20E18A-MNT
Tray
TQFP32
Tape & Reel
Tray
32K
4K
QFN32
TQFP32
QFN32
TQFP32
QFN32
TQFP32
QFN32
Tape & Reel
Tray
Tape & Reel
Tray
64K
128K
256K
8K
Tape & Reel
Tray
Tape & Reel
Tray
16K
Tape & Reel
Tray
Tape & Reel
Tray
32K
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
5
Atmel-42129LS–SAM-D20_Summary–09/2014
2.2
SAM D20G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G14A-AU
ATSAMD20G14A-AN
ATSAMD20G14A-AUT
ATSAMD20G14A-ANT
ATSAMD20G14A-MU
ATSAMD20G14A-MN
ATSAMD20G14A-MUT
ATSAMD20G14A-MNT
ATSAMD20G15A-AU
ATSAMD20G15A-AN
ATSAMD20G15A-AUT
ATSAMD20G15A-ANT
ATSAMD20G15A-MU
ATSAMD20G15A-MN
ATSAMD20G15A-MUT
ATSAMD20G15A-MNT
ATSAMD20G16A-AU
ATSAMD20G16A-AN
ATSAMD20G16A-AUT
ATSAMD20G16A-ANT
ATSAMD20G16A-MU
ATSAMD20G16A-MN
ATSAMD20G16A-MUT
ATSAMD20G16A-MNT
Tray
TQFP48
Tape & Reel
Tray
16K
2K
QFN48
TQFP48
QFN48
TQFP48
QFN48
Tape & Reel
Tray
Tape & Reel
Tray
32K
4K
Tape & Reel
Tray
Tape & Reel
Tray
64K
8K
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
6
Atmel-42129LS–SAM-D20_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G17A-AU
ATSAMD20G17A-AN
ATSAMD20G17A-AUT
ATSAMD20G17A-ANT
ATSAMD20G17A-MU
ATSAMD20G17A-MN
ATSAMD20G17A-MUT
ATSAMD20G17A-MNT
ATSAMD20G17A-UUT
ATSAMD20G18A-AU
ATSAMD20G18A-AN
ATSAMD20G18A-AUT
ATSAMD20G18A-ANT
ATSAMD20G18A-MU
ATSAMD20G18A-MN
ATSAMD20G18A-MUT
ATSAMD20G18A-MNT
ATSAMD20G18A-UUT
Tray
TQFP48
Tape & Reel
Tray
128K
16K
QFN48
WLCSP45
TQFP48
Tape & Reel
Tape & Reel
Tray
Tape & Reel
Tray
256K
32K
QFN48
Tape & Reel
Tape & Reel
WLCSP45
2.3
SAM D20J
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J14A-AU
ATSAMD20J14A-AN
ATSAMD20J14A-AUT
ATSAMD20J14A-ANT
ATSAMD20J14A-MU
ATSAMD20J14A-MN
ATSAMD20J14A-MUT
ATSAMD20J14A-MNT
Tray
TQFP64
Tape & Reel
Tray
16K
2K
QFN64
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
7
Atmel-42129LS–SAM-D20_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J15A-AU
ATSAMD20J15A-AN
ATSAMD20J15A-AUT
ATSAMD20J15A-ANT
ATSAMD20J15A-MU
ATSAMD20J15A-MN
ATSAMD20J15A-MUT
ATSAMD20J15A-MNT
ATSAMD20J16A-AU
ATSAMD20J16A-AN
ATSAMD20J16A-AUT
ATSAMD20J16A-ANT
ATSAMD20J16A-MU
ATSAMD20J16A-MN
ATSAMD20J16A-MUT
ATSAMD20J16A-MNT
ATSAMD20J17A-AU
ATSAMD20J17A-AN
ATSAMD20J17A-AUT
ATSAMD20J17A-ANT
ATSAMD20J17A-MU
ATSAMD20J17A-MN
ATSAMD20J17A-MUT
ATSAMD20J17A-MNT
ATSAMD20J17A-CU
ATSAMD20J17A-CUT
Tray
TQFP64
Tape & Reel
Tray
32K
4K
QFN64
TQFP64
QFN64
Tape & Reel
Tray
Tape & Reel
Tray
64K
8K
Tape & Reel
Tray
TQFP64
Tape & Reel
Tray
128K
16K
QFN64
Tape & Reel
Tray
UFBGA64
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
8
Atmel-42129LS–SAM-D20_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J18A-AU
ATSAMD20J18A-AN
ATSAMD20J18A-AUT
ATSAMD20J18A-ANT
ATSAMD20J18A-MU
ATSAMD20J18A-MN
ATSAMD20J18A-MUT
ATSAMD20J18A-MNT
ATSAMD20J18A-CU
ATSAMD20J18A-CUT
Tray
TQFP64
Tape & Reel
Tray
256K
32K
QFN64
Tape & Reel
Tray
UFBGA64
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
9
Atmel-42129LS–SAM-D20_Summary–09/2014
3.
Block Diagram
ARM SINGLE CYCLE IOBUS
ARM CORTEX-M0+
PROCESSOR
SWCLK
SWDIO
SERIAL
WIRE
F
48MHz
max
DEVICE
SERVICE
UNIT
M
32/16/8/4/2KB
RAM
M
S
HIGH SPEED
BUS MATRIX
S
256/128/64/32/16KB
FLASH
S
S
S
PERIPHERAL
ACCESS CONTROLLER
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
AHB-APB
BRIDGE B
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
SYSTEM CONTROLLER
PIN[3:0]
WO[1:0]
6 x SERCOM
VREF
OSCULP32K
OSC32K
BOD33
XOSC32K
XOSC
XIN32
XOUT32
OSC8M
8 x TIMER COUNTER
(See Note1)
XIN
XOUT
DFLL48M
AIN[19:0]
VREFA
VREFB
POWER MANAGER
CLOCK
ADC
CONTROLLER
RESET
CONTROLLER
SLEEP
CONTROLLER
AIN[3:0]
CMP1:0]
RESET
2 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
GCLK_IO[7:0]
VOUT
DAC
REAL TIME
COUNTER
VREFA
WATCHDOG
TIMER
X[15:0]
Y[15:0]
PERIPHERAL
TOUCH
CONTROLLER
EXTINT[15:0]
NMI
EXTERNAL INTERRUPT
CONTROLLER
Notes:
1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to “Configuration Summary” on
page 3 for details.
Atmel | SMART SAM D20 [DATASHEET Summary]
10
Atmel-42129LS–SAM-D20_Summary–09/2014
4.
Pinout
4.1
SAM D20J
4.1.1 QFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDIO
GND
PA00
PA01
PA02
PA03
PB04
PB05
1
2
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
3
4
5
6
GNDANA
VDDANA
PB06
7
8
9
PB07
10
11
12
13
14
15
16
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel | SMART SAM D20 [DATASHEET Summary]
11
Atmel-42129LS–SAM-D20_Summary–09/2014
4.1.2 UFBGA64
Atmel | SMART SAM D20 [DATASHEET Summary]
12
Atmel-42129LS–SAM-D20_Summary–09/2014
4.2
SAM D20G
4.2.1 QFP48
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
GND
1
2
PA00
PA01
PA02
PA03
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
3
4
5
GNDANA
VDDANA
PB08
6
7
8
PB09
9
PA04
10
11
12
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel | SMART SAM D20 [DATASHEET Summary]
13
Atmel-42129LS–SAM-D20_Summary–09/2014
4.2.2 WLCSP45
Atmel | SMART SAM D20 [DATASHEET Summary]
14
Atmel-42129LS–SAM-D20_Summary–09/2014
4.3
SAM D20E
24
23
22
21
20
19
18
17
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
1
2
3
4
5
6
7
8
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
Atmel | SMART SAM D20 [DATASHEET Summary]
15
Atmel-42129LS–SAM-D20_Summary–09/2014
5.
I/O Multiplexing and Considerations
5.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written
to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in
the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1.
Pin
PORT Function Multiplexing
A
B(1)
C
D
E
F
G
H
SAM SAM SAM I/O
D20ED20GD20J Pin Supply Type
Pin
EIC
REF
ADC AC PTC DAC
SERCOM(2)
TC(3)
AC/GCLK
SERCOM1/
PAD[0]
TC2/
WO[0]
1
1
1
PA00 VDDANA
EXTINT[0]
SERCOM1/
PAD[1]
TC2/
WO[1]
2
3
4
2
3
4
2
3
4
PA01 VDDANA
PA02 VDDANA
PA03 VDDANA
EXTINT[1]
EXTINT[2]
EXTINT[3]
AIN[0]
AIN[1]
Y[0] VOUT
Y[1]
ADC/VREFA
DAC/VREFA
5
6
9
PB04 VDDANA
PB05 VDDANA
PB06 VDDANA
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
AIN[12]
AIN[13]
AIN[14]
AIN[15]
Y[10]
Y[11]
Y[12]
Y[13]
10 PB07 VDDANA
11 PB08 VDDANA
SERCOM4/
PAD[0]
TC4/
WO[0]
7
EXTINT[8]
EXTINT[9]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
NMI
AIN[2]
AIN[3]
Y[14]
Y[15]
SERCOM4/
PAD[1]
TC4/
WO[1]
8
12 PB09 VDDANA
13 PA04 VDDANA
14 PA05 VDDANA
15 PA06 VDDANA
16 PA07 VDDANA
17 PA08 VDDIO I2C
ADC/
VREFB
SERCOM0/
PAD[0]
TC0/
WO[0]
5
6
9
AIN[4] AIN[0] Y[2]
AIN[5] AIN[1] Y[3]
AIN[6] AIN[2] Y[4]
AIN[7] AIN[3] Y[5]
SERCOM0/
PAD[1]
TC0/
WO[1]
10
11
12
13
14
15
16
19
20
SERCOM0/
PAD[2]
TC1/
WO[0]
7
SERCOM0/
PAD[3]
TC1/
WO[1]
8
SERCOM0/ SERCOM2/
PAD[0] PAD[0]
TC0/
WO[0]
11
12
13
14
AIN[16]
AIN[17]
AIN[18]
AIN[19]
X[0]
X[1]
X[2]
X[3]
SERCOM0/ SERCOM2/
PAD[1] PAD[1]
TC0/
WO[1]
18 PA09 VDDIO I2C EXTINT[9]
SERCOM0/ SERCOM2/
PAD[2] PAD[2]
TC1/
WO[0]
19 PA10 VDDIO
20 PA11 VDDIO
23 PB10 VDDIO
24 PB11 VDDIO
EXTINT[10]
EXTINT[11]
EXTINT[10]
EXTINT[11]
GCLK_O[4]
GCLK_IO[5]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[6]
GCLK_IO[7]
GCLK_IO[0]
GCLK_IO[1]
SERCOM0/ SERCOM2/
TC1/
WO[1]
PAD[3]
PAD[3]
SERCOM4/
PAD[2]
TC5/
WO[0]
SERCOM4/
PAD[3]
TC5/
WO[1]
SERCOM4/
PAD[0]
TC4/
WO[0]
25 PB12 VDDIO I2C EXTINT[12]
26 PB13 VDDIO I2C EXTINT[13]
X[12]
X[13]
X[14]
X[15]
SERCOM4/
PAD[1]
TC4/
WO[1]
SERCOM4/
PAD[2]
TC5/
WO[0]
27 PB14 VDDIO
28 PB15 VDDIO
EXTINT[14]
EXTINT[15]
SERCOM4/
PAD[3]
TC5/
WO[1]
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
Table 5-1.
Pin
PORT Function Multiplexing (Continued)
A
B(1)
C
D
E
F
G
H
SAM SAM SAM I/O
D20ED20GD20J Pin Supply Type
Pin
EIC
REF
ADC AC PTC DAC
SERCOM(2)
TC(3)
AC/GCLK
SERCOM2/ SERCOM4/
PAD[0] PAD[0]
TC2/
WO[0]
21
22
23
24
25
26
27
28
29 PA12 VDDIO I2C EXTINT[12]
AC/CMP[0]
SERCOM2/ SERCOM4/
PAD[1] PAD[1]
TC2/
WO[1]
30 PA13 VDDIO I2C EXTINT[13]
AC/CMP[1]
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[2]
GCLK_IO[3]
AC/CMP[0]
AC/CMP[1]
GCLK_IO[2]
GCLK_IO[3]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[6]
GCLK_IO[7]
SERCOM2/ SERCOM4/
PAD[2] PAD[2]
TC3/
WO[0]
15
16
17
18
19
20
31 PA14 VDDIO
32 PA15 VDDIO
EXTINT[14]
EXTINT[15]
SERCOM2/ SERCOM4/
PAD[3] PAD[3]
TC3/
WO[1]
SERCOM1/ SERCOM3/
PAD[0] PAD[0]
TC2/
WO[0]
35 PA16 VDDIO I2C EXTINT[0]
36 PA17 VDDIO I2C EXTINT[1]
X[4]
X[5]
X[6]
X[7]
SERCOM1/ SERCOM3/
PAD[1] PAD[1]
TC2/
WO[1]
SERCOM1/ SERCOM3/
PAD[2] PAD[2]
TC3/
WO[0]
37 PA18 VDDIO
38 PA19 VDDIO
EXTINT[2]
EXTINT[3]
SERCOM1/ SERCOM3/
TC3/
WO[1]
PAD[3]
PAD[3]
SERCOM5/
PAD[0]
TC6/
WO[0]
39 PB16 VDDIO I2C EXTINT[0]
40 PB17 VDDIO I2C EXTINT[1]
SERCOM5/
PAD[1]
TC6/
WO[1]
SERCOM5/ SERCOM3/
PAD[2] PAD[2]
TC7/
WO[0]
29
30
31
32
33
34
37
38
41 PA20 VDDIO
42 PA21 VDDIO
EXTINT[4]
EXTINT[5]
X[8]
X[9]
SERCOM5/ SERCOM3/
PAD[3] PAD[3]
TC7/
WO[1]
SERCOM3/ SERCOM5/
PAD[0] PAD[0]
TC4/
WO[0]
21
22
23
24
43 PA22 VDDIO I2C EXTINT[6]
44 PA23 VDDIO I2C EXTINT[7]
X[10]
X[11]
SERCOM3/ SERCOM5/
PAD[1] PAD[1]
TC4/
WO[1]
SERCOM3/ SERCOM5/
PAD[2] PAD[2]
TC5/
WO[0]
45 PA24 VDDIO
46 PA25 VDDIO
49 PB22 VDDIO
50 PB23 VDDIO
EXTINT[12]
EXTINT[13]
EXTINT[6]
EXTINT[7]
SERCOM3/ SERCOM5/
TC5/
WO[1]
PAD[3]
PAD[3]
SERCOM5/
PAD[2]
TC7/
WO[0]
GCLK_IO[0]
GCLK_IO[1]
SERCOM5/
PAD[3]
TC7/
WO[1]
25
27
39
41
51 PA27 VDDIO
53 PA28 VDDIO
EXTINT[15]
EXTINT[8]
GCLK_IO[0]
GCLK_IO[0]
SERCOM1/
PAD[2]
TC1/
WO[0]
31
32
45
46
57 PA30 VDDIO
58 PA31 VDDIO
EXTINT[10]
EXTINT[11]
SWCLK GCLK_IO[0]
SWDIO(4)
SERCOM1/
PAD[3]
TC1/
WO[1]
SERCOM5/
PAD[0]
TC0/
WO[0]
59 PB30 VDDIO I2C EXTINT[14]
60 PB31 VDDIO I2C EXTINT[15]
SERCOM5/
PAD[1]
TC0/
WO[1]
SERCOM5/
PAD[2]
TC7/
WO[0]
61 PB00 VDDANA
62 PB01 VDDANA
63 PB02 VDDANA
64 PB03 VDDANA
EXTINT[0]
EXTINT[1]
EXTINT[2]
EXTINT[3]
AIN[8]
AIN[9]
Y[6]
Y[7]
Y[8]
Y[9]
SERCOM5/
PAD[3]
TC7/
WO[1]
SERCOM5/
PAD[0]
TC6/
WO[0]
47
48
AIN[10]
AIN[11]
SERCOM5/
PAD[1]
TC6/
WO[1]
Note:
1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode.
3. Note that TC6 and TC7 are not supported on the SAM D20G. Refer to “Configuration Summary” on page 3 for details.
4. This function is only activated in the presence of a debugger
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
5.2
Other Functions
5.2.1 Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL).
Oscillator
Supply
Signal
XIN
I/O Pin
PA14
PA15
PA00
PA01
XOSC
VDDIO
XOUT
XIN32
XOUT32
XOSC32K
VDDANA
5.2.2 Serial Wire Debug Interface Pinout
After reset, SWCLK functionality is selected for pin PA30 to allow for debugger probe detection. The application software
can switch the SWCLK functionality of PA30 to GPIO (or other peripherals) during runtime. PA31, by default, is config-
ured like other normal I/O pins and will automatically switch to SWDIO function when a debugger cold-plugging or hot-
plugging is detected. When the device is put in debug mode, application software accesses to PA30 and PA31 PORT
registers are ignored.
Signal
SWCLK
SWDIO
Supply
VDDIO
VDDIO
I/O Pin
PA30
PA31
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
6.
Product Mapping
Figure 6-1. SAM D20 Product Mapping
Global Memory Space
0x00000000
Code
0x00000000
Code
Internal flash
0x20000000
0x00040000
0x1FFFFFFF
Reserved
SRAM
SRAM
0x20008000
0x20000000
0x20008000
AHB-APB Bridge C
Undefined
Internal SRAM
0x42000000
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
SERCOM5
TC0
0x40000000
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42001C00
0x42002000
0x42002400
0x42002800
0x42002C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
0x42004C00
Peripherals
Peripherals
0x40000000
0x41000000
0x43000000
AHB-APB
Bridge A
Reserved
0x60000000
AHB-APB
Bridge B
Undefined
0x42000000
0x42FFFFFF
0x60000200
Reserved
AHB-APB
Bridge C
0xE0000000
System
0xFFFFFFFF
System
0xE0000000
0xE000E000
0xE000F000
0xE00FF000
TC1
Reserved
TC2
SCS
TC3
Reserved
ROM Table
Reserved
AHB-APB Bridge A
TC4
0x40000000
0xE0100000
0xFFFFFFFF
PAC0
TC5
0x40000400
PM
TC6
0x40000800
AHB-APB Bridge B
SYSCTRL
TC7
0x40000C00
0x41000000
GCLK
PAC1
DSU
ADC
0x40001000
0x41002000
0x41004000
0x41004400
WDT
AC
0x40001400
RTC
NVMCTRL
PORT
DAC
0x40001800
EIC
PTC
0x40001C00
Reserved
0x40FFFFFF
0x41004800
0x41FFFFFF
0x42005000
0x42FFFFFF
Reserved
Reserved
This figure represents the full configuration of the Atmel® SAM D20 with maximum flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 3 for details.
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
7.
Processor and Architecture
7.1
Cortex-M0+ Processor
The Atmel® SAM D20 implements the ARM® Cortex®-M0+ processor, which is based on the ARMv6 architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and
upward compatible with the Cortex-M3 and Cortex-M4 processors. The ARM Cortex-M0+ implemented is revision r0p1.
For more information, refer to www.arm.com.
7.1.1 Cortex-M0+ Configuration
Feature
Configurable Option
External interrupts 0-32
Little-endian or big-endian
Present or absent
0, 1, 2
SAM D20 Configuration
Interrupts
32
Data endianness
Little-endian
Present
2
SysTick timer
Number of watchpoint comparators
Number of breakpoint comparators
Halting debug support
Multiplier
0, 1, 2, 3, 4
4
Present or absent
Fast or small
Present
Fast (single cycle)
Present
Not supported
Present
Absent
Single-cycle I/O port
Wake-up interrupt controller
Vector Table Offset Register
Unprivileged/Privileged support
Memory Protection Unit
Reset all registers
Present or absent
Supported or not supported
Present or absent
Present or absent
Not present or 8-region
Present or absent
16-bit only or mostly 32-bit
Not present
Absent(1)
32-bit
Instruction fetch width
Note:
1.
All software run in privileged mode only
The ARM Cortex-M0+ processor has two bus interfaces:
z
Single 32-bit AMBA® 3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
z
Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.
Packaging Information
8.1
Thermal Considerations
8.1.1 Thermal Resistance Data
Table 8-1 summarizes the thermal resistance data depending on the package.
Table 8-1. Thermal Resistance Data
Package Type
32-pin TQFP
48-pin TQFP
64-pin TQFP
32-pin QFN
48-pin QFN
64-pin QFN
θJA
θJC
68°C/W
25.8°C/W
12.3°C/W
11.9°C/W
3.1°C/W
11.4°C/W
11.2°C/W
78.8°C/W
66.7°C/W
37.2°C/W
33°C/W
33.5°C/W
8.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following equations:
Equation 1
T
= T + (P × θ
JA
)
J
A
D
Equation 2
= T + (P × (θ
T
+ θ ))
JC
J
A
D
HEATSINK
where:
z
z
z
z
z
θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1
θ
θ
JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1
HEATSINK = cooling device thermal resistance (°C/W), provided in the manufacturer datasheet
PD = device power consumption (W)
TA = ambient temperature (°C)
From “Equation 1” , the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or
not. If a cooling device is to be fitted on the chip, “Equation 2” should be used to compute the resulting average chip-
junction temperature TJ in °C.
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2
Package Drawings
8.2.1 64-pin TQFP
Table 8-2. Device and Package Maximum Weight
300
mg
Table 8-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-4. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.2 64-pin QFN
Note: The exposed die attached pad is not connected inside the device.
Table 8-5. Device and Package Maximum Weight
200
mg
Table 8-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-7. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.3 64-ball UFBGA
Table 8-8. Device and Package Maximum Weight
TBD
mg
Table 8-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-10. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-280
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.4 48-pin TQFP
Table 8-11. Device and Package Maximum Weight
140
mg
Table 8-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-13. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.5 48-pin QFN
Note: The exposed die attached pad is not connected inside the device.
Table 8-14. Device and Package Maximum Weight
140
mg
Table 8-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-16. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.6 45-ball WLCSP
Note: The exposed die attached pad is not connected inside the device.
Table 8-17. Device and Package Maximum Weight
TBD
mg
Table 8-18. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-19. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.7 32-pin TQFP
Table 8-20. Device and Package Maximum Weight
100
mg
Table 8-21. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-22. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.2.8 32-pin QFN
Note: The exposed die attached pad is connected inside the device to GND and GNDANA connected together.
Table 8-23. Device and Package Maximum Weight
90
mg
Table 8-24. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-25. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
Atmel | SMART SAM D20 [DATASHEET Summary]
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Atmel-42129LS–SAM-D20_Summary–09/2014
8.3
Soldering Profile
Table Table 8-26 gives the recommended soldering profile from J-STD-20.
Table 8-26. Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
Preheat Temperature 175°C ±25°C
Time Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
3°C/s max.
150-200°C
60-150s
30s
260°C
Ramp-down Rate
6°C/s max
8 minutes max.
Time 25°C to Peak Temperature
A maximum of three reflow passes is allowed per component.
___REV___267652
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Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1
2.2
2.3
SAM D20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SAM D20G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SAM D20J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1
4.2
4.3
SAM D20J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SAM D20G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SAM D20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . .16
5.1
Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7. Processor and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.1
Cortex-M0+ Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8.1
8.2
8.3
Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Atmel | SMART SAM D20 [DATASHEET Summary]
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