SAM-R21E_14 [ATMEL]
SMART ARM-Based Wireless Microcontroller;
| 型号： | SAM-R21E_14 |
| 厂家： | 
ATMEL |
| 描述： | SMART ARM-Based Wireless Microcontroller 无线 微控制器 |
| 文件： | 总22页 (文件大小：762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel SAM R21E / SAM R21G
SMART ARM-Based Wireless Microcontroller
PRELIMINARY DATASHEET SUMMARY
Description
The Atmel® | SMART™ SAM R21 is a series of low-power microcontrollers using the 32-bit ARM®
Cortex®-M0+ processor and an integrated ultra-low power 2.4GHz ISM band transceiver. SAM
R21 devices are available in 32- and 48-pin packages with up to 256KB Flash, 32KB of SRAM
and are operating at a maximum frequency of 48MHz and reach 2.14 Coremark/MHz. They are
designed for simple and intuitive migration with identical peripheral modules, hex compatible
code, identical linear address map and pin compatible migration paths between all devices in the
product series. All devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and wheel user
interfaces.
The Atmel SAM R21 devices provide the following features: In-system programmable Flash,
12-channel direct memory access (DMA) controller, 12-channel Event System, programmable
interrupt controller, up to 28 programmable I/O pins, ultra-low power 2.4GHz ISM band
transceiver with a data rate of 250kB/s, 32-bit real-time clock and calendar, three 16-bit
Timer/Counters (TC) and three 16-bit Timer/Counters for Control (TCC), where each TC can be
configured to perform frequency and waveform generation, accurate program execution timing or
input capture with time and frequency measurement of digital signals. The TCs can operate in 8-
or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and the three Timer/Counters
for Control have extended functions optimized for motor, lighting and other control applications.
The series provide one full-speed USB 2.0 embedded host and device interface; up to five Serial
Communication Modules (SERCOM) that each can be configured to act as an USART, UART,
SPI, I2C up 3.4MHz and LIN slave; up to eight channel 350ksps 12-bit ADC with programmable
gain and optional oversampling and decimation supporting up to 16-bit resolution, two analog
comparators with window mode, Peripheral Touch Controller supporting up to 48 buttons, sliders,
wheels and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on
reset and two-pin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be
used as a source for the system clock. Different clock domains can be independently configured
to run at different frequencies, enabling power saving by running each peripheral at its optimal
clock frequency, and thus maintaining a high CPU frequency while reducing power consumption.
The SAM R21 devices have two software-selectable sleep modes, idle and standby. In idle mode
the CPU is stopped while all other functions can be kept running. In standby all clocks and
functions are stopped expect those selected to continue running. The device supports
SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and
hence perform predefined tasks without waking up the CPU. The CPU can then be only woken on
a need basis, e.g. a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send events
even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The
same interface can be used for non-intrusive on-chip debug of application code. A boot loader
running in the device can use any communication interface to download and upgrade the
application program in the Flash memory.
The SAM R21 devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and
evaluation kits.
Atmel-42223AS–SAM-R21_Summary–07/2014
SMART
Features
z
Processor
ARM Cortex-M0+ CPU running at up to 48MHz
z
z
z
Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
z
z
Memories
z
z
256/128/64KB in-system self-programmable Flash
32/16/8KB SRAM
System
z
Power-on reset (POR) and brown-out detection (BOD)
z
Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional
Digital Phase Locked Loop (FDPLL96M)
z
z
z
z
External Interrupt Controller (EIC)
Up to 15 external interrupts
One non-maskable interrupt
Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
z
z
Low Power
z
z
Idle and standby sleep modes
SleepWalking peripherals
Peripherals
z
z
z
12-channel Direct Memory Access Controller (DMAC)
12-channel Event System
Integrated Ultra Low Power Transceiver for 2.4GHz ISM Band
z
z
z
z
z
z
z
z
z
250kB/s data rate
-99dBm RX Sensitivity; TX Output Power up to +4dBm
Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
SFD-Detection; Spreading; De-Spreading; Framing; CRC-16 Computation
Antenna Diversity and TX/RX Control
128 Byte TX/RX Frame Buffer
Integrated 16MHz Crystal Oscillator (external crystal needed)
PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4GHz ISM band
Hardware Security (AES, True Random Generator)
z
z
Three 16-bit Timer/Counters (TC), configurable as either:
z
z
z
One 16-bit TC with compare/capture channels
One 8-bit TC with compare/capture channels
One 32-bit TC with compare/capture channels, by using two TCs
Three 16-bit Timer/Counters for Control (TCC), with extended functions:
z
z
z
z
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error
z
z
z
z
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
z
z
Embedded host and device function
Eight endpoints
z
z
Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either:
z
z
z
z
USART with full-duplex and single-wire half-duplex configuration
I2C up to 3.4MHz
SPI
LIN slave
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to eight external channels
z
z
z
z
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
z
z
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
z
48-channel capacitive touch and proximity sensing
z
I/O and Package
z
z
16/28 programmable I/O pins
32-pin and 48-pin QFN
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
2
Atmel-42223AS–SAM-R21_Summary–07/2014
z
z
Operating Voltage
1.8V – 3.6V
Temperature Range
z
z
z
-40°C to 85°C Industrial
-40°C to 125°C Industrial
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
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Atmel-42223AS–SAM-R21_Summary–07/2014
1.
Configuration Summary
SAM R21G
SAM R21E
Pins
48
32
General Purpose I/O-pins (GPIOs)
Flash
28
16
256/128/64KB
256/128/64KB
SRAM
32/16/8KB
32/16/8KB
Timer Counter (TC) instances
Waveform output channels per TC instance
Timer Counter for Control (TCC) instances
Waveform output channels per TCC
DMA channels
3
2
3
2
3
3
4/4/2
12
1
4/4/2
12
1
USB interface
Serial Communication Interface (SERCOM) instances
Inter-IC Sound (I2S) interface
Analog-to-Digital Converter (ADC) channels
Analog Comparators (AC)
5+1(1)
No
8
4+1(1)
No
4
2
2
Digital-to-Analog Converter (DAC)
channels
No
No
Real-Time Counter (RTC)
RTC alarms
Yes
1
Yes
1
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
RTC compare values
External Interrupt lines
15
14
Peripheral Touch Controller (PTC) X and Y lines
Maximum CPU frequency
8x6
6x2
48MHz
Packages
QFN
Yes
QFN
No
32.768kHz crystal oscillator (XOSC32K)
16MHz crystal oscillator for 2.4GHz TRX (XOSCRF)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
Oscillators
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
SW Debug Interface
12
12
Yes
Yes
Yes
Yes
Watchdog Timer (WDT)
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
4
Atmel-42223AS–SAM-R21_Summary–07/2014
Note:
1. SERCOM4 is internally connected to the AT86RF233.
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
5
Atmel-42223AS–SAM-R21_Summary–07/2014
2.
Ordering Information
ATSAMR 21 E 16 A - M U T
Product Family
Package Carrier
SAMR = SoC Microcontroller with RF
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0+ CPU, USB
Package Grade
U = -40 - 85°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Pin Count
E = 32 Pins
G = 48 Pins
Package Type
Flash Memory
M = QFN
18 = 256KB
17 = 128KB
16 = 64KB
Device Variant
A = Default Variant
2.1
SAM R21E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMR21E16A-MF
ATSAMR21E16A-MFT
ATSAMR21E16A-MU
ATSAMR21E16A-MUT
ATSAMR21E17A-MF
ATSAMR21E17A-MFT
ATSAMR21E17A-MU
ATSAMR21E17A-MUT
ATSAMR21E18A-MF
ATSAMR21E18A-MFT
ATSAMR21E18A-MU
ATSAMR21E18A-MUT
Tray
Tape & Reel
Tray
64K
8K
QFN32
Tape & Reel
Tray
Tape & Reel
Tray
128K
256K
16K
32K
QFN32
QFN32
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
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Atmel-42223AS–SAM-R21_Summary–07/2014
2.2
SAM R21G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
Tray
ATSAMR21G16A-MF
ATSAMR21G16A-MFT
ATSAMR21G16A-MU
ATSAMR21G16A-MUT
ATSAMR21G17A-MF
ATSAMR21G17A-MFT
ATSAMR21G17A-MU
ATSAMR21G17A-MUT
ATSAMR21G18A-MF
ATSAMR21G18A-MFT
ATSAMR21G18A-MU
ATSAMR21G18A-MUT
Tape & Reel
Tray
64K
8K
QFN48
Tape & Reel
Tray
Tape & Reel
Tray
128K
256K
16K
32K
QFN48
QFN48
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
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Atmel-42223AS–SAM-R21_Summary–07/2014
3.
Block Diagrams
3.1
MCU Block Diagram
IOBUS
256/128/64KB
NVM
32/16/8KB
RAM
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SWCLK
SWDIO
SERIAL
WIRE
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
DEVICE
SERVICE
UNIT
M
M
S
S
M
M
DMA
HIGH SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
DP
USB FS
S
S
S
DM
DEVICE
MINI-HOST
SOF 1KHZ
AHB-APB
BRIDGE B
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
DMA
SYSTEM CONTROLLER
PAD0
PAD1
PAD2
PAD3
5x SERCOM
VREF
OSCULP32K
OSC32K
BOD33
DMA
(4)
XIN32
WO0
WO1
XOUT32
XOSC32K
OSC8M
3 x TIMER / COUNTER
DFLL48M
FDPLL96M
XIN
XOUT
XOSC
WO0
WO1
DMA
3x TIMER / COUNTER
FOR CONTROL
(2)
POWER MANAGER
CLOCK
WOn
(3)
DMA
AIN[n]
CONTROLLER
8-CHANNEL
VREFB
12-bit ADC 350KSPS
RESET
CONTROLLER
SLEEP
CONTROLLER
RESETN
(3)
GENERIC CLOCK
CONTROLLER
2 ANALOG
COMPARATORS
AIN[3..0]
GCLK_IO[n]
REAL TIME
COUNTER
X[7..0]
Y[5..0]
PERIPHERAL
TOUCH
CONTROLLER
WATCHDOG
TIMER
EXTINT[15..1]
NMI
EXTERNAL INTERRUPT
CONTROLLER
Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC sig-
nals. Refer to “Ordering Information” on page 6 for details.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines.
3. Refer to the PORT Function Multiplexing Table 5-1 for details about the available GCLK_IO and ADC signals.
4. Only available for SAM R21G.
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
8
Atmel-42223AS–SAM-R21_Summary–07/2014
3.2
SAM R21 Interconnection
FECTRL2..5
2.4 GHz RF
front-end circuit
FECTRL0..1
DIG3
2.4GHz TRX (analog)
TRX (digital)
DIG4
(1)
DVSS
AVSS
AVDD
EVDD
AVSS
XTAL1
XTAL2
GNDANA
AVDD
DVDD
AVREG
DVDD
VDDIO
DVREG
DEVDD
DIG1
VDDANA
GNDANA
XTAL1
DIG2
Control Logic
RSTN
XOSC
RF
SPI
(Slave)
SLP_TR
XTAL2
AT86RF233
(4)
GCLK_IO1
GENERIC
CLOCK
ADC
AC
SERCOM 4(3)
EXTINT0
EXTERNAL
INTERRUPT
CONTROLLER
PA20
PB15
PORT
PTC
DIG1..4
RFCTRL
VREG
XOSC
32K
SAMD21
SAMR21
Notes: 1. Paddle connected to digital ground DVSS, GND.
2. Only available for SAM R21G.
3. Dedicated SERCOM4 alternate pin function mapping for internally connected AT86RF233.
4. Die revision A uses GCLK_IO5.
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
9
Atmel-42223AS–SAM-R21_Summary–07/2014
4.
Pinout
4.1
SAM R21G - QFN48
PA00
PA01
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
GND
XTAL2
XTAL1
GNDANA
VDDANA
AVDD
3
PA25
PA24
PA23
PA22
DVDD
GND
4
5
6
7
GNDANA
PA04
8
9
PA19
PA18
PA17
PA16
PA05
10
11
12
PA06
PA07
OSCILLATOR
RF PIN
DIGITAL PIN
ANALOG PIN
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
DIGITAL PIN/
OSCILLATOR
Note:
The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
10
Atmel-42223AS–SAM-R21_Summary–07/2014
4.2
SAM R21E - QFN32
XTAL2
XTAL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDIO
PA25
PA24
DVDD
PA19
PA18
PA17
PA16
GNDANA
VDDANA
AVDD
GNDANA
PA06
PA07
OSCILLATOR
GROUND
RF PIN
DIGITAL PIN
ANALOG PIN
INPUT SUPPLY
RESET PIN
DIGITAL PIN/
OSCILLATOR
REGULATED OUTPUT
SUPPLY
Note:
The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
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Atmel-42223AS–SAM-R21_Summary–07/2014
5.
I/O Multiplexing and Considerations
5.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT must be
written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even
bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1.
Pin
PORT Function Multiplexing
A
B(1)(2)
C
D
E
F
G
H
FECTRL
TCC
SERCOM COM
SAMR21 SAMR21
SERCOM SERCOM-
TC
TCC
AC/
GCLK
(1)(2)
E
G
I/O Pin Supply Type
EIC
REF
ADC
AC PTC
ALT
SERCOM1/
PAD[0]
1
PA00 VDDANA
TCC2/WO[0]
TCC2/WO[1]
TCC0/WO[0]
TCC0/WO[1]
TCC1/WO[0]
TCC1/WO[1]
SERCOM1/
PAD[1]
2
PA01 VDDANA
PA04 VDDANA
PA05 VDDANA
PA06 VDDANA
PA07 VDDANA
EXTINT[1]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
NMI
ADC/
VREFB
SERCOM0/
PAD[0]
9
AIN[4] AIN[0] Y[2]
AIN[5] AIN[1] Y[3]
AIN[6] AIN[2] Y[4]
AIN[7] AIN[3] Y[5]
SERCOM0/
PAD[1]
10
11
12
15
16
21
22
23
24
25
26
27
28
31
32
33
34
SERCOM0/
PAD[2]
7
8
SERCOM0/
PAD[3]
SERCOM0/ SERCOM2/
9
PA08 VDDIO
PA09 VDDIO
PA12 VDDIO
PA13 VDDIO
PA14 VDDIO
PA15 VDDIO
PA16 VDDIO
PA17 VDDIO
PA18 VDDIO
PA19 VDDIO
PA22 VDDIO
PA23 VDDIO
PA24 VDDIO
PA25 VDDIO
I2C
AIN[16]
AIN[17]
X[0]
X[1]
TCC0/WO[0] FECTRL[0]
TCC0/WO[1] FECTRL[1]
TCC2/WO[0] FECTRL[2]
TCC2/WO[1] FECTRL[3]
TC3/WO[0] FECTRL[4]
TC3/WO[1] FECTRL[5]
PAD[0]
PAD[0]
SERCOM0/ SERCOM2/
10
I2C EXTINT[9]
I2C EXTINT[12]
I2C EXTINT[13]
EXTINT[14]
PAD[1]
PAD[1]
SERCOM2/
PAD[0]
AC/
CMP[0]
SERCOM2/
PAD[1]
AC/
CMP[1]
SERCOM2/
PAD[2]
15
16
17
18
19
20
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[2]
GCLK_IO[3]
SERCOM2/
PAD[3]
EXTINT[15]
SERCOM1/ SERCOM3/
PAD[0] PAD[0]
TCC0/
TCC2/WO[0]
WO[0]
I2C
X[4]
X[5]
SERCOM1/ SERCOM3/
PAD[1] PAD[1]
TCC0/
TCC2/WO[1]
WO[1]
I2C EXTINT[1]
EXTINT[2]
SERCOM1/ SERCOM3/
PAD[2] PAD[2]
TCC0/
TC3/WO[0]
AC/
CMP[0]
X[6]
WO[2]
SERCOM1/ SERCOM3/
PAD[3] PAD[3]
TCC0/
TC3/WO[1]
AC/
CMP[1]
EXTINT[3]
X[7]
WO[3]
SERCOM3/ SERCOM5/
TCC0/
TC4/WO[0]
I2C EXTINT[6]
I2C EXTINT[7]
EXTINT[12]
X[10]
X[11]
GCLK_IO[6]
GCLK_IO[7]
PAD[0]
PAD[0]
WO[4]
SERCOM3/ SERCOM5/
PAD[1] PAD[1]
TCC0/
TC4/WO[1]
WO[5]
SERCOM3/ SERCOM5/
PAD[2] PAD[2]
TCC1/
TC5/WO[0]
22
23
USB_DM
USB_DP
WO[2]
SERCOM3/ SERCOM5/
PAD[3] PAD[3]
TCC1/
TC5/WO[1]
EXTINT[13]
WO[3]
Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]
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Atmel-42223AS–SAM-R21_Summary–07/2014
Table 5-1.
Pin
PORT Function Multiplexing (Continued)
A
B(1)(2)
C
D
E
F
G
H
FECTRL
TCC
SERCOM COM
SAMR21 SAMR21
SERCOM SERCOM-
TC
TCC
AC/
GCLK
(1)(2)
E
G
I/O Pin Supply Type
EIC
REF
ADC
AC PTC
ALT
SERCOM5/
PAD[2]
37
PB22 VDDIO
EXTINT[6]
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[0]
GCLK_IO[0]
SERCOM5/
PAD[3]
38
39
41
45
46
47
48
PB23 VDDIO
PA27 VDDIO
PA28 VDDIO
PA30 VDDIO
PA31 VDDIO
PB02 VDDANA
PB03 VDDANA
EXTINT[7]
EXTINT[15]
EXTINT[8]
EXTINT[10]
EXTINT[11]
EXTINT[2]
EXTINT[3]
SERCOM3/
PAD[0]
25
27
31
32
SERCOM3/
PAD[1]
SERCOM1/
PAD[2]
TCC1/WO[0]
TCC1/WO[1]
SWCLK GCLK_IO[0]
SERCOM1/
PAD[3]
SERCOM5/
PAD[0]
AIN[10]
AIN[11]
Y[8]
Y[9]
SERCOM5/
PAD[1]
Notes:
1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to !!!CRs_ElChar_Top!!! for details on
the I2C pin characteristics.
5.2
Internal Multiplexed Signals
PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are by default controlled by the PORT as a general purpose I/O
and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral
function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done
by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in
the PORT.
PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL
inputs.
A
B
C
D
E
F
G
H
FECTRL
TCC
SERCOM
Internal
Signal
SERCOM-
ALT
AC/
GCLK
Supply
VDDIO
VDDIO
VDDIO
VDDANA
VDDIO
VDDIO
VDDIO
Type
Input
Input
I/O
EIC
REF
ADC
AC
PTC
SERCOM
TC
COM
I/O Pin
DIG3
PA10
EXTINT[10]
EXTINT[11]
DIG4
PA11
PA20
PB00
PB15
PB16
PB17
SLP_TR
IRQ
I/O
EXTINT[0]
RSTN
DIG1
I/O
Input
Input
EXTINT[0]
EXTINT[1]
DIG2
SERCOM4/
PAD[2]
MOSI
SEL
PB30
PB31
VDDIO
VDDIO
I/O
I/O
SERCOM4/
PAD[1]
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A
B
C
D
E
F
G
H
FECTRL
TCC
SERCOM
Internal
Signal
SERCOM-
ALT
AC/
GCLK
Supply
Type
EIC
REF
ADC
AC
PTC
SERCOM
TC
COM
I/O Pin
GCLK/
IO[1](1)
CLKM
SCLK
MISO
PC16
VDDIO
I/O
SERCOM4/
PAD[3]
PC18
PC19
VDDIO
VDDIO
I/O
I/O
SERCOM4/
PAD[0]
Note:
1. Die revision A uses GCLK/IO[5].
5.3
Other Functions
5.3.1 Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL).
Oscillator
Supply
Signal
XIN
I/O Pin
PA14
PA15
PA00
PA01
XOSC
VDDIO
XOUT
XIN32
XOUT32
XOSC32K
VDDANA
The integrated AT86RF233 16 MHz crystal oscillator is directly connected to pins and has no multiplexing functionality.
Oscillator Supply Signal I/O Pin
XTAL1
XTAL2
XTAL1
XTAL2
XOSCRF
EVDD/VDDANA
5.3.2 Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will
automatically switch the SWDIO port to the SWDIO function.
Signal
SWCLK
SWDIO
Supply
VDDIO
VDDIO
I/O Pin
PA30
PA31
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6.
Product Mapping
Figure 6-1. Atmel | SMART SAM R21 Product Mapping
Global Memory Space
Code
0x00000000
0x20000000
0x22008000
0x40000000
0x43000000
0x60000000
0x00000000
Code
SRAM
Internal Flash
AHB-APB Bridge C
0x00400000
0x1FFFFFFF
0x42000000
Reserved
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4(1)
SERCOM5
TCC0
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42001C00
0x42002000
0x42002400
0x42002800
0x42002C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
0x42004C00
Undefined
Peripherals
SRAM
0x20000000
0x20008000
Internal SRAM
Reserved
Undefined
Reserved
AHB-APB
0x40000000
0x41000000
AHB-APB
Bridge A
0x60000200
0xFFFFFFFF
AHB-APB
Bridge B
TCC1
0x42000000
0x42FFFFFF
TCC2
AHB-APB
Bridge C
TC3
TC4
AHB-APB Bridge A
0x40000000
TC5
AHB-APB Bridge B
0x41000000
PAC1
PAC0
PM
Reserved
Reserved
ADC
0x41002000
0x41004000
0x41004400
0x41004800
0x41005000
0x41006000
0x40000400
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
DSU
NVMCTRL
PORT
SYSCTRL
GCLK
WDT
AC
DMAC
USB
Reserved
PTC
RTC
0x42005000
0x42005400
MTB
EIC
Reserved
0x40001C00
0x40FFFFFF
0x41004700
0x41FFFFFF
Reserved
Reserved
RFCTRL
Reserved
0x42005800
0x40FFFFFF
Note 1. SERCOM4 is internally connected to the AT86RF233.
This figure represents the full configuration of the Atmel | SMART SAM R21 with maximum Flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 4 for details.
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7.
Processor And Architecture
7.1
Cortex M0+ Processor
The Atmel | SMART SAM R21 implements the ARM® Cortex™-M0+ processor, which is based on the ARMv6
Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0
processor, and upward compatible to Cortex-M3 and M4 processors.
For more information refer to www.arm.com.
7.1.1 Cortex M0+ Configuration
Atmel | SMART SAM R21
configuration
Features
Configuration option
External interrupts 0-32
Little-endian or big-endian
Present or absent
0, 1, 2
Interrupts
32
Data endianness
Little-endian
Present
2
SysTick timer
Number of watchpoint comparators
Number of breakpoint comparators
Halting debug support
Multiplier
0, 1, 2, 3, 4
4
Present or absent
Fast or small
Present
Fast (single cycle)
Present
Not supported
Present
Absent(1)
Not present
Absent
Single-cycle I/O port
Wake-up interrupt controller
Vector Table Offset Register
Unprivileged/Privileged support
Memory Protection Unit
Reset all registers
Present or absent
Supported or not supported
Present or absent
Present or absent
Not present or 8-region
Present or absent
16-bit only or mostly 32-bit
Instruction fetch width
32-bit
Note: 1. All software run in privileged mode only
The ARM Cortex-M0+ core has two bus interfaces:
z
Single 32-bit AMBA®-3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
z
Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
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8.
Packaging Information
8.1
Thermal Considerations
8.1.1 Thermal Resistance Data
Table 8-1 summarizes the thermal resistance data depending on the package.
Table 8-1. Thermal Resistance Data
Package Type
32-pin QFN
48-pin QFN
θJA
θJC
37.2 °C/W
33 °C/W
3.1 °C/W
11.4 °C/W
8.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
where:
z
z
z
z
z
θ
θ
θ
JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1.
JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1.
HEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
PD = device power consumption (W).
TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary
or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average
chip-junction temperature TJ in °C.
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8.2
Package Drawings
8.2.1 48-pin QFN
Table 8-2. Device and Package Maximum Weight
100
mg
Table 8-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-4. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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8.2.2 32-pin QFN
Table 8-5. Device and Package Maximum Weight
90
mg
Table 8-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-7. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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8.3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Profile Feature
Green Package
3°C/s max
150-200°C
60-150s
Average Ramp-up Rate (217°C to peak)
Preheat Temperature 175°C +/-25°C
Time Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
30s
260°C
Ramp-down Rate
6°C/s max
8 minutes max
Time 25°C to Peak Temperature
A maximum of three reflow passes is allowed per component.
SVNREVISION
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Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1
SAM R21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
SAM R21G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
SAM R21 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1
SAM R21G - QFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
SAM R21E - QFN32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . .12
5.1
5.2
5.3
Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7.1
Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8.1
8.2
8.3
Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
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