ATR2406 [ATMEL]
LOW IF .4 GHZ ISM TRANSCEIVER; 低中频0.4 GHz的ISM收发器
| 型号： | ATR2406 |
| 厂家： | 
ATMEL |
| 描述： | LOW IF .4 GHZ ISM TRANSCEIVER |
| 文件： | 总20页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fully Integrated Low IF Receiver
• Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 kBit/s
• High Sensitivity of Typically -93 dBm Due to Integrated LNA
• High Output Power of Typically +4 dBm
• Multi-channel Operation
– 95 Channels
– Support Frequency Hopping (ETSI) and Digital Modulation (FCC)
• Supply-voltage Range 2.9 V to 3.6 V (Unregulated)
• Auxiliary-voltage Regulator on Chip (3.2 V to 4.6 V)
• Low Current Consumption
• Few Low Cost External Components
• Integrated Ramp-signal Generator and Power Control for an Additional
Power Amplifier
Low IF 2.4 GHz
ISM Transceiver
• Low Profile Lead-free Plastic Package QFN32 (5 × 5 × 0.9 mm)
ATR2406
Applications
• Hightech Multi-user Toys
• Wireless Game Controllers
• Telemetry
• Wireless Audio/Video
Preliminary
• Electronic Point of Sales
• Wireless Head Set
• FCC CFR47, Part 15, ETSI EN 300 328 and ARIB STD-T-66 Compliant Radio Links
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATR2406 is a single chip RF-transceiver intended for applications in the 2.4 GHz
ISM band. The QFN32 packaged IC is a complete transceiver including image rejec-
tion mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping
generator for external power amplifier, integrated synthesizer, and a fully integrated
VCO and TX filter. No mechanical adjustment is necessary in production.
The RF-transceiver offers a clock recovery function on-chip.
Rev. 4779F–ISM–09/04
Figure 1. Block Diagram
REG_DEC
VREG REG_CTRL VS_REG IREF
VS_SYN
VS_IFD
VS_IFA
VCO
REG
AUX
VREF
REG
VREG_VCO
RX_IN
VS_RX/TX
LNA
LIMITER
RSSI
IR-MIXER
BP
DEMOD
RX_DATA
RSSI
PA
VCO
CLOCK
DATA
TX_OUT
BUS
ENABLE
RX-CLOCK
PU_REG
PU_TRX
RX_ON
TX_ON
GAUSSIAN
FILTER
CTRL
LOGIC
RAMP
GEN
RAMP_OUT
PLL
nOLE
REF_CLK TX_DATA VTUNE
CP
Pin Configuration
Figure 2. Pinning QFN32 - 5 × 5
32 31 30 29 28 27 26 25
24 RX_ON
PU_REG
1
2
3
4
5
6
7
8
REF_CLK
RSSI
23
22
IC
IC
VS_IFD
VS_IFA
RX-CLOCK
IC
21 RAMP_OUT
20 TX_OUT
19 RX_IN1
18 RX_IN2
17 VS_TRX
ATR2406
IREF
9 10 11 12 13 14 15 16
2
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Pin Description
Pin
Symbol
Function
1
PU_REG
REF_CLK
RSSI
Power-up input for auxiliary regulator
Reference frequency input
Received signal strength indicator output
Digital supply voltage
2
3
4
VS_IFD
VS_IFA
RX-CLOCK
IC
5
Analog supply voltage for IF circuits
RX-CLOCK, if RX mode with clock recovery is active
Internal connected, do not connect on PCB
External resistor for band-gap reference
Auxiliary voltage regulator control output
Auxiliary voltage regulator output
Auxiliary voltage regulator supply voltage
Decoupling pin for VCO_REG
VCO voltage regulator
6
7
8
IREF
9
REG_CTRL
VREG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Paddle
VS_REG
REG_DEC
VREG_VCO
VTUNE
CP
VCO tuning voltage input
Charge-pump output
VS_SYN
VS_TRX
RX_IN2
RX_IN1
TX_OUT
RAMP_OUT
IC
Synchronous supply voltage
Transmitter receiver supply voltage
Differential receiver input 2
Differential receiver input 1
TX driver amplifier output
Ramp generator output for PA power ramping
Internal connected, do not connect on PCB
Internal connected, do not connect on PCB
RX control input
IC
RX_ON
TX_ON
nOLE
TX control input
Open loop enable input
PU_TRX
RX_DATA
TX_DATA
CLOCK
DATA
RX/TX/PLL/VCO power-up input
RX data output
TX data input
3-wire-bus: Clock input
3-wire-bus: Data input
ENABLE
GND
3-wire-bus: Enable input
Ground
3
4779F–ISM–09/04
Functional Description
Receiver
The RF signal at RF_IN is differently fed through the LNA to the image rejection mixer
IR_MIXER driving the integrated LowIF bandpass filter. The IF frequency is
864 kHz.The limiting IF_AMP with an integrated RSSI function feeds the signal to the
digital demodulator DEMOD. No tuning is required. Datasling is handled internally.
Clock Recovery
For 1152 kBit/s data rate the receiver has a clock recovery function on-chip.
The receiver includes a clock recovery circuit which regenerates the clock out of the
received data. The advantage is that this recovered clock is synchronous to the clock of
the transmitting device (and thus to the transmitted data) which allows to reduce the
load of the processing microcontroller significantly.
The falling edge of the clock gives the optimal sampling position for the RX_Data signal
so at this event the data must be sampled by the microcontroller. The recovered clock is
available at pin 6.
Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to
the fully integrated VCO operating at twice the output frequency. After modulation the
signal is frequency-divided by 2 and fed to the internal preamplifier PA. This preamplifier
supplies typically +4 dBm output power at TX_OUT.
A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the
external power amplifier, is integrated. The slope of the ramp signal is controlled inter-
nally so that spurious requirements are fulfilled.
Synthesizer
The IR_MIXER, the PA and the programmable counter PC are driven by the fully inte-
grated VCO, using on-chip inductors and varactors. The output signal is frequency
divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter
for the IR_MIXER and to be used by the PC for the phase detector PD
(fPD = 1.728 MHz). Open loop modulation is supported.
Power Supply
An integrated bandgap-stabilized voltage regulator for use with an external low-cost
PNP transistor is implemented. Multiple power-down and current saving modes are
provided.
4
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
-0.3
-0.3
-0.3
-40
Max.
+4.7
+3.6
VS
Unit
V
Supply voltage auxiliary regulator
Supply voltage
VS
V
Control voltages
Vcontr
Tstg
V
Storage temperature
Input RF level
+125
+10
°C
dBm
V
PRF
VESD_anal
VESD_dig
TBD
TBD
ESD protection
V
Operating Range
Parameters
Symbol
VS
Min.
2.9
Max.
3.6
Unit
V
Supply voltage
Auxiliary regulator supply voltage
Temperature ambient
Input frequency range
VS_BATT
Tamb
3.2
4.6
V
-10
+60
2483
°C
fRX
2400
MHz
Electrical Characteristics
VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Supply
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
1
1.1 Supply voltage
With AUX regulator
w/o AUX regulator
CW-mode
VS
VS
IS
3.2
2.9
3.6
3.0
31
4.6
3.6
V
1.2 Supply voltage
V
1.3 RX supply current
1.4 TX supply current
1.5 Synthesizer supply current
mA
mA
mA
CW-mode
IS
16
IS
26
Supply current in power-down
mode
With AUX regulator
PU_TRX = 0; PU_REG = 0
1.6
IS
IS
< 1
< 1
µA
µA
Supply current in power-down
mode
w/o AUX regulator
PU_TRX = 0; PU_REG = 0
1.7
2
Voltage Regulator
2.1 AUX regulator
2.2 VCO regulator
VREG
3.0
2.7
V
V
VREG_VCO
3
Transmitter Part
3.1 TX data rate
72/144/288/576/1152
kBit/s
dBm
Over full temperature range, from
2400 MHz to 2483 MHz(1)
3.2 Output power
PTX
0
4
Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For
further information refer to Application Note.
5
4779F–ISM–09/04
Electrical Characteristics (Continued)
VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Test Conditions
Symbol
fTXFCLK
Min.
Typ.
6.912
±400
Max.
Unit
MHz
kHz
3.3 TX data filter clock
3.4 Frequency deviation
6 taps in filter
GFFM_nom
GFFM = GFFM_nom × GFCS
(see bus protocol D9 to D11)
3.5 Frequency deviation scaling
GFCS
60
130
±10
%
3.6 Frequency drift during a slot
∆fo (drift)
kHz
Harmonics
3.7 2nd Harmonic
3rd Harmonic
BW = 100 kHz(1)
BW = 100 kHz(1)
-40.5
-46
dBc
dBc
Spurious Emission
30 - 1000 MHz
3.8 1 - 12.75 GHz
1.8 - 1.9 GHz
-40.5
-48
-70
dBm
dBm
dBm
dBm
5.15 - 5.3 GHz
-70
4
Receiver Part
At input for BER ≤10-3
4.1 Sensitivity
-93
-15
dBm
dBm
at 1152 kBit/s(1)
4.2 Third order input intercept point
IIP3
IM3
BER < 10-3, wanted at -83 dBm,
level of interferers in channels
N + 2 and N + 4(1)
4.3 Intermodulation rejection
4.4 Co-channel rejection
32
dBc
dBc
BER < 10-3, wanted at -76 dBm(1)
RCO
-11
BER < 10-3, wanted at -76 dBm,
adjacent level referred to wanted
channel level(1)
4.5 Adjacent channel rejection
4.6 Bi-adjacent channel rejection
Ri (N-1)
Ri (N - 2)
Ri (n ≥ 3)
4
dBc
dBc
dBc
±1.728 MHz
BER < 10-3, wanted at -76 dBm, bi-
adjacent level referred to wanted
channel level(1)
30
40
±3.456 MHz
BER < 10-3, wanted at -76 dBm,
n ≥ 3 adjacent level referred to
wanted channel level(1)
≥ ±5.128 MHz
Rejection with ≥ 3 channels
4.7
separation
BER < 10-3, wanted at -83 dBm at
2.45 GHz(1)
4.8 Out of band rejection > 6 MHz
Out of band rejection
Bldf>6MHz
Blnear
38
47
dBc
dBc
BER < 10-3, wanted at -83 dBm at
2.45 GHz(1)
4.9
2300 MHz to 2394 MHz
2506 MHz to 2600 GHz
Out of band rejection
BER < 10-3, wanted at -83 dBm at
2.45 GHz(1)
4.10
Blfar
57
dBc
30 MHz to 2300 MHz
2600 MHz to 6 GHz
5
RSSI Part
5.1 Maximum RSSI output voltage Under high RX input signal level
VRSSImax
2.1
V
Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For
further information refer to Application Note.
6
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Electrical Characteristics (Continued)
VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
RSSI output voltage, monotonic with -33 dBm at RF input
over range -96 dBm to -36 dBm with -96 dBm at RF input
1.9
0.3
V
V
5.2
VRSSI
Wake-up time from power-up
signal to correct RSSI output
5.3
Ton
40
µs
6
VCO
6.1 Oscillator frequency
Over full temperature range(1)
2400
0.5
2483
MHz
V
6.2 Frequency control voltage range
6.3 VCO tuning input gain
VVTUNE
GVCO
VCC - 0.5
150
MHz/V
7
Synthesizer
External reference input
frequency
D7 = 0
D7 = 1
10.368
13.824
MHz
MHz
7.1
REF_CLK
REF_CLK
Sinusoidal input signal level
(RMS value)
7.2
AC coupled sinewave
250
0
500
31
mVRMS
7.3 Scaling factor prescaler
SPSC
SMC
SSC
32/33
7.4 Scaling factor main counter
7.5 Scaling factor swallow counter
86/87/88/89
8
8.1
9
Phase Detector
Phase detector comparison
frequency
fPD
1728
kHz
Charge-pump Output
9.1 Charge-pump output current
9.2 Leakage current
VCP = 1/2 VCC
VCP = 1/2 VCC
ICP
IL
±2
mA
pA
±100
10 Timing Conditions(1)(2)
10.1 Transmit to Receive time
10.2 Receive to Transmit time
10.3 Channel switch time
10.4 Power down to Transmit
10.5 Power down to Receive
10.6 Programming register
10.7 PLL settling time
TX →RX-time
RX →TX-time
CS-time
100
100
350
450
400
3
µs
µs
µs
µs
µs
µs
µs
PD →TR-time
PD →RX-time
PRR-time
PLL set-time
350
11 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE
11.1 HIGH-level input voltage
11.2 LOW-level input voltage
11.3 HIGH-level output voltage
11.4 LOW-level output voltage
11.5 Input bias current
Logic 1
VIH
VIL
1.4
3.4
+0.4
3.4
V
V
Logic 0
-0.3
Logic 1
VOH
V
Logic 0
VOL
0
V
Logic 1 or logic 0
Ibias
-5
+5
10
µA
MHz
11.6 3-wire bus clock frequency
fCLKmax
Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For
further information refer to Application Note.
7
4779F–ISM–09/04
PLL Principle
Figure 3. PLL Principle
Programable counter PC
"- Main counter MC
"- Swallow counter SC
f
VCO = 1728 kHz × (SMC × 32 + SSC)
External
loop filter
PA driver
Mixer
Phase frequency
detector PD
fPD = 1728 kHz
Divider
by 2
Charge
pump
VCO
Gaussian
filter GF
Reference counter RC
REF_CLK
D7
10.368 MHz
13.824 MHz
0
1
TXDAT
PLL reference
Frequency
REF_CLK
Baseband controller
8
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
The following table shows the LO frequencies for RX and TX in the 2.4 GHz ISM band. There are 95 channels available.
Since the ATR2406 supports wideband modulation with 400 kHz deviation, every second channel can be used without
overlap in the spectrum.
Table 1. LO Frequencies
Mode
fIF/kHz
Channel
C0
fANT/MHz
2401.056
2401.920
...
fVCO/MHz
2401.056
2401.920
...
SMC
86
86
...
SSC
27
28
...
N
2779
2780
...
C1
TX
...
C93
C94
C0
2481.408
2482.272
2401.056
2401.920
...
2481.408
2482.272
2401.920
2402.784
...
89
89
86
86
...
24
25
28
29
...
2872
2873
2780
2781
...
C1
RX
864
...
C93
C94
2481.408
2482.272
2482.272
2483.136
89
89
25
26
2873
2874
TX Register Setting
The following 16-bit word has to be programmed for TX.
MSB
LSB
Data bits
D15
0
D14
1
D13
D12
D11
D10
D9
D8
1
D7
D6
D5
D4
D3
D2
SC
D1
D0
PA
GFCS
RC
MC
Note:
D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0
or 1.
Table 2. Output Power Settings with Bits D12 - D13
PA (Output Power Settings)
D13
0
D12
0
RAMP_OUT (Pin 21)
1.3 V
1.35 V
1.4 V
0
1
1
0
1
1
1.75 V
9
4779F–ISM–09/04
RX Register Setting
The are two RX settings possible. For a data rate of 1152 kBit/s an internal clock recov-
ery function is implemented.
Register Setting without Must be used for data rates below 1.152 Mbit.
Clock Recovery
MSB
LSB
Data bits
D15
0
D14
1
D13
X
D12
X
D11
X
D10
X
D9
X
D8
0
D7
D6
D5
D4
D3
D2
SC
D1
D0
RC
MC
Note:
X values are not relevant and can be set to 0 or 1.
RX Register Setting with Recommended for 1.152 Mbit data rate.
Internal Clock Recovery
The output pin of the recovered clock is pin 6. The falling edge of the recovered clock
signal samples the data signal.
MSB
Data bits
D24
D23
0
D22
1
D21
0
D20
0
D19
0
D18
0
D17
0
D16
0
1
LSB
D15
0
D14
0
D13
X
D12
X
D11
X
D10
X
D9
X
D8
0
D7
D6
D5
D4
D3
D2
SC
D1
D0
RC
MC
Note:
X values are not relevant and can be set to 0 or 1.
PLL Settings
RC, MC and SC bits are controlling the synthesizer frequency according to Table 3,
Table 4 and Table 5.
Formula for calculating the frequency:
TX frequency: fANT = 864 kHz × (32 × SMC + SSC
)
RX frequency: fANT = 864 kHz × (32 × SMC + SSC + 1)
Table 3. PLL Settings with the Reference Counter Bit D7
RC (Reference Counter)
D7
0
CLK Reference
10.368 MHz
1
13.824 MHz
10
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Table 4. PLL Settings with the Main Counter Bits D5 - D6
MC (Main Counter)
D6
0
D5
0
SMC
86
0
1
87
1
0
88
1
1
89
Table 5. PLL Settings with the Swallow Counter Bits D0 - D4
SC (Swallow Counter)
D4
0
D3
0
D2
0
D1
0
D0
0
SSC
0
0
0
0
0
1
1
0
0
0
1
0
2
...
1
...
1
...
1
...
0
...
1
...
29
30
31
1
1
1
1
0
1
1
1
1
1
GFCS Adjustment
The Gaussian Filter Control Setting is used to compensate production tolerances by
tuning the modulation deviation in production to the nominal value of 400 kHz. These
bits are only relevant in TX mode.
Table 6. GFCS Adjustment with Bits D9 - D11
GFCS (Gaussian Filter Control Settings)
D11
0
D10
0
D9
0
GFCS
60%
0
0
1
70%
0
1
0
80%
0
1
1
90%
1
0
0
100%
110%
120%
130%
1
0
1
1
1
0
1
1
1
The VRAMP voltage is used to control the output power of an external power amplifier.
The voltage ramp is started with the TX_ON signal.
These bits are only relevant in TX mode.
11
4779F–ISM–09/04
Control Signals
The various transceiver functions are activated by the following control signals. A timing
proposal is given in Figure 5 on page 13
Table 7. Control Signals – Functions
Signal
Functions
Activates AUX voltage regulator and the VCO voltage regulator
supplying the complete transceiver
PU_REG
PU_TRX
RX_ON
Activates RX/TX blocks
Activates RX circuits: DEMOD, IF AMP, IR MIXER
Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at
RAMP_OUT
TX_ON
nOLE
Disables open loop mode of the PLL
Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE).
After setting enable signal to low condition, on the rising edge of the clock signal, the
data is transferred bit by bit into the shift register, starting with the MSB-bit. When the
enable signal has returned to high condition, the programmed information is active.
Additional leading bits are ignored and there is no check made how many clock pulses
arrived during enable low condition.
The programming of the transceiver is done by a 16 bit or 25 bit data word (for the RX
clock recovery mode).
3-wire BUS Timing
Figure 4. 3-wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TC
TH
TPER
TEC
TT
TL
TS
Table 8. 3-wire Bus Protocol Table
Description
Symbol
TPER
TS
Minimum Value
Unit
ns
Clock period
100
20
Set time data to clock
Hold Time data to clock
Clock pulse width
ns
TH
20
ns
TC
60
ns
Set time enable to clock
Hold time enable to data
Time between two protocols
TL
100
0
ns
TEC
TT
ns
250
ns
12
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Figure 5. Complete TX and RX Timing Diagram
)
p u u t t O X ( T R o r m s f g n S a i l
)
n I p u X t ( T R o s t g n S a i l
13
4779F–ISM–09/04
Table 9. Description of the Conditions/States
Conditiion
Description
Power-down
C1
ATR2406 is switched off and the supply current is lower than 1 µA.
Power-up
ATR2406 is powered up by toggling PU_REG and PU_RTX to high.
PU_REG enables the external AUX-Regulator transistor and PU_TRX
enables the internal regulator like VCO_REG (VCO supply voltage
regulator) as well as wakes up the PLL, the VCO, the demodulator,
mixer, etc.
C2
It is necessary to wait at least 40 µs until the different supply voltage
regulators have settled.
Programming
Via the tree-wire-interface the internal register of ATR2406 is programmed.
At TX, this is just the PLL (transmit channel) and the deviation (gaussian
filter).
At RX, this is just the PLL (receive channel) and if the clock recovery is
used also the bits to enable this option. At start of the
three-wire-programming, the enable signal is toggled from high to low to
enable clocking the data into the internal register. When the enable signals
rises again to high, the programmed data is latched. This is the time point
at which the settling of the PLL is starting. It is necessary to wait the
settling time of 350 µs so that the VCO-Frequency is stable.
The reference clock needs to be applied to ATR2406 at minimum the time
when the PLL is in operation - which is the programming state (C3) and the
active slot (C4, C5). Out of the reference clock, several internal signals are
also derived, i.e., the gaussian filter circuitry and TX_DATA sampling.
C3
This is the receive slot where the transmit burst is received and data as
well as recovered clock are available.
C4
C5
This is the active transmit slot. As soon as TX_DATA is applied to
ATR2406, the signal nOLE toggles to low which enables modulation in
open-loop-mode.
ReceivedSignalStrength The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value
is shown in Figure 6.
Indication RSSI
Figure 6. Typical RSSI Value versus Input Power
2.5
2.0
1.5
1.0
0.5
0.0
-130
-110
-90
-70
-50
-30
-10
10
RF Level (dBm)
14
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Application Circuit
The ATR2406 requires only few low cost external components for operation. A typical
application is shown in Figure 7.
Figure 7. Application Circuit
N C
R 1
J 2 4
8
2
2
1 p
C 3
2 p
0
8 2
C 7
2 p
R 6
C 6
p i r t µ S
G N D 3
G N D 1
G N D 6
G N D 5
G N D 4
G N D 9
G N D 8
G N D 7
B V A T T
G N D 2
3 p i n r 3 µ S t
_ O P U M T R A
_ O N R X
N C
5
1 k
C 1 4
R 4
3 9 0 p
N O T X _
L E n O
C 4
G N D
G
N
_ O T X
N
_ S Y V S
C P
V T U N
2 5
1 6
1 5
L E n O
X R T _ P U
2 6
2 7
2 8
2 9
3 0
3 1
3 2
R T X P U _
A T A R X _ D
A T _ D T A X
A T _ D A R X
E
6 8 p
1 4
1 3
1 2
1 1
O
_ V G C V R E
G _ D R E
N C
A T D A T X _
C 1 8
7 4 0 n
C
C 1 7
O C C K L
A T D A
G E R _ V S
E G V R
K
C L O C
T A D A
L E A B E N
1 0
C 1 9
E L B E N A
R T L C _ G R E
9
6 2 k
R 3
E G R _ P U
F _ C R L E K
4 n 7
1 8 p
C 1 1
4 p 7
C 2 3
C 2 4
J 2
S V
I
R S S
L O C C K R X -
15
4779F–ISM–09/04
PCB-layout Design
Figure 8. PCB-layout ATR2406-DEV-BOARD
16
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Table 10. Bill of Material
Part
C1
Value
5p6
1p8
390p
4p7
2p2
2p2
1p5
1p8
18P
100n
4µ7
1n
Part Number
Vendor
Package
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
3216
0402
0402
3216
0402
0402
0402/0603
0805
0603
0402
0402
0402
0402
0402
0402
0402
MLF32
Comment
GJM1555C1H5R6CB01 or GRM1555C1H5R6DZ01 Murata®
C3
GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata
C4
GRM1555C1H391JA01
Murata
C5
GJM1555C1H4R7CB01 or GRM1555C1H4R7CZ01 Murata
GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata
GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata
GJM1555C1H1R5CB01 or GRM1555C1H1R5CZ01 Murata
GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata
NC
C6
C7
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C23
C24
L6
GRM1555C1H180JB01
GRM15F51H104ZB01
Murata
Murata
Epcos®
Murata
Murata
Epcos
B45196H2475M109
Optional2
NC
GRM15R71H102KB01
GRM15F51H104ZB01
100n
4µ7
3n3
68p
470n
B45196H2475M109
Optional2
NC
GRM15R71H332KB01
GRM155C1H680JB01
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Würth Electronic®
Vishay®
Vishay
GRM18F51H474ZB01 (0402) or 0603-Version
22n, COG GRM21B5C1H223JA01
2n2, COG GRM1885C1H222JA01
4n7
4p7
8n2
62k
GRM15R71H472KB01
GRM1555C1H4R7CB01
WE-MK0402 744784082
62k, ←5%
NC, µStrip used
R3
R4
1k5
1k5, ←5%
R5
3k3
3k3, ←5%
Vishay
Ref_Clk-Level, optional1
Ref_Clk-Level, optional1
R6
820R
820R, ←5%
Vishay
IC2
ATR2406 ATR2406
Atmel
BC808-40, any standard type can be used,
important is "-40"
Vishay, Philips®,
...
T1
BC808-40
SOT-23
Optional2
MSUB
FR4
FR4, e_r = 4.4 at 2.45 GHz, H = 500 µm, T = 35 µm, tand = 0.02, surface i.e. chem. tin or chem. gold
Note:
Option1 = no necessary if supplied RefClk level is within specification range
Option2 = if no AUX regulator is used, then T1 has to be bypassed
To use the integrated F-antenna, set jumper R2 (0R resistor 0603)
Table 11. Parts Count Bill of Material
Parts Count
Required (Minimal BOM)
Optional (Depending on Application)
Capacitors 0402
Capacitors >0402
Resistors 0402
Inductors 0402
Semiconductors
14
2
-
2
2
-
2
-
1
1
17
4779F–ISM–09/04
Ordering Information
Extended Type Number
Package
Remarks
MOQ
600
6000
1
ATR2406-PNSG
QFN32 - 5x5
Tube, Sampling; Pb-free
Taped and reeled; Pb-free
RF-module
ATR2406-PNQG
QFN32 - 5x5
ATR2406-DEV-BOARD
ATR2406-DEV-KIT
-
-
Complete Evaluation-kit
1
Package Information
18
ATR2406 [Preliminary]
4779F–ISM–09/04
ATR2406 [Preliminary]
Recommended Footprint/Landing Pattern
Figure 9. Recommenced Footprint/Landing Pattern
Table 1. Recommended Footprint/Landing Pattern Signs
Sign
A
Size
3.2 mm
1.2 mm
0.3 mm
1.1 mm
0.3 mm
0.2 mm
0.55 mm
0.5 mm
B
C
a
b
c
d
e
19
4779F–ISM–09/04
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Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.
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4779F–ISM–09/04
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