ATR2406_08 [ATMEL]
Low-IF 2.4-GHz ISM Transceiver; 低中频的2.4GHz ISM收发器
| 型号： | ATR2406_08 |
| 厂家： | 
ATMEL |
| 描述： | Low-IF 2.4-GHz ISM Transceiver |
| 文件： | 总25页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fully Integrated Low IF Receiver
• Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 Kbits/s
• High Sensitivity of Typically –93 dBm Due to Integrated LNA
• High Output Power of Typically +4 dBm
• Multi-channel Operation
– 95 Channels
– Support Frequency Hopping (ETSI) and Digital Modulation (FCC)
• Supply-voltage Range 2.9V to 3.6V (Unregulated)
• Auxiliary Voltage Regulator on Chip (3.2V to 4.6V)
• Low Current Consumption
Low-IF 2.4-GHz
ISM Transceiver
• Few Low-cost External Components
• Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier
• Low Profile Lead-free Plastic Package QFN32 (5 mm × 5 mm × 0.9 mm)
• RoHs Compliant
ATR2406
Applications
• High-tech Multi-user Toys
• Wireless Game Controllers
• Telemetry
• Wireless Audio/Video
• Electronic Point of Sales
• Wireless Head Set
• FCC CFR47, Part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 Compliant Radio
Links
1. Description
The ATR2406 is a single chip RF transceiver intended for applications in the 2.4-GHz
ISM band. The QFN32-packaged IC is a complete transceiver including image rejec-
tion mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping
generator for external power amplifier, integrated synthesizer, and a fully integrated
VCO and TX filter. No mechanical adjustment is necessary in production.
The RF transceiver offers a clock recovery function on-chip.
4779N–ISM–12/08
Figure 1-1. Block Diagram
REG_DEC VREG REG_CTRL VS_REG IREF
VS_SYN
VS_IFD
VCO
REG
AUX
REG
AUX
REG
VREG_VCO
RX_IN
VS_IFA
VS_RX/TX
LIMITER
RSSI
DEMOD
LNA
IR-Mixer
BP
RX_DATA
RSSI
PA
VCO
CLOCK
DATA
Divider
by 2
TX_OUT
BUS
ENABLE
TEST1
TEST2
PU_REG
PU_TRX
RX_ON
TX_ON
nOLE
GAUSSIAN
FILTER
RAMP
GEN
CTRL
LOGIC
RAMP_OUT
PLL
CP REF_CLK TX_DATA
VTUNE
2. Pin Configuration
Figure 2-1. Pinning QFN32 - 5 × 5
32 31 30 29 28 27 26 25
1
PU_REG
REF_CLK
RSSI
24 RX_ON
2
3
4
5
6
7
8
23
22
IC
IC
VS_IFD
VS_IFA
RX-CLOCK
IC
21 RAMP_OUT
20 TX_OUT
19 RX_IN1
18 RX_IN2
17 VS_TRX
ATR2406
IREF
9 10 11 12 13 14 15 16
2
ATR2406
4779N–ISM–12/08
ATR2406
Table 2-1.
Pin Description
Symbol
PU_REG
REF_CLK
RSSI
Pin
1
Function
Power-up input for auxiliary regulator
Reference frequency input
2
3
Received signal strength indicator output
Digital supply voltage
4
VS_IFD
VS_IFA
RX-CLOCK
IC
5
Analog supply voltage for IF circuits
RX-CLOCK, if RX mode with clock recovery is active
Internally connected. Connect to VS if internal AUX regulator is not used
External resistor for band-gap reference
Auxiliary voltage regulator control output
Auxiliary voltage regulator output
Auxiliary voltage regulator supply voltage
Decoupling pin for VCO_REG
VCO voltage regulator
6
7
8
IREF
9
REG_CTRL
VREG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Paddle
VS_REG
REG_DEC
VREG_VCO
VTUNE
CP
VCO tuning voltage input
Charge-pump output
VS_SYN
VS_TRX
RX_IN2
RX_IN1
TX_OUT
RAMP_OUT
IC
Synchronous supply voltage
Transmitter receiver supply voltage
Differential receiver input 2
Differential receiver input 1
TX driver amplifier output
Ramp generator output for PA power ramping
Internally connected, do not connect on PCB
Internally connected, do not connect on PCB
RX control input
IC
RX_ON
TX_ON
nOLE
TX control input
Open loop enable input
PU_TRX
RX_DATA
TX_DATA
CLOCK
DATA
RX/TX/PLL/VCO power-up input
RX data output
TX data input
3-wire-bus: Clock input
3-wire-bus: Data input
ENABLE
GND
3-wire-bus: Enable input
Ground
3
4779N–ISM–12/08
3. Functional Description
3.1
Receiver
The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer
IR_MIXER, driving the integrated low-IF band-pass filter. The IF frequency is 864 kHz. The limit-
ing IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator
DEMOD. No tuning is required. Data slicing is handled internally.
3.2
Clock Recovery
For a 1152-kBit/s data rate, the receiver has a clock recovery function on-chip.
The receiver includes a clock recovery circuit which regenerates the clock out of the received
data. The advantage is that this recovered clock is synchronous to the clock of the transmitting
device (and thus to the transmitted data), which significantly reduces the load of the processing
microcontroller.
The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this
event the data must be sampled by the microcontroller. The recovered clock is available at pin 6.
3.3
Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the
fully integrated VCO operating at twice the output frequency. After modulation, the signal is fre-
quency divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically
+4 dBm output power at TX_OUT.
A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external
power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spuri-
ous requirements are fulfilled.
3.4
3.5
Synthesizer
The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated
VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the
desired frequency to the TX_DRIVER, the 0/90 degree phase shifter for the IR_MIXER, and to
be used by the PC for the phase detector (PD) (fPD = 1.728 MHz). Open loop modulation is
supported.
Power Supply
An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP tran-
sistor is implemented. Multiple power-down and current saving modes are provided.
4
ATR2406
4779N–ISM–12/08
ATR2406
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
–0.3
–0.3
–0.3
–40
Max.
+4.7
+3.6
VS
Unit
V
Supply voltage auxiliary regulator
Supply voltage
VS
V
Control voltages
Vcontr
Tstg
V
Storage temperature
Input RF level
+125
+10
°C
dBm
V
PRF
VESD_ana
VESD_dig
TBD
TBD
ESD protection
V
Electrostatic sensitive device.
Observe precautions for handling.
5. Operating Range
Parameters
Symbol
VS
Min.
2.9
Max.
3.6
Unit
V
Supply voltage
Auxiliary regulator supply voltage
Temperature ambient
Input frequency range
VS_BATT
Tamb
3.2
4.6
V
–10
2400
+60
2483
°C
fRX
MHz
5
4779N–ISM–12/08
6. Electrical Characteristics
VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Supply
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
1
1.1 Supply voltage
1.2 Supply voltage
With AUX regulator
VS
VS
IS
3.2
2.9
3.6
3.0
57
4.6
3.6
V
Without AUX regulator
CW mode (peak current)
Burst mode at 10 Kbits/s(4)
CW mode (peak current)
Burst mode at 10 Kbits/s(4)
V
mA
µA
mA
µA
1.3 RX supply current
1.4 TX supply current
IS
625
42
IS
IS
500
Battery lifetime of a remote
1.5 control application using an
AVR®
See Section 10. “Appendix: Current
Calculations for a Remote Control”
on page 20
Supply current in power-down
mode
With AUX regulator
PU_TRX = 0; PU_REG = 0
1.6
IS
IS
< 1
< 1
µA
µA
Supply current in power-down
mode
Without AUX regulator
PU_TRX = 0; PU_REG = 0
1.7
2
Voltage Regulator
2.1 AUX regulator
2.2 VCO regulator
VREG
3.0
2.7
V
V
VREG_VCO
3
Transmitter Part
3.1 TX data rate
72/144/288/576/1152
kBits/s
dBm
MHz
kHz
3.2 Output power
PTX
4
3.3 TX data filter clock
3.4 Frequency deviation
9 taps in filter
fTXFCLK
10.368/13.824
±400
To be tuned by GFCS bits
GFFM_nom
GFFM = GFFM_nom × GFCS
(Refer to bus protocol D9 to D11)
3.5 Frequency deviation scaling(3)
GFCS
60
130
%
With standard loop filter and slot
length of 1400 µs (Refer to the
application note “ATR2406 Loop
Filter and Data Rates”)
3.6 Frequency drift
3.7 Harmonics
Δfo (drift)
±40
kHz
BW = 100 kHz(1)
–41.2
dBm
Spurious emissions
30 – 1000 MHz
3.8 1 – 12.75 GHz
1.8 – 1.9 GHz
–57
–57
–57
–57
dBm
dBm
dBm
dBm
BW = 100 kHz(1)
5.15 – 5.3 GHz
4
Ramp Generator, Pin 21
4.1 Minimum output voltage
4.2 Maximum output voltage
4.3 Rise time
TX_ON = low
Vmin
Vmax
tr
0.7
V
V
Refer to bus protocol D12 to D13
1.1
1.9
5
5
µs
µs
4.4 Fall time
tf
Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-
quency (Smart RF) firmware. Conducted measured.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.
For further information refer to the application notes.
3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation
in production to the nominal value of 400 kHz.
4. Burst mode with 0.9% duty cycle
6
ATR2406
4779N–ISM–12/08
ATR2406
6. Electrical Characteristics (Continued)
VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Receiver Part
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
5
5.1 RX input impedance
Differential
Zin
170 + j0
–93
Ω
At input for BER ≤ 10-3
at 1152 kBits/s(1)
5.2 Sensitivity
dBm
dBm
5.3 Third order input intercept point
IIP3
IM3
–15
BER < 10-3, wanted at -83 dBm,
level of interferers in channels
N + 2 and N + 4(1)
5.4 Intermodulation rejection
5.5 Co-channel rejection
32
–11
14
dBc
dBc
dBc
BER < 10-3, wanted at –76 dBm(1)
RCO
BER < 10-3, wanted at –76 dBm,
adjacent level referred to wanted
channel level(1)
Adjacent channel rejection
±1.728 MHz
5.6
Ri (N – 1)
BER < 10-3, wanted at –76 dBm,
bi-adjacent level referred to wanted
channel level(1)
Bi-adjacent channel rejection
±3.456 MHz
5.7
Ri (N – 2)
30
dBc
Rejection with ≥ 3 channels
5.8 separation
BER < 10-3, wanted at –76 dBm,
n ≥ 3 adjacent level referred to
wanted channel level(1)
Ri (n
≥
40
38
47
dBc
dBc
dBc
3)
≥ ±5.128 MHz
BER < 10-3, wanted at –83 dBm at
5.9 Out of band rejection > 6 MHz
Bldf>6MHz
2.45 GHz(1)
Out of band rejection
5.10 2300 MHz to 2394 MHz
2506 MHz to 2600 GHz
BER < 10-3, wanted at –83 dBm at
2.45 GHz(1)
Blnear
Out of band rejection
5.11 30 MHz to 2300 MHz
2600 MHz to 6 GHz
BER < 10-3, wanted at –83 dBm at
2.45 GHz(1)
Blfar
57
dBc
6
RSSI Part
6.1 Maximum RSSI output voltage Under high RX input signal level
VRSSImax
VRSSI
2.1
V
RSSI output voltage, monotonic With –33 dBm at RF input
1.9
0.1
V
V
6.2
over range –96 dBm to –36 dBm With –96 dBm at RF input
7
VCO
Oscillator frequency defined at
TX output
7.1
Over full temperature range(1)
2400
0.5
2483
MHz
V
7.2 Frequency control voltage range
VVTUNE
GVCO
VCC – 0.5
VCO tuning input gain defined at
TX output
7.3
240
MHz/V
Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-
quency (Smart RF) firmware. Conducted measured.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.
For further information refer to the application notes.
3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation
in production to the nominal value of 400 kHz.
4. Burst mode with 0.9% duty cycle
7
4779N–ISM–12/08
6. Electrical Characteristics (Continued)
VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
8
Synthesizer
External reference input
frequency
D7 = 0
D7 = 1
10.368
13.824
MHz
MHz
8.1
REF_CLK
REF_CLK
Sinusoidal input signal level
(peak-to-peak value)
8.2
AC-coupled sine wave
500
0
1000
31
mVPP
8.3 Scaling factor prescaler
SPSC
SMC
SSC
32/33
-
-
-
8.4 Scaling factor main counter
8.5 Scaling factor swallow counter
86/87/88/89
9
Phase Detector
Phase detector comparison
frequency
9.1
fPD
1728
kHz
10 Charge-pump Output
10.1 Charge-pump output current
10.2 Leakage current
V
CP = 1/2 VCC
ICP
IL
±2
mA
pA
VCP = 1/2 VCC
±100
1000
11 Timing Conditions(1)(2)
11.1 Transmit to receive time
11.2 Receive to transmit time
11.3 Channel switch time
11.4 Power down to transmit
11.5 Power down to receive
11.6 Programming register
11.7 PLL settling time
Reference clock stable
Reference clock stable
Reference clock stable
Reference clock stable
Reference clock stable
Reference clock stable
Reference clock stable
TX → RX time
RX → TX time
CS time
200
200
200
250
200
3
µs
µs
µs
µs
µs
µs
µs
PD → TR time
PD → RX time
PRR time
PLL set time
200
12 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE
12.1 HIGH-level input voltage
12.2 LOW-level input voltage
12.3 HIGH-level output voltage
12.4 LOW-level output voltage
12.5 Input bias current
Logic 1
VIH
VIL
1.4
3.1
+0.4
3.1
V
V
Logic 0
–0.3
Logic 1
VOH
V
Logic 0
VOL
0
V
Logic 1 or logic 0
Ibias
–5
+5
10
µA
MHz
12.6 3-wire bus clock frequency
fCLKmax
Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre-
quency (Smart RF) firmware. Conducted measured.
2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter.
For further information refer to the application notes.
3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation
in production to the nominal value of 400 kHz.
4. Burst mode with 0.9% duty cycle
8
ATR2406
4779N–ISM–12/08
ATR2406
7. PLL Principle
Figure 7-1. PLL Principle
Programable counter PC
"- Main counter MC
"- Swallow counter SC
fVCO = 1728 kHz × (SMC × 32 + SSC
)
External
loop filter
PA driver
Mixer
Phase frequency
detector PD
fPD = 1728 kHz
Divider
by 2
Charge
pump
VCO
Gaussian
filter GF
Reference counter RC
REF_CLK
D7
10.368 MHz
13.824 MHz
0
1
TXDAT
PLL reference
Frequency
REF_CLK
Baseband controller
9
4779N–ISM–12/08
Table 7-1 shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95
channels available. Since the ATR2406 supports wideband modulation with 400-kHz deviation,
every second channel can be used without overlap in the spectrum.
Table 7-1.
Mode
LO Frequencies
fIF / kHz
Channel
C0
fANT / MHz
2401.056
2401.920
...
fVCO / MHz divided by 2
2401.056
2401.920
...
SMC
86
86
...
SSC
27
28
...
N
2779
2780
...
C1
TX
RX
...
C93
C94
C0
2481.408
2482.272
2401.056
2401.920
...
2481.408
2482.272
2401.920
2402.784
...
89
89
86
86
...
24
25
28
29
...
2872
2873
2780
2781
...
C1
864
...
C93
C94
2481.408
2482.272
2482.272
2483.136
89
89
25
26
2873
2874
7.1
TX Register Setting
The following 16-bit word has to be programmed for TX.
MSB
LSB
D0
Data bits
D15
0
D14
1
D13
D12
D11
D10
D9
D8
1
D7
D6
D5
D4
D3
D2
SC
D1
PA
GFCS
RC
MC
Note:
D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0
or 1.
Table 7-2.
Output Power Settings with Bits D12 - D13
PA (Output Power Settings)
D13
0
D12
0
RAMP_OUT (Pin 21)
1.3V
1.35V
1.4V
0
1
1
0
1
1
1.75V
The VRAMP voltage is used to control the output power of an external power amplifier. The volt-
age ramp is started with the TX_ON signal.
These bits are only relevant in TX mode.
10
ATR2406
4779N–ISM–12/08
ATR2406
7.2
7.3
RX Register Setting
There are two RX settings possible. For a data rate of 1152 kBits/s, an internal clock recovery
function is implemented.
Register Setting Without Clock Recovery
Must be used for data rates below 1.152 Mbits/s.
MSB
LSB
D0
Data bits
D15
0
D14
1
D13
X
D12
X
D11
X
D10
X
D9
X
D8
0
D7
D6
D5
D4
D3
D2
SC
D1
RC
MC
Note:
X values are not relevant and can be set to 0 or 1.
7.4
RX Register Setting with Internal Clock Recovery
Recommended for 1.152-Mbit/s data rate.
The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal
samples the data signal.
MSB
Data bits
D24
1
D23
0
D22
1
D21
0
D20
0
D19
0
D18
0
D17
0
D16
0
LSB
D0
Data bits
D15
0
D14
0
D13
X
D12
X
D11
X
D10
X
D9
X
D8
0
D7
D6
D5
D4
D3
D2
SC
D1
RC
MC
Note:
X values are not relevant and can be set to 0 or 1.
7.5
PLL Settings
RC, MC and SC bits control the synthesizer frequency as shown in Table 7-3, Table 7-4 on page
12 and Table 7-5 on page 12.
Formula for calculating the frequency:
TX frequency: fANT = 864 kHz × (32 × SMC + SSC
)
RX frequency: fANT = 864 kHz × (32 × SMC + SSC – 1)
Table 7-3.
PLL Settings of the Reference Counter Bit D7
RC (Reference Counter)
D7
0
CLK Reference
10.368 MHz
1
13.824 MHz
11
4779N–ISM–12/08
Table 7-4.
PLL Settings of the Main Counter Bits D5 to D6
MC (Main Counter)
D6
0
D5
0
SMC
86
0
1
87
1
0
88
1
1
89
Table 7-5.
PLL Settings of the Swallow Counter Bits D0 to D4
SC (Swallow Counter)
D4
0
D3
0
D2
0
D1
0
D0
0
SSC
0
0
0
0
0
1
1
0
0
0
1
0
2
...
1
...
1
...
1
...
0
...
1
...
29
30
31
1
1
1
1
0
1
1
1
1
1
7.6
GFCS Adjustment
The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by
tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are
only relevant in TX mode.
Table 7-6.
GFCS Adjustment of Bits D9 - D11
GFCS
D11
D10
0
D9
0
GFCS
60%
0
0
0
0
1
1
1
1
0
1
70%
1
0
80%
1
1
90%
0
0
100%
110%
120%
130%
0
1
1
0
1
1
12
ATR2406
4779N–ISM–12/08
ATR2406
7.7
Control Signals
The various transceiver functions are activated by the following control signals. A timing pro-
posal is shown in Figure 7-3 on page 14
Table 7-7.
Control Signals and Functions
Signal
Functions
Activates AUX voltage regulator and the VCO voltage regulator supplying the
complete transceiver
PU_REG
PU_TRX
RX_ON
TX_ON
nOLE
Activates RX/TX blocks
Activates RX circuits: DEMOD, IF AMP, IR MIXER
Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT
Disables open loop mode of the PLL
7.8
Serial Programming Bus
The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE).
After setting the enable signal to low, the data is transferred bit by bit into the shift register on the
rising edge of the clock signal, starting with the MSBit. When the enable signal has returned to
high, the programmed information is active. Additional leading bits are ignored and there is no
check made of how many clock pulses arrived during enable low.
The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock
recovery mode).
7.9
3-wire Bus Timing
Figure 7-2. 3-wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TL
TC
TH
TPER
TEC
TT
TS
Table 7-8.
3-wire Bus Protocol Table
Description
Symbol
TPER
TS
Minimum Value
Unit
ns
Clock period
100
20
Set time data to clock
Hold time data to clock
Clock pulse width
ns
TH
20
ns
TC
60
ns
Set time enable to clock
Hold time enable to data
Time between two protocols
TL
100
0
ns
TEC
TT
ns
250
ns
13
4779N–ISM–12/08
Figure 7-3. Example TX and RX Timing Diagram
( O X R u t p u t ) f s r o m g T i n S a l
( I X n R p u t ) t s o T g i n S a l
14
ATR2406
4779N–ISM–12/08
ATR2406
Table 7-9.
Description of the Conditions/States
Description
Condition
Power down
C1
C2
ATR2406 is switched off and the supply current is lower than 1 µA.
Power up
ATR2406 is powered up by toggling PU_REG and PU_TRX to high.
PU_REG enables the external AUX regulator transistor including VCO regulator.
PU_TRX enables internal blocks like the PLL and the VCO.
Depending on the value of the external capacitors (for example, at the AUX
regulator, if one is used), it is necessary to wait at least 40 µs until the different
supply voltages have settled.
Programming
The internal register of the ATR2406 is programmed via the three-wire interface.
At TX, this is just the PLL (transmit channel) and the deviation (Gaussian filter).
At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also
the bits to enable this option. At the start of the three-wire programming, the
enable signal is toggled from high to low to enable clocking the data into the
internal register. When the enable signal rises again to high, the programmed
data is latched. This is the time point at which the settling of the PLL starts. It is
necessary to wait the settling time of 200 µs so that the VCO frequency is stable.
The reference clock needs to be applied to ATR2406 for at least the time when the
PLL is in operation, which is the programming state (C3) and the active slot (C4,
C5). Out of the reference clock, several internal signals are also derived, for
example, the Gaussian filter circuitry and TX_DATA sampling.
C3
This is the receive slot where the transmit burst is received and data as well as
recovered clock are available.
C4
C5
This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the
signal nOLE toggles to low which enables modulation in open-loop mode.
The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON.
7.10 Received Signal Strength Indication (RSSI)
The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is
shown in Figure 7-4.
Figure 7-4. Typical RSSI Value versus Input Power
2.5
2.0
1.5
1.0
0.5
0.0
-130
-110
-90
-70
-50
-30
-10
10
RF Level (dBm)
15
4779N–ISM–12/08
8. Application Circuit
The ATR2406 requires only a few low-cost external components for operation. A typical applica-
tion is shown in Figure 8-3 on page 17.
8.1
Typical Application Circuit
Figure 8-1. Microcontroller Interfacing with General Purpose MCU, Pin Connections between
Microcontroller and ATR2406
Microcontroller
ATR2406
TX_DATA
RX_DATA
RX-CLOCK
ENABLE
CLOCK
DATA
Ctrl_Lines
REF_CLK
XTAL(1)
XTAL_OUT
Figure 8-2. Example with AVR MCU
AVR_MCU
ATR2406
USART
RF_DATA
TXD
RXD
XCK
TX_DATA
RX_DATA
RX-CLOCK
R
GPIO
RF_CTRL
ENABLE
CLOCK
DATA
nOLE
TX_ON
RX_ON
PU_REG
PU_TRX
RSSI
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
13.824 MHz XTAL
REF_CLK
Note:
1. XTAL: for example, XRFBCC-NANL; 13.824 MHz, 10 ppm
Order at: Taitien Electronic, Taitien Specific No.: A009-x-B26-3, SMD
16
ATR2406
4779N–ISM–12/08
ATR2406
Figure 8-3. Application Circuit for ATR2406-DEV-BOARD
N C
R 1
J 2 4
1 p 8
C 3
2 p 2
1 k 5
R 6
C 7
2 p 2
C 6
p t r i µ S
G N
G N
G N
G N
G N
G N
G N
G N
T
V B A T
R A M
G N
p t r i µ S
U T O _ P
N O R X _
N C
1 k 0
R 4
4
C 1
3 9 0 p
C 4
N
_ O T X
n O L E
G N D
S Y N V S _
C P
G
N O _ T X
2 5
1 6
1 5
n O L E
R T X P U _
A T D R X _
2 6
2 7
2 8
X R T P U _
E N U V T
A
6 8 p
1 4
A
A T D R X _
C V O _
D E G _ R E
G E R V S _
V R E G
1 3
N C
C 1
A T A _ D T X
O C C K L
A T A _ D T X
8
9
C 1
4 7 0 n
C
2 9
3 0
3 1
3 2
1 2
7
1 1
O C C K L
A T D A
V R E G
1 0
R L C T G _ R E
C 1
E
A B L E N
A
D A T
E N A B L
9
E
6 2 k
R 3
E G R P U _
C _ L R E F
R S S I
4 n 7
C 2
1 8 p
4 p 7
3
K
1
C 1
4
C 2
J 2
S V
C K O L C R X -
17
4779N–ISM–12/08
9. PCB Layout Design
Figure 9-1. PCB Layout ATR2406-DEV-BOARD
18
ATR2406
4779N–ISM–12/08
ATR2406
Table 9-1.
Part
Bill of Materials
Part Number
Value
5.6 pF
1.8 pF
390 pF
4.7 pF
2.2 pF
1.5 pF
18 pF
100 nF
4.7 µF
1 nF
Vendor
Package
0402
Comment
C1
C3, C10
C4
0402
0402
C5
0402
NC
C6, C7
C9
0402
0402
C11
0402
C12, C15
C13, C16
C14
0402
B45196H2475M109
Epcos®
3216
Optional(2)
NC
0402
C17
3.3 nF
68 pF
470 nF
0402
NC
C18
0402
C19
0402/0603
COG, important for good
RF performance
C20
C21
22 nF, COG GRM21B5C1H223JA01
Murata
Murata
0805
0603
2.2 nF,
COG, important for good
RF performance
GRM1885C1H222JA01
COG
C23
C24
R3
4.7 nF
4.7 pF
0402
0402
0402
0402
0402
0402
MLF32
62 kΩ
1.0 kΩ
1.5 kΩ
1.5 kΩ
62k, ≤ 5%
1k0, ≤ 5%
1k5, ≤ 5%
1k5, ≤ 5%
R4
R5
Ref_Clk level, optional(1)
Ref_Clk level, optional(1)
R6
IC2
ATR2406 ATR2406
Atmel
BC808-40, any standard type can be used, but it is Vishay®,Philips®,
T1
BC808-40
SOT-23
Optional(2)
important that be “–40”!
etc.
MSUB
FR4
FR4, e_r = 4.4 at 2.45 GHz, H = 500 µm, T = 35 µm, tand = 0.02, surface, that is, chem. tin or chem. gold
Notes: 1. Not necessary if supplied RefClk level is within specification range
2. If no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad.
Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna, set jumper R2 (0R
resistor 0603)
Table 9-2.
Parts Count Bill of Materials
Parts Count
Required (Minimal BOM)
Optional (Depending on Application)
Capacitors 0402
14
2
14
4
Capacitors >0402
Resistors 0402
Inductors 0402
Semiconductors
2
2
–
–
1
2
19
4779N–ISM–12/08
10. Appendix: Current Calculations for a Remote Control
Assumptions:
A data packet consists of 24 bytes.
Protocol
24 bytes = 240 bits (USART connection)
Tpacket_length = 210 µs at 1.152 Mbits/s
The system will use five predefined channels for frequency hopping spread
spectrum (FHSS) which gives improved immunity against interferers
Channel
Loop filter
Loop filter settling time will be 110 µs
If not in use, the handheld device will be in power-down mode with the AVR’s
watchdog timer disabled. The AVR power-down current is typically 1.25 µA. If
an external voltage regulator is used, additional power-down current has to be
taken into account
Handheld device
The base station will periodically scan all the channels of the used subset. The
base station will stay on one channel for 2 seconds. If the base station receives
a correct packet, an acknowledge will be returned to the handheld device. The
power consumption of the base station device is not power-sensitive, as this
part of the application is normally mains powered
Base station device
Basic Numbers:
Peak current ATR2406 in TX at 1.152 Kbits/s
Peak current ATR2406 in RX at 1.152 Kbits/s
Peak current ATR2406 with synthesizer running
Current ATmega88 active
42 mA
57 mA
26 mA
5 mA
Current ATmega88 power down (no WDT)
Current ATmega88 power down (+ WDT)
Loop settling time of ATR2406
1.25 µA
5 µA
110 µs
30 µs
Configuration of ATR2406
Time needed for exchanging a packet at 1.152 Kbits/s
210 µs
Amount of Current Needed to Transmit One Packet:
Q1 = (0.005A + 0.026A) × 5030 µs = 155 µAs (charge up time ATR2406 + AVR internal calculations)
Q2 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406)
Q3 = (0.005A + 0.026A) × 110 µs = 3.41 µAs (charge for settling the loop filter)
Q4 = (0.005A + 0.042A) × 210 µs = 9.87 µAs (charge for transmitting the packet)
Q5 = (0.005A) × 250 µs = 1.25 µAs (charge for turn around (TX to RX, RX to TX, etc.))
Q6 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406)
Q7 = (0.005A + 0.026A) × 60 µs = 1.86 µAs (charge for settling the loop filter)
Q8 = (0.005A + 0.057A) × 50 µs = 3.10 µAs (charge until valid data can be received)
Q9 = (0.005A + 0.057A) × 210 µs = 13.02 µAs (charge for receiving the packet)
Q10 = (0.005A + 0.057A) × 50 µs = 3.1 µAs (charge for latency before receiving)
20
ATR2406
4779N–ISM–12/08
ATR2406
A successful packet exchange needs the following charge
Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47 µAs
As the described system is a FHSS system with 5 different channels, the system has to do this
up to five times before the packet is acknowledged by the base station. The average will be 2.5
times. In the case of an interfered environment, some more retries may be required; therefore, it
is assumed the factor will be 3. The power-up time is included only once, as the cycle will be
completed without powering up and down the handheld in order to be as power efficient as
possible.
Average current needed for a packet exchange:
155 µAs + (37.5 µAs × 3) = 267.5 µAs
If the device will be used 1000 times a day →3.1 µA
Average current in active mode:
→ System Power Down current:
Current ATmega88:
Current ATR2406:
1.25 µA
1.0 µA
Current VREG (+ ShutDown):
2.75 µA
Assumed average power-down current is 5 µA.
→Overall power consumption is 8.1 µA
It is assumed the system uses a small battery with a capacity of 100 mAh. This is 100.000 µAh.
→Battery lifetime will be around: 12345 hours = 514 days = 1.4 years.
The most important factor is to get the power-down current as low as possible!
Example:
Assume a system where the handheld is used just 10 times per day.
→Iactive = 0.031 µA
and assuming the power-down current of this device is just 4 µA.
→I = 0.031 µA + 4 µA = 4.03 µA
→Battery lifetime will be around 24807 hours = 1033 days = 2.83 years.
→Power-down current is the main factor influencing the battery lifetime.
21
4779N–ISM–12/08
11. Ordering Information
Extended Type Number
Package
QFN32 - 5x5
–
Remarks
MOQ
4000
1
ATR2406-PNQG
Taped and reeled, Pb-free
RF module
ATR2406-DEV-BOARD
Complete evaluation kit
and reference design
ATR2406 + ATmega88
ATR2406-DEV-KIT2
–
1
12. Package Information
Package: QFN 32 - 5 x 5
Exposed pad 3.7 x 3.7
Dimensions in mm
Not indicated tolerances ± 0.05
5
0.9±0.1
+0
3.7
0.05-0.05
25
32
32
1
24
17
1
8
technical drawings
according to DIN
specifications
5
16
9
0.5 nom.
3.5
Drawing-No.: 6.543-5096.01-4
Issue: 1; 22.01.03
22
ATR2406
4779N–ISM–12/08
ATR2406
13. Recommended Footprint/Landing Pattern
Figure 13-1. Recommenced Footprint/Landing Pattern
Table 13-1. Recommended Footprint/Landing Pattern Signs
Sign
A
Size
3.2 mm
1.2 mm
0.3 mm
1.1 mm
0.3 mm
0.2 mm
0.55 mm
0.5 mm
B
C
a
b
c
d
e
23
4779N–ISM–12/08
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
4779N-ISM-12/08
• Section 12 “Package Information” on page 22 changed
• Put datasheet in a new template
4779M-ISM-02/07
• Table 9-1 “Bill of Materials” on page 19 changed
• Table “Electrical Characteristics” on pages 6 to 8 changed
• Section 10 “Appendix: Current Calculations for a Remote Control” on
pages 20 to 21 changed
4779L-ISM-08/06
• Table “Ordering Information” on page 22 changed
• Minor corrections to grammar and style throughout document
• Put datasheet in a new template
• Table “Electrical Characteristics” on pages 6 to 8 changed
4779K-ISM-06/06
• Section 10 “Appendix: Current Calculations for a Remote Control” on
pages 20 to 21 added
• Ordering Information on page 22 changed
24
ATR2406
4779N–ISM–12/08
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4779N–ISM–12/08
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