ATMEGA64A_09 [ATMEL]
8-bit Microcontroller with 64K Bytes In-System Programmable Flash; 8位微控制器,带有64K字节的系统内可编程闪存型号: | ATMEGA64A_09 |
厂家: | ATMEL |
描述: | 8-bit Microcontroller with 64K Bytes In-System Programmable Flash |
文件: | 总21页 (文件大小:586K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 64K Bytes of In-System Reprogrammable Flash program memory
– 2K Bytes EEPROM
8-bit
– 4K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and
Capture Mode
ATmega64A
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain (1x, 10x, 200x)
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
Summary
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega64A
• Speed Grades
– 0 - 16 MHz for ATmega64A
8160CS–AVR–07/09
ATmega64A
1. Pin Configuration
Figure 1-1. Pinout ATmega64A
TQFP/MLF
PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
1
2
3
4
5
6
7
8
9
48 PA3 (AD3)
47 PA4 (AD4)
46 PA5 (AD5)
45 PA6 (AD6)
44 PA7 (AD7)
43 PG2(ALE)
42 PC7 (A15)
41 PC6 (A14)
40 PC5 (A13)
39 PC4 (A12)
38 PC3 (A11)
37 PC2 (A10
36 PC1 (A9)
35 PC0 (A8)
34 PG1(RD)
33 PG0(WR)
(ICP3/INT7) PE7
(SS) PB0 10
(SCK) PB1 11
(MOSI) PB2 12
(MISO) PB3 13
(OC0) PB4 14
(OC1A) PB5 15
(OC1B) PB6
16
Note:
The bottom pad under the QFN/MLF package should be soldered to ground.
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8160CS–AVR–07/09
ATmega64A
2. Overview
The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power con-
sumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
PF0 - PF7
PA0 - PA7
PC0 - PC7
VCC
GND
PORTA DRIVERS
PORTF DRIVERS
PORTC DRIVERS
AVCC
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
XTAL1
XTAL2
AREF
CALIB. OSC
INTERNAL
OSCILLATOR
ADC
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
JTAG TAP
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
RESET
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
PEN
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
2-WIRE SERIAL
INTERFACE
SPI
USART0
USART1
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG. DATA DIR.
PORTG
REG. PORTG
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PORTE DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega64A provides the following features: 64K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O
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8160CS–AVR–07/09
ATmega64A
lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Coun-
ters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an
8-channel, 10-bit ADC with optional differential input stage with programmable gain, program-
mable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and programming, and
six software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down
mode saves the register contents but freezes the Oscillator, disabling all other chip functions
until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer contin-
ues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer
and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption. In Extended Standby mode, both the main
Oscillator and the asynchronous timer continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot Program can use any interface to download the
Application Program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega64A is a powerful microcontroller that provides a highly-flexi-
ble and cost-effective solution to many embedded control applications.
The ATmega64A AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.
2.2
ATmega103 and ATmega64A Compatibility
The ATmega64A is a highly complex microcontroller where the number of I/O locations super-
sedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility
with the ATmega103, all I/O locations present in ATmega103 have the same location in
ATmega64A. Most additional I/O locations are added in an Extended I/O space starting from
0x60 to 0xFF (i.e., in the ATmega103 internal RAM space). These location can be reached by
using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions.
The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the
increased number of Interrupt Vectors might be a problem if the code uses absolute addresses.
To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the
internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed.
The ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103 on
current printed circuit boards. The application notes “Replacing ATmega103 by ATmega128”
and “Migration between ATmega64 and ATmega128” describes what the user should be aware
of replacing the ATmega103 by an ATmega128 or ATmega64.
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8160CS–AVR–07/09
ATmega64A
2.2.1
ATmega103 Compatibility Mode
By programming the M103C Fuse, the ATmega64A will be compatible with the ATmega103
regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new fea-
tures in ATmega64A are not available in this compatibility mode, these features are listed below:
• One USART instead of two, asynchronous mode only. Only the eight least significant bits of
the Baud Rate Register is available.
• One 16 bits Timer/Counter with two compare registers instead of two 16 bits Timer/Counters
with three compare registers.
• Two-wire serial interface is not supported.
• Port G serves alternate functions only (not a general I/O port).
• Port F serves as digital input only in addition to analog input to the ADC.
• Boot Loader capabilities is not supported.
• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
• The External Memory Interface can not release any Address pins for general I/O, neither
configure different wait states to different External Memory Address sections.
• Only EXTRF and PORF exist in the MCUCSR Register.
• No timed sequence is required for Watchdog Timeout change.
• Only low-level external interrupts can be used on four of the eight External Interrupt sources.
• Port C is output only.
• USART has no FIFO buffer, so Data OverRun comes earlier.
• The user must have set unused I/O bits to 0 in ATmega103 programs.
2.3
Pin Descriptions
2.3.1
VCC
Digital supply voltage.
2.3.2
2.3.3
GND
Ground.
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega64A as listed on page
75.
2.3.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
5
8160CS–AVR–07/09
ATmega64A
Port B also serves the functions of various special features of the ATmega64A as listed on page
76.
2.3.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega64A as listed on page 79. In
ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated
when a reset condition becomes active.
2.3.6
2.3.7
2.3.8
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega64A as listed on page
80.
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64A as listed on page
83.
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will
be activated even if a reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input port only.
6
8160CS–AVR–07/09
ATmega64A
2.3.9
Port G (PG4:PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the external
memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1,
PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock
is not running. PG3 and PG4 are Oscillator pins.
2.3.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 28-3 on page
330. Shorter pulses are not guaranteed to generate a reset.
2.3.11
2.3.12
2.3.13
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.14
2.3.15
AREF
PEN
AREF is the analog reference pin for the A/D Converter.
This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low
during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN is inter-
nally pulled high. The pullup is shown in Figure 10-1 on page 52 and its value is given in Section
28.2 “DC Characteristics” on page 327. PEN has no function during normal operation.
7
8160CS–AVR–07/09
ATmega64A
3. Resources
A comprehensive set of development tools, application notes and datasheetsare available for
download on http://www.atmel.com/avr.
Note:
1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
8
8160CS–AVR–07/09
ATmega64A
5. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
:
Reserved
Reserved
Reserved
UCSR1C
UDR1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
UMSEL1
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
198
196
196
197
200
200
USART1 I/O Data Register
UCSR1A
UCSR1B
UBRR1L
UBRR1H
Reserved
Reserved
UCSR0C
Reserved
Reserved
Reserved
Reserved
UBRR0H
Reserved
ADCSRB
Reserved
TCCR3C
TCCR3A
TCCR3B
TCNT3H
TCNT3L
OCR3AH
OCR3AL
OCR3BH
OCR3BL
OCR3CH
OCR3CL
ICR3H
RXC1
TXC1
UDRE1
UDRIE1
FE1
DOR1
UPE1
U2X1
MPCM1
TXB81
RXCIE1
TXCIE1
RXEN1
TXEN1
UCSZ12
RXB81
USART1 Baud Rate Register Low
– USART1 Baud Rate Register High
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
–
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
198
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x90)
(0x8F)
(0x8E)
–
–
–
–
USART0 Baud Rate Register High
200
251
–
–
–
–
–
–
–
–
ADTS2
–
–
ADTS1
–
–
ADTS0
–
–
–
–
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
–
–
–
–
–
FOC3A
COM3A1
ICNC3
FOC3B
COM3A0
ICES3
FOC3C
COM3B1
–
–
–
–
–
–
137
133
135
137
137
138
138
138
138
138
138
139
139
COM3B0
WGM33
COM3C1
WGM32
COM3C0
CS32
WGM31
CS31
WGM30
CS30
Timer/Counter3 – Counter Register High Byte
Timer/Counter3 – Counter Register Low Byte
Timer/Counter3 – Output Compare Register A High Byte
Timer/Counter3 – Output Compare Register A Low Byte
Timer/Counter3 – Output Compare Register B High Byte
Timer/Counter3 – Output Compare Register B Low Byte
Timer/Counter3 – Output Compare Register C High Byte
Timer/Counter3 – Output Compare Register C Low Byte
Timer/Counter3 – Input Capture Register High Byte
Timer/Counter3 – Input Capture Register Low Byte
ICR3L
Reserved
Reserved
ETIMSK
ETIFR
–
–
–
–
–
–
–
–
–
–
–
–
OCIE3A
OCF3A
–
–
OCIE3B
OCF3B
–
–
TOIE3
TOV3
–
–
OCIE3C
OCF3C
–
–
OCIE1C
OCF1C
–
(0x7D)
(0x7C)
(0x7B)
(0x7A)
–
–
TICIE3
ICF3
–
140
141
–
–
–
–
Reserved
TCCR1C
OCR1CH
OCR1CL
Reserved
Reserved
Reserved
TWCR
FOC1A
FOC1B
FOC1C
–
–
–
–
–
136
138
138
(0x79)
(0x78)
(0x77)
(0x76)
(0x75)
Timer/Counter1 – Output Compare Register C High Byte
Timer/Counter1 – Output Compare Register C Low Byte
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x74)
(0x73)
(0x72)
(0x71)
(0x70)
(0x6F)
(0x6E)
(0x6D)
(0x6C)
(0x6B)
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
226
228
229
228
226
44
TWDR
Two-wire Serial Interface Data Register
TWAR
TWA6
TWS7
TWA5
TWS6
TWA4
TWS5
TWA3
TWS4
TWA2
TWS3
TWA1
–
TWA0
TWGCE
TWPS0
TWSR
TWPS1
TWBR
Two-wire Serial Interface Bit Rate Register
Oscillator Calibration Register
OSCCAL
Reserved
XMCRA
XMCRB
Reserved
EICRA
–
–
–
–
SRL0
–
–
SRW01
–
–
SRW00
XMM2
–
–
SRW11
XMM1
–
–
–
SRL2
SRL1
30
32
XMBK
–
–
XMM0
–
–
–
–
–
–
(0x6A)
(0x69)
(0x68)
(0x67)
(0x66)
(0x65)
(0x64)
(0x63)
ISC31
ISC30
ISC21
ISC20
–
ISC11
–
ISC10
–
ISC01
–
ISC00
–
65
Reserved
SPMCSR
Reserved
Reserved
PORTG
DDRG
–
–
–
SPMIE
RWWSB
–
RWWSRE
–
BLBSET
–
PGWRT
–
PGERS
–
SPMEN
–
293
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTG4
DDG4
PING4
PORTF4
DDF4
PORTG3
DDG3
PING3
PORTF3
DDF3
PORTG2
DDG2
PING2
PORTF2
DDF2
PORTG1
DDG1
PING1
PORTF1
DDF1
PORTG0
DDG0
PING0
PORTF0
DDF0
91
91
91
90
90
–
–
–
–
–
–
PING
(0x62)
(0x61)
PORTF
PORTF7
DDF7
PORTF6
DDF6
PORTF5
DDF5
DDRF
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8160CS–AVR–07/09
ATmega64A
5. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x60)
Reserved
SREG
–
I
–
T
–
H
–
–
–
–
–
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
S
V
N
Z
C
10
13
13
44
SPH
SP15
SP7
SP14
SP6
SP13
SP5
XDIV5
–
SP12
SP4
SP11
SP3
SP10
SP2
SP9
SP8
SPL
SP1
SP0
XDIV
XDIVEN
–
XDIV6
–
XDIV4
–
XDIV3
–
XDIV2
–
XDIV1
–
XDIV0
–
Reserved
EICRB
EIMSK
EIFR
ISC71
INT7
INTF7
OCIE2
OCF2
SRE
JTD
ISC70
INT6
INTF6
TOIE2
TOV2
SRW10
–
ISC61
INT5
INTF5
TICIE1
ICF1
SE
ISC60
INT4
INTF4
OCIE1A
OCF1A
SM1
ISC51
INT3
ISC50
INT2
INTF
TOIE1
TOV1
SM2
BORF
CS02
ISC41
INT1
INTF1
OCIE0
OCF0
IVSEL
EXTRF
CS01
ISC40
INT0
INTF0
TOIE0
TOV0
IVCE
PORF
CS00
66
67
INTF3
OCIE1B
OCF1B
SM0
67
TIMSK
TIFR
109, 139, 160
109, 141, 160
30, 50, 64
57, 261
106
MCUCR
MCUCSR
TCCR0
TCNT0
OCR0
–
JTRF
COM00
WDRF
WGM01
FOC0
WGM00
COM01
Timer/Counter0 (8 Bit)
108
Timer/Counter0 Output Compare Register
108
ASSR
–
–
–
COM1B1
–
–
AS0
TCN0UB
COM1C0
CS12
OCR0UB
WGM11
CS11
TCR0UB
WGM10
CS10
108
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
COM1A1
ICNC1
COM1A0
ICES1
COM1B0
WGM13
COM1C1
WGM12
133
135
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
137
137
Timer/Counter1 – Output Compare Register A High Byte
Timer/Counter1 – Output Compare Register A Low Byte
Timer/Counter1 – Output Compare Register B High Byte
Timer/Counter1 – Output Compare Register B Low Byte
Timer/Counter1 – Input Capture Register High Byte
Timer/Counter1 – Input Capture Register Low Byte
138
138
138
138
139
ICR1L
139
TCCR2
TCNT2
OCR2
FOC2
WGM20
OCDR6
COM21
COM20
WGM21
CS22
CS21
CS20
157
Timer/Counter2 (8 Bit)
160
Timer/Counter2 Output Compare Register
160
IDRD/
OCDR7
0x22 (0x42)
OCDR
OCDR5
OCDR4
OCDR3
OCDR2
OCDR1
OCDR0
258
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
WDTCR
SFIOR
EEARH
EEARL
EEDR
–
TSM
–
–
–
–
–
–
–
WDCE
WDE
ACME
–
WDP2
PUD
WDP1
PSR0
WDP0
57
–
–
PSR321
91, 110, 145, 231
EEPROM Address Register High Byte
32
32
EEPROM Address Register Low Byte
EEPROM Data Register
33
EECR
–
–
–
–
EERIE
PORTA3
DDA3
EEMWE
PORTA2
DDA2
EEWE
PORTA1
DDA1
EERE
PORTA0
DDA0
33
PORTA
DDRA
PINA
PORTA7
DDA7
PORTA6
DDA6
PORTA5
DDA5
PORTA4
DDA4
88
89
PINA7
PORTB7
DDB7
PINA6
PORTB6
DDB6
PINA5
PORTB5
DDB5
PINA4
PORTB4
DDB4
PINA3
PINA2
PINA1
PINA0
89
PORTB
DDRB
PINB
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
89
89
PINB7
PORTC7
DDC7
PINB6
PORTC6
DDC6
PINB5
PORTC5
DDC5
PINB4
PORTC4
DDC4
PINB3
PINB2
PINB1
PINB0
89
PORTC
DDRC
PINC
PORTC3
DDC3
PORTC2
DDC2
PORTC1
DDC1
PORTC0
DDC0
89
89
PINC7
PORTD7
DDD7
PINC6
PORTD6
DDD6
PINC5
PORTD5
DDD5
PINC4
PORTD4
DDD4
PINC3
PORTD3
DDD3
PINC2
PINC1
PORTD1
DDD1
PINC0
PORTD0
DDD0
89
PORTD
DDRD
PIND
PORTD2
DDD2
90
90
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
90
SPDR
SPI Data Register
173
172
171
196
196
197
200
231
247
249
250
250
90
SPSR
SPIF
SPIE
WCOL
SPE
–
–
–
–
–
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
CPHA
SPR1
UDR0
USART0 I/O Data Register
UCSR0A
UCSR0B
UBRR0L
ACSR
RXC0
TXC0
UDRE0
UDRIE0
FE0
DOR0
UPE0
U2X0
MPCM0
TXB80
RXCIE0
TXCIE0
RXEN0
TXEN0
UCSZ02
RXB80
USART0 Baud Rate Register Low
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ACI
MUX4
ADIF
ACIE
MUX3
ADIE
ACIC
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
ADMUX
ADCSRA
ADCH
ADCL
ADLAR
ADATE
ADC Data Register High Byte
ADC Data Register Low byte
PORTE
DDRE
PINE
PORTE7
DDE7
PORTE6
DDE6
PORTE5
DDE5
PORTE4
DDE4
PORTE3
DDE3
PORTE2
DDE2
PORTE1
DDE1
PORTE0
DDE0
90
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
90
10
8160CS–AVR–07/09
ATmega64A
5. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x00 (0x20)
PINF
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
91
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
11
8160CS–AVR–07/09
ATmega64A
6. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ¨ (Rd x Rr) << 1
R1:R0 ¨ (Rd x Rr) << 1
R1:R0 ¨ (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
k
Direct Subroutine Call
Subroutine Return
PC ← k
4
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
k
k
12
8160CS–AVR–07/09
ATmega64A
6. Instruction Set Summary (Continued)
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
1/2
1/2
BRID
k
Branch if Interrupt Disabled
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0:6
Z,C,N,V
Rd(3:0)←Rd(7:4),Rd(7:4)←Rd(3:0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
H ← 1
H
13
8160CS–AVR–07/09
ATmega64A
6. Instruction Set Summary (Continued)
CLH
Clear Half Carry Flag in SREG
H ← 0
H
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
14
8160CS–AVR–07/09
ATmega64A
7. Ordering Information
Speed (MHz)
Power Supply
Ordering Code(2)
Package(1)
Operation Range
ATmega64A-AU
ATmega64A-MU
64A
Industrial
16
2.7 - 5.5
64M1
(-40°C to 85°C)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
15
8160CS–AVR–07/09
ATmega64A
8. Packaging Information
8.1
64A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.30
0.09
0.45
–
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
E1
B
14.10 Note 2
0.45
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64A
B
R
16
8160CS–AVR–07/09
ATmega64A
8.2
64M1
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
TOP VIEW
A
K
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
1
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
0.30
9.10
NOM
0.90
0.02
0.25
9.00
NOTE
SYMBOL
E2
Option B
Option C
A
Pin #1
Chamfer
(C 0.30)
A1
b
0.18
8.90
D
D2
E
5.20
5.40
9.00
5.60
9.10
K
Pin #1
Notch
(0.20 R)
8.90
e
b
E2
e
5.20
5.40
0.50 BSC
0.40
5.60
BOTTOM VIEW
L
0.35
0.45
1.55
K
1.25
1.40
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Note:
5/25/06
DRAWING NO. REV.
64M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
G
R
17
8160CS–AVR–07/09
ATmega64A
9. Errata
The revision letter in this section refers to the revision of the ATmega64A device.
9.1
ATmega64A, rev. D
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Stabilizing time needed when changing XDIV Register
• Stabilizing time needed when changing OSCCAL Register
• IDCODE masks data from TDI input
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous
Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).
3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
; clear global interrupt enable
; set new prescale value
; no operation
OUT XDIV, temp
NOP
NOP
NOP
NOP
NOP
NOP
; no operation
; no operation
; no operation
; no operation
; no operation
18
8160CS–AVR–07/09
ATmega64A
NOP
NOP
SEI
; no operation
; no operation
; clear global interrupt enable
4. Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-
ister, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega64A is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega64A by issuing the IDCODE instruction
or by entering the Test-Logic-Reset state of the TAP controller to read out the
contents of its Device ID Register and possibly data from succeeding devices of the
scan chain. Issue the BYPASS instruction to the ATmega64A while reading the
Device ID Registers of preceding devices of the boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega64A must be the first device in the chain.
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-
ister triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
19
8160CS–AVR–07/09
ATmega64A
10. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section refers to the document revision.
10.1 8160C – 07/09
10.2 8160B – 03/09
1.
Updated “Errata” on page 382.
1.
2.
3.
Updated “Typical Characteristics” view.
Updated Figure 29-36 and Figure 29-37 on page 361 (BOD Thresholds Characteristics).
Updated the last page.
10.3 8160A – 08/08
1.
2.
Initial revision (Based on the ATmega64/L datasheet 2490N-AVR-06/08).
Changes done compared to ATmega64/L datasheet 2490N-AVR-06/08:
– All Electrical Characteristics are moved to “Electrical Characteristics” on page 327.
– Register descriptions are moved to sub section at the end of each chapter.
– Updated “DC Characteristics” on page 327 with new VOL Max (0.9V and 0.6V) and
typical values for ICC
.
– Added “Speed Grades” on page 329.
– Added “System and Reset Characteristics” on page 330.
– New graphics in “Typical Characteristics” on page 343.
– New “Ordering Information” on page 15.
20
8160CS–AVR–07/09
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8160CS–AVR–07/09
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