ATMEGA64C1-15MZ [ATMEL]
Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQCC32,;
| 型号： | ATMEGA64C1-15MZ |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQCC32, 微控制器 |
| 文件： | 总27页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
8-bit
– 16K/32K/64K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
Microcontroller
with
16K/32K/64K
Bytes In-System
Programmable
Flash
– Optional Boot Code Section with Independent Lock Bits
– In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 512/1024/2048 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
• Programming Lock for Flash Program and EEPROM Data Security
• 1024/2048/4096 Bytes Internal SRAM
• On Chip Debug Interface (debugWIRE)
• CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified (1)
• LIN 2.1 and 1.3 Controller or 8-Bit UART
• One 12-bit High Speed PSC (Power Stage Controller) (only ATmega16/32/64M1)
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
Atmel
• Synchronous Update of all PWM Registers
• Auto Stop Function for Emergency Event
ATmega16M1
ATmega32M1
ATmega64M1
ATmega32C1
ATmega64C1
• Peripheral Features
– One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode
and Capture Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– One Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels
• Internal Reference Voltage
• Direct Power Supply Voltage Measurement
– 10-bit DAC for Variable Voltage Reference (Comparators, ADC)
– Four Analog Comparators with Variable Threshold Detection
– 100µA ±6% Current Source (LIN Node Identification)
– Interrupt and Wake-up on Pin Change
Automotive
Summary
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– On-chipTemperature Sensor
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– In-System Programmable via SPI Port
– High Precision Crystal Oscillator for CAN Operations (16MHz)
See certification on Atmel® web site.
7647ES–AVR–07/12
1.
– Internal Calibrated RC Oscillator (8MHz)
– On-chip PLL for fast PWM (32MHz, 64MHz) and CPU (16MHz) (only ATmega16/32/64M1)
• Operating Voltage:
– 2.7V - 5.5V
• Extended Operating Temperature:
– –40°C to +125°C
• Core Speed Grade:
– 0 - 8MHz at 2.7 - 4.5V
– 0 - 16MHz at 4.5 - 5.5V
Table 0-1.
ATmega32/64/M1/C1 Product Line-up
Part Number
Flash Size
ATmega32C1
ATmega64C1
ATmega16M1
16 Kbyte
1024 bytes
512 bytes
Yes
ATmega32M1
32 Kbyte
ATmega64M1
64 Kbyte
32 Kbyte
2048 bytes
1024 bytes
64 Kbyte
4096 bytes
2048 bytes
RAM Size
EEPROM Size
8-bit Timer
16-bit Timer
PSC
2048 bytes
1024 bytes
4096 bytes
2048 bytes
Yes
No
No
Yes
10
3
PWM Outputs
Fault Inputs (PSC)
PLL
4
0
4
0
10
3
10
3
Yes
11 single
3 Differential
10-bit ADC Channels
10-bit DAC
Analog Comparators
Current Source
CAN
Yes
4
Yes
Yes
Yes
Yes
Yes
LIN/UART
On-Chip Temp. Sensor
SPI Interface
2
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
1. Pin Configurations
Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package
(PCINT18/PSCIN2/OC1A/MISO_A) PD2
(PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3
(PCINT9/PSCIN1/OC1B/SS_A) PC1
VCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB4 (AMP0+/PCINT4)
PB3 (AMP0-/PCINT3)
PC6 (ADC10/ACMP1/PCINT14)
AREF(ISRC)
AGND
GND
AVCC
(PCINT10/T0/TXCAN) PC2
(PCINT11/T1/RXCAN/ICP1B) PC3
(PCINT0/MISO/PSCOUT2A) PB0
PC5 (ADC9/ACMP3/AMP1+/PCINT13)
PC4 (ADC8/ACMPN3/AMP1-/PCINT12)
Note:
On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not
located on PC4. It is located on PE2.
3
7647ES–AVR–07/12
Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package
(PCINT18/OC1A/MISO_A) PD2
(PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3
(PCINT9/OC1B/SS_A) PC1
VCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB4 (AMP0+/PCINT4)
PB3 (AMP0-/PCINT3)
PC6 (ADC10/ACMP1/PCINT14)
AREF(ISRC)
AGND
GND
AVCC
(PCINT10/T0/TXCAN) PC2
(PCINT11/T1/RXCAN/ICP1B) PC3
(PCINT0/MISO) PB0
PC5 (ADC9/ACMP3/AMP1+/PCINT13)
PC4 (ADC8/ACMPN3/AMP1-/PCINT12)
Note:
On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is
not located on PC4. It is located on PE2.
4
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
1.1
Pin Descriptions
:
Table 1-1.
Pin out description
QFN32 Pin
Number
Mnemonic
GND
Type
Name, Function and Alternate Function
Ground: 0V reference
5
20
4
Power
Power
Power
AGND
VCC
Analog Ground: 0V reference for analog part
Power Supply
Analog Power Supply: This is the power supply voltage for
analog part
19
21
AVCC
AREF
Power
Power
For a normal use this pin must be connected.
Analog Reference : reference for analog converter . This is
the reference voltage of the A/D converter. As output, can be
used by external analog
ISRC (Current Source Output)
MISO (SPI Master In Slave Out)
PSCOUT2A (PSC Module 2 Output A)
PCINT0 (Pin Change Interrupt 0)
8
9
PB0
PB1
I/O
I/O
MOSI (SPI Master Out Slave In)
PSCOUT2B (PSC Module 2 Output B)
PCINT1 (Pin Change Interrupt 1)
ADC5 (Analog Input Channel 5 )
INT1 (External Interrupt 1 Input)
16
PB2
I/O
ACMPN0 (Analog Comparator 0 Negative Input)
PCINT2 (Pin Change Interrupt 2)
AMP0- (Analog Differential Amplifier 0 Negative Input)
PCINT3 (Pin Change Interrupt 3)
23
24
PB3
PB4
I/O
I/O
AMP0+ (Analog Differential Amplifier 0 Positive Input)
PCINT4 (Pin Change Interrupt 4)
ADC6 (Analog Input Channel 6)
INT2 (External Interrupt 2 Input)
26
PB5
I/O
ACMPN1 (Analog Comparator 1 Negative Input)
AMP2- (Analog Differential Amplifier 2 Negative Input)
PCINT5 (Pin Change Interrupt 5)
ADC7 (Analog Input Channel 7)
PSCOUT1B (PSC Module 1 Output A)
PCINT6 (Pin Change Interrupt 6)
27
28
PB6
PB7
I/O
I/O
ADC4 (Analog Input Channel 4)
PSCOUT0B (PSC Module 0 Output B)
SCK (SPI Clock)
PCINT7 (Pin Change Interrupt 7)
Note:
1. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate func-
tion is not located on PC4. It is located on PE2.
5
7647ES–AVR–07/12
Table 1-1.
Pin out description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function and Alternate Function
PSCOUT1A (PSC Module 1 Output A)
INT3 (External Interrupt 3 Input)
PCINT8 (Pin Change Interrupt 8)
30
3
PC0
I/O
PSCIN1 (PSC Digital Input 1)
OC1B (Timer 1 Output Compare B)
SS_A (Alternate SPI Slave Select)
PCINT9 (Pin Change Interrupt 9)
PC1
PC2
PC3
I/O
I/O
I/O
T0 (Timer 0 clock input)
6
TXCAN (CAN Transmit Output)
PCINT10 (Pin Change Interrupt 10)
T1 (Timer 1 clock input)
RXCAN (CAN Receive Input)
7
ICP1B (Timer 1 input capture alternate B input)
PCINT11 (Pin Change Interrupt 11)
ADC8 (Analog Input Channel 8)
AMP1- (Analog Differential Amplifier 1 Negative Input)
ACMPN3 (Analog Comparator 3 Negative Input)
PCINT12 (Pin Change Interrupt 12)
17
PC4
I/O
ADC9 (Analog Input Channel 9)
AMP1+ (Analog Differential Amplifier 1 Positive Input)
ACMP3 (Analog Comparator 3 Positive Input)
PCINT13 (Pin Change Interrupt 13)
18
22
PC5
PC6
I/O
I/O
ADC10 (Analog Input Channel 10)
ACMP1 (Analog Comparator 1 Positive Input)
PCINT14 (Pin Change Interrupt 14)
D2A (DAC output)
25
29
32
PC7
PD0
PD1
I/O
I/O
I/O
AMP2+ (Analog Differential Amplifier 2 Positive Input)
PCINT15 (Pin Change Interrupt 15)
PSCOUT0A (PSC Module 0 Output A)
PCINT16 (Pin Change Interrupt 16)
PSCIN0 (PSC Digital Input 0)
CLKO (System Clock Output)
PCINT17 (Pin Change Interrupt 17)
OC1A (Timer 1 Output Compare A)
PSCIN2 (PSC Digital Input 2)
1
PD2
I/O
MISO_A (Programming & alternate SPI Master In Slave Out)
PCINT18 (Pin Change Interrupt 18)
Note:
1. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate func-
tion is not located on PC4. It is located on PE2.
6
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
Table 1-1.
Pin out description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function and Alternate Function
TXD (UART Tx data)
TXLIN (LIN Transmit Output)
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
2
PD3
I/O
MOSI_A (Programming & alternate Master Out SPI Slave In)
PCINT19 (Pin Change Interrupt 19)
ADC1 (Analog Input Channel 1)
RXD (UART Rx data)
RXLIN (LIN Receive Input)
12
PD4
I/O
ICP1A (Timer 1 input capture alternate A input)
SCK_A (Programming & alternate SPI Clock)
PCINT20 (Pin Change Interrupt 20)
ADC2 (Analog Input Channel 2)
13
14
PD5
PD6
I/O
I/O
ACMP2 (Analog Comparator 2 Positive Input)
PCINT21 (Pin Change Interrupt 21)
ADC3 (Analog Input Channel 3)
ACMPN2 (Analog Comparator 2 Negative Input)
INT0 (External Interrupt 0 Input)
PCINT22 (Pin Change Interrupt 22)
ACMP0 (Analog Comparator 0 Positive Input)
PCINT23 (Pin Change Interrupt 23)
15
31
PD7
PE0
I/O
RESET (Reset Input)
I/O or I
OCD (On Chip Debug I/O)
PCINT24 (Pin Change Interrupt 24)
XTAL1 (XTAL Input)
10
11
PE1
PE2
I/O
I/O
OC0B (Timer 0 Output Compare B)
PCINT25 (Pin Change Interrupt 25)
XTAL2 (XTAL Output)
ADC0 (Analog Input Channel 0)
PCINT26 (Pin Change Interrupt 26)
Note:
1. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate func-
tion is not located on PC4. It is located on PE2.
7
7647ES–AVR–07/12
2. Overview
The ATmega16/32/64/M1/C1 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega16/32/64/M1/C1 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
Data Bus 8-bit
Interrupt
Unit
Program
Counter
Status
and Control
Flash Program
Memory
SPI
Unit
32 x 8
General
Purpose
Registrers
Instruction
Register
Watchdog
Timer
4 Analog
Comparators
Instruction
Decoder
ALU
HW LIN/UART
Timer 0
Timer 1
ADC
Control Lines
Data
SRAM
EEPROM
DAC
MPSC
I/O Lines
CAN
Current Source
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
8
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
The ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512/1024/2048 bytes EEPROM,
1024/2048/4096 bytes SRAM, 27 general purpose I/O lines, 32 general purpose working regis-
ters, one Motor Power Stage Controller, two flexible Timer/Counters with compare modes and
PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with
programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual
Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power sav-
ing modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN,
LIN/UART and interrupt system to continue functioning. The Power-down mode saves the regis-
ter contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except
ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Reso-
nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI
serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The boot program can use any interface to download the
application program in the application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega16/32/64/M1/C1 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega16/32/64/M1/C1 AVR is supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2
Automotive Quality Grade
The ATmega16/32/64/M1/C1 have been developed and manufactured according to the most
stringent requirements of the international standard ISO-TS-16949. This data sheet contains
limit values extracted from the results of extensive characterization (Temperature and Voltage).
The quality and reliability of the ATmega16/32/64/M1/C1 have been verified during regular prod-
uct qualification as per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, the products are available in only one tem-
perature grade.
Table 2-1.
Temperature
-40°C; +125°C
Temperature Grade Identification for Automotive Products
Temperature Identifier
Comments
Full Automotive Temperature Range
Z
9
7647ES–AVR–07/12
2.3
Pin Descriptions
2.3.1
VCC
Digital supply voltage.
2.3.2
2.3.3
GND
Ground.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16/32/64/M1/C1.
2.3.4
2.3.5
2.3.6
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega16/32/64/M1/C1.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16/32/64/M1/C1.
Port E (PE2..0) RESET/ XTAL1/ XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-
acteristics of PE0 differ from those of the other pins of Port E.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
10
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
2.3.7
AVCC
AREF
AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should
be externally connected to VCC, even if the ADC, DAC are not used. If the ADC is used, it should
be connected to VCC through a low-pass filter.
2.3.8
This is the analog reference pin for the A/D Converter.
2.4
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
11
7647ES–AVR–07/12
3. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ←Rd + Rr
Rd ←Rd + Rr + C
Rdh:Rdl ←Rdh:Rdl + K
Rd ←Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADIW
SUB
SUBI
SBC
Rd ←Rd - K
Rd ←Rd - Rr - C
Rd ←Rd - K - C
Rdh:Rdl ←Rdh:Rdl - K
Rd ←Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ←Rd • K
Z,N,V
Rd ←Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ←Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ←Rd Rr
Z,N,V
Rd ←0xFF - Rd
Rd ←0x00 - Rd
Rd ←Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ←Rd · (0xFF - K)
Rd ←Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ←Rd - 1
Z,N,V
TST
Rd
Test for Zero or Minus
Rd ←Rd • Rd
Z,N,V
CLR
Rd
Clear Register
Rd ←Rd Rd
Z,N,V
SER
Rd
Set Register
Rd ←0xFF
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ←Rd x Rr
R1:R0 ←Rd x Rr
R1:R0 ←Rd x Rr
R1:R0 ←(Rd x Rr) << 1
R1:R0 ←(Rd x Rr) << 1
R1:R0 ←(Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
Indirect Jump to (Z)
PC ←PC + k + 1
PC ←Z
None
None
None
None
None
None
None
I
2
2
JMP(*)
RCALL
ICALL
CALL(*)
RET
k
k
Direct Jump
PC ←k
3
Relative Subroutine Call
Indirect Call to (Z)
PC ←PC + k + 1
3
PC ←Z
3
k
Direct Subroutine Call
Subroutine Return
PC ←k
4
PC ←STACK
4
RETI
Interrupt Return
PC ←STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ←PC + 2 or 3
Rd - Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ←PC + 2 or 3
if (Rr(b)=1) PC ←PC + 2 or 3
if (P(b)=0) PC ←PC + 2 or 3
if (P(b)=1) PC ←PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ←PC + k + 1
if (Z = 0) then PC ←PC + k + 1
if (C = 1) then PC ←PC + k + 1
if (C = 0) then PC ←PC + k + 1
if (C = 0) then PC ←PC + k + 1
if (C = 1) then PC ←PC + k + 1
if (N = 1) then PC ←PC + k + 1
if (N = 0) then PC ←PC + k + 1
if (N V= 0) then PC ←PC + k + 1
if (N V= 1) then PC ←PC + k + 1
if (H = 1) then PC ←PC + k + 1
if (H = 0) then PC ←PC + k + 1
if (T = 1) then PC ←PC + k + 1
if (T = 0) then PC ←PC + k + 1
if (V = 1) then PC ←PC + k + 1
if (V = 0) then PC ←PC + k + 1
if ( I = 1) then PC ←PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
k
k
k
12
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ←PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ←1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O(P,b) ←0
None
LSL
Rd(n+1) ←Rd(n), Rd(0) ←0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ←Rd(n+1), Rd(7) ←0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ←Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ←1
SREG(s) ←0
T ←Rr(b)
Rd(b) ←T
C ←1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ←0
Set Negative Flag
N ←1
Clear Negative Flag
Set Zero Flag
N ←0
Z ←1
Clear Zero Flag
Z ←0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ←1
I
CLI
I ←0
I
SES
CLS
SEV
CLV
SET
CLT
S ←1
S
S ←0
S
V ←1
V
V ←0
V
T ←1
T
Clear T in SREG
T ←0
T
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ←1
H ←0
H
H
1
1
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ←Rr
Rd+1:Rd ←Rr+1:Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Load Immediate
Rd ←K
Rd ←(X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ←(X), X ←X + 1
X ←X - 1, Rd ←(X)
Rd ←(Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ←(Y), Y ←Y + 1
Y ←Y - 1, Rd ←(Y)
Rd ←(Y + q)
Rd ←(Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ←(Z), Z ←Z+1
Z ←Z - 1, Rd ←(Z)
Rd ←(Z + q)
Rd ←(k)
LD
LDD
LDS
ST
X, Rr
(X) ←Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ←Rr, X ←X + 1
X ←X - 1, (X) ←Rr
(Y) ←Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ←Rr, Y ←Y + 1
Y ←Y - 1, (Y) ←Rr
(Y + q) ←Rr
ST
STD
ST
(Z) ←Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ←Rr, Z ←Z + 1
Z ←Z - 1, (Z) ←Rr
(Z + q) ←Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ←Rr
R0 ←(Z)
Rd, Z
Rd ←(Z)
Rd, Z+
Rd ←(Z), Z ←Z+1
(Z) ←R1:R0
Rd, P
P, Rr
Rr
Rd ←P
1
1
2
2
OUT
PUSH
POP
Out Port
P ←Rr
Push Register on Stack
Pop Register from Stack
STACK ←Rr
Rd ←STACK
Rd
13
7647ES–AVR–07/12
Mnemonics
Operands
Description
Operation
Flags
#Clocks
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
1
1
SLEEP
(see specific descr. for Sleep function)
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
Note:
1. These Instructions are only available in “16K and 32K parts”
14
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
Reserved
Reserved
Reserved
Reserved
Reserved
CANMSG
CANSTMPH
CANSTMPL
CANIDM1
CANIDM2
CANIDM3
CANIDM4
CANIDT1
CANIDT2
CANIDT3
CANIDT4
CANCDMOB
CANSTMOB
CANPAGE
CANHPMOB
CANREC
CANTEC
CANTTCH
CANTTCL
CANTIMH
CANTIML
CANTCON
CANBT3
CANBT2
CANBT1
CANSIT1
CANSIT2
CANIE1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MSG 7
TIMSTM15
TIMSTM7
IDMSK28
IDMSK20
IDMSK12
MSG 6
TIMSTM14
TIMSTM6
IDMSK27
IDMSK19
IDMSK11
MSG 5
TIMSTM13
TIMSTM5
IDMSK26
IDMSK18
IDMSK10
MSG 4
TIMSTM12
TIMSTM4
IDMSK25
IDMSK17
MSG 3
TIMSTM11
TIMSTM3
IDMSK24
IDMSK16
MSG 2
TIMSTM10
TIMSTM2
IDMSK23
IDMSK15
MSG 1
TIMSTM9
TIMSTM1
IDMSK22
IDMSK14
MSG 0
TIMSTM8
TIMSTM0
IDMSK21
IDMSK13
IDMSK
9
1
IDMSK
8
0
IDMSK
7
IDMSK
6
IDMSK5
IDMSK
4
IDMSK
3
IDMSK
2
IDMSK
IDMSK
RTRMSK
IDT23
–
IDEMSK
IDT21
IDT28
IDT20
IDT12
IDT27
IDT19
IDT11
IDT26
IDT18
IDT10
IDT25
IDT17
IDT24
IDT16
IDT22
IDT14
IDT15
IDT13
IDT
9
1
IDT
8
0
IDT
7
IDT
6
IDT5
IDT
4
IDT
3
IDT
2
IDT
IDT
RTRTAG
DLC2
CERR
INDX2
CGP2
REC2
TEC2
TIMTTC10
TIMTTC2
CANTIM10
CANTIM2
TPRSC2
PHS11
PRS1
BRP1
–
RB1TAG
DLC1
FERR
INDX1
CGP1
REC1
TEC1
TIMTTC9
TIMTTC1
CANTIM9
CANTIM1
TRPSC1
PHS10
PRS0
BRP0
–
RB0TAG
DLC0
AERR
INDX0
CGP0
REC0
TEC0
TIMTTC8
TIMTTC0
CANTIM8
CANTIM0
TPRSC0
SMP
–
CONMOB1
CONMOB0
RPLV
IDE
DLC3
SERR
AINC
CGP3
REC3
TEC3
TIMTTC11
TIMTTC3
CANTIM11
CANTIM3
TPRSC3
PHS12
PRS2
BRP2
–
DLCW
TXOK
RXOK
BERR
MOBNB3
MOBNB2
MOBNB1
MOBNB0
HPMOB3
HPMOB2
HPMOB1
HPMOB0
REC7
REC6
REC5
REC4
TEC7
TEC6
TEC5
TEC4
TIMTTC15
TIMTTC14
TIMTTC13
TIMTTC12
TIMTTC7
TIMTTC6
TIMTTC5
TIMTTC4
CANTIM15
CANTIM14
CANTIM13
CANTIM12
CANTIM7
CANTIM6
CANTIM5
CANTIM4
TPRSC7
TPRSC6
TPRSC5
TPRSC4
–
PHS22
PHS21
PHS20
–
SJW1
SJW0
–
–
BRP5
BRP4
BRP3
–
–
–
–
–
–
–
–
SIT5
SIT4
SIT3
SIT2
SIT1
SIT0
–
–
–
–
–
–
–
–
CANIE2
–
–
IEMOB5
IEMOB4
IEMOB3
–
IEMOB2
–
IEMOB1
–
IEMOB0
–
CANEN1
CANEN2
CANGIE
–
–
–
–
–
–
ENMOB5
ENMOB4
ENMOB3
ENERR
SERG
RXBSY
LISTEN
–
ENMOB2
ENBX
CERG
ENFG
TEST
–
ENMOB1
ENERG
FERG
BOFF
ENA/STB
–
ENMOB0
ENOVRT
AERG
ERRP
SWRES
–
ENIT
ENBOFF
ENRX
ENTX
CANGIT
CANIT
BOFFIT
OVRTIM
BXOK
CANGSTA
CANGCON
Reserved
Reserved
Reserved
Reserved
Reserved
LINDAT
–
OVRG
–
TXBSY
ABRQ
OVRQ
TTC
SYNTTC
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
/LAINC
LID3
LDATA2
LINDX2
LID2
LDATA1
LINDX1
LID1
LDATA0
LINDX0
LID0
LRXDL0
LDIV8
LDIV0
LBT0
LBERR
LENRXOK
LRXOK
LCMD0
–
LINSEL
–
–
–
–
LINIDR
LP1
LP0
LID5 / LDL1
LID4 / LDL0
LINDLR
LTXDL3
LTXDL2
LTXDL1
LTXDL0
LRXDL3
LDIV11
LDIV3
LBT3
LSERR
LENERR
LERR
LENA
–
LRXDL2
LDIV10
LDIV2
LBT2
LPERR
LENIDOK
LIDOK
LCMD2
–
LRXDL1
LDIV9
LDIV1
LBT1
LCERR
LENTXOK
LTXOK
LCMD1
–
LINBRRH
LINBRRL
LINBTR
–
–
–
–
LDIV7
LDIV6
LDIV5
LDIV4
LDISR
–
LBT5
LBT4
LINERR
LABORT
LTOERR
LOVERR
LFERR
LINENIR
–
–
–
–
LINSIR
LIDST2
LIDST1
LIDST0
LBUSY
LINCR
LSWRES
LIN13
LCONF1
LCONF0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15
7647ES–AVR–07/12
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xBE)
(0xBD)
(0xBC)(5)
(0xBB)(5)
(0xBA)(5)
(0xB9)(5)
(0xB8)(5)
(0xB7)(5)
(0xB6)(5)
(0xB5)(5)
(0xB4)(5)
(0xB3)(5)
(0xB2)(5)
(0xB1)(5)
(0xB0)(5)
(0xAF)(5)
(0xAE)(5)
(0xAD)(5)
(0xAC)(5)
(0xAB)(5)
(0xAA)(5)
(0xA9)(5)
(0xA8)(5)
(0xA7)(5)
(0xA6)(5)
(0xA5)(5)
(0xA4)(5)
(0xA3)(5)
(0xA2)(5)
(0xA1)(5)
(0xA0)(5)
(0x9F)
Reserved
Reserved
PIFR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PEV2
PEV1
PEV0
PEOP
PIM
–
–
–
–
PEVE2
PAOC2
PAOC1
PAOC0
–
PEVE1
PRFM22
PRFM12
PRFM02
–
PEVE0
PRFM21
PRFM11
PRFM01
PCCYC
POEN0B
–
PEOPE
PRFM20
PRFM10
PRFM00
PRUN
PMIC2
POVEN2
PISEL2
PELEV2
PFLTE2
PMIC1
POVEN1
PISEL1
PELEV1
PFLTE1
PMIC0
POVEN0
PISEL0
PELEV0
PFLTE0
PCTL
PPRE1
PPRE0
PCLKSEL
–
POC
–
–
POEN2B
POEN2A
POEN1B
POPB
POEN1A
POPA
POEN0A
–
PCNF
–
–
PULOCK
PMODE
PSYNC
–
–
PSYNC21
PSYNC20
PSYNC11
POCR_RB11
POCR_RB3
POCR2SB11
POCR2SB3
POCR2RA11
POCR2RA3
POCR2SA11
POCR2SA3
POCR1SB11
POCR1SB3
POCR1RA11
POCR1RA3
POCR1SA11
POCR1SA3
POCR0SB11
POCR0SB3
POCR0RA11
POCR0RA3
POCR0SA11
POCR0SA3
–
PSYNC10
POCR_RB10
POCR_RB2
POCR2SB10
POCR2SB2
POCR2RA10
POCR2RA2
POCR2SA10
POCR2SA2
POCR1SB10
POCR1SB2
POCR1RA10
POCR1RA2
POCR1SA10
POCR1SA2
POCR0SB10
POCR0SB2
POCR0RA10
POCR0RA2
POCR0SA10
POCR0SA2
–
PSYNC01
POCR_RB9
POCR_RB1
POCR2SB9
POCR2SB1
POCR2RA9
POCR2RA1
POCR2SA9
POCR2SA1
POCR1SB9
POCR1SB1
POCR1RA9
POCR1RA1
POCR1SA9
POCR1SA1
POCR0SB9
POCR0SB1
POCR0RA9
POCR0RA1
POCR0SA9
POCR0SA1
–
PSYNC00
POCR_RB8
POCR_RB0
POCR2SB8
POCR2SB0
POCR2RA8
POCR2RA0
POCR2SA8
POCR2SA0
POCR1SB8
POCR1SB0
POCR1RA8
POCR1RA0
POCR1SA8
POCR1SA0
POCR0SB8
POCR0SB0
POCR0RA8
POCR0RA0
POCR0SA8
POCR0SA0
–
POCR_RBH
POCR_RBL
POCR2SBH
POCR2SBL
POCR2RAH
POCR2RAL
POCR2SAH
POCR2SAL
POCR1SBH
POCR1SBL
POCR1RAH
POCR1RAL
POCR1SAH
POCR1SAL
POCR0SBH
POCR0SBL
POCR0RAH
POCR0RAL
POCR0SAH
POCR0SAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AC3CON
AC2CON
AC1CON
AC0CON
Reserved
DACH
–
–
–
–
POCR_RB7
POCR_RB6
POCR_RB5
POCR_RB4
–
–
–
–
POCR2SB7
POCR2SB6
POCR2SB5
POCR2SB4
–
–
–
–
POCR2RA7
POCR2RA6
POCR2RA5
POCR2RA4
–
–
–
–
POCR2SA7
POCR2SA6
POCR2SA5
POCR2SA4
–
–
–
–
POCR1SB7
POCR1SB6
POCR1SB5
POCR1SB4
–
–
–
–
POCR1RA7
POCR1RA6
POCR1RA5
POCR1RA4
–
–
–
–
POCR1SA7
POCR1SA6
POCR1SA5
POCR1SA4
–
–
–
–
POCR0SB7
POCR0SB6
POCR0SB5
POCR0SB4
–
–
–
–
POCR0RA7
POCR0RA6
POCR0RA5
POCR0RA4
–
–
–
–
POCR0SA7
POCR0SA6
POCR0SA5
POCR0SA4
–
–
–
–
(0x9E)
–
–
–
–
–
–
–
–
(0x9D)
–
–
–
–
–
–
–
–
–
–
(0x9C)
–
–
–
–
–
–
–
(0x9B)
–
–
–
–
–
–
–
–
(0x9A)
–
–
–
–
–
–
–
(0x99)
–
–
–
–
–
–
–
–
(0x98)
–
–
–
–
–
–
–
–
(0x97)
AC3EN
AC2EN
AC1EN
AC0EN
–
AC3IE
AC2IE
AC1IE
AC0IE
–
AC3IS1
AC2IS1
AC1IS1
AC0IS1
–
AC3IS0
AC2IS0
AC1IS0
AC0IS0
–
–
AC3M2
AC2M2
AC1M2
AC0M2
–
AC3M1
AC2M1
AC1M1
AC0M1
–
AC3M0
AC2M0
AC1M0
AC0M0
–
(0x96)
–
(0x95)
AC1ICE
ACCKSEL
–
(0x94)
(0x93)
(0x92)
- / DAC9
DAC7 / DAC1
DAATE
–
- / DAC8
DAC6 /DAC0
DATS2
–
- / DAC7
DAC5 / -
DATS1
–
- / DAC6
DAC4 / -
DATS0
–
- / DAC5
DAC3 / -
–
- / DAC4
DAC2 / -
DALA
DAC9 / DAC3
DAC1 / -
DAOE
DAC8 / DAC2
DAC0 /
DAEN
(0x91)
DACL
(0x90)
DACON
(0x8F)
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
–
–
–
–
(0x8E)
–
–
–
–
–
–
–
–
(0x8D)
–
–
–
–
–
–
–
–
(0x8C)
–
–
–
–
–
–
–
–
(0x8B)
OCR1B15
OCR1B7
OCR1A15
OCR1A7
ICR115
ICR17
TCNT115
TCNT17
–
OCR1B14
OCR1B6
OCR1A14
OCR1A6
ICR114
ICR16
TCNT114
TCNT16
–
OCR1B13
OCR1B5
OCR1A13
OCR1A5
ICR113
ICR15
TCNT113
TCNT15
–
OCR1B12
OCR1B4
OCR1A12
OCR1A4
ICR112
ICR14
TCNT112
TCNT14
–
OCR1B11
OCR1B3
OCR1A11
OCR1A3
ICR111
ICR13
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
ICR12
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
ICR1L
ICR11
ICR10
(0x85)
TCNT1H
TCNT111
TCNT13
–
TCNT110
TCNT12
–
TCNT19
TCNT11
–
TCNT18
TCNT10
–
(0x84)
TCNT1L
(0x83)
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
(0x82)
FOC1A
ICNC1
COM1A1
–
FOC1B
ICES1
COM1A0
AMP2PD
ADC6D
–
–
–
–
–
–
–
(0x81)
–
WGM13
COM1B0
AMP0PD
ADC4D
–
WGM12
–
CS12
CS11
CS10
(0x80)
COM1B1
ACMP0D
ADC5D
–
–
WGM11
ADC9D
ADC1D
–
WGM10
ADC8D
ADC0D
–
(0x7F)
AMP0ND
ADC3D
–
ADC10D
ADC2D
–
(0x7E)
DIDR0
ADC7D
–
(0x7D)
Reserved
16
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0x7C)
(0x7B)
ADMUX
ADCSRB
ADCSRA
ADCH
REFS1
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
ADHSM
ISRCEN
AREFEN
–
ADTS3
ADTS2
ADTS1
ADTS0
(0x7A)
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
- / ADC9
- / ADC8
- / ADC7
- / ADC6
- / ADC5
- / ADC4
ADC9 / ADC3
ADC8 / ADC2
(0x78)
ADCL
ADC7 / ADC1
ADC6 / ADC0
ADC5 / -
ADC4 / -
ADC3 / -
ADC2 / -
ADC1 / -
ADC0 /
(0x77)
AMP2CSR
AMP1CSR
AMP0CSR
Reserved
Reserved
Reserved
Reserved
Reserved
TIMSK1
TIMSK0
PCMSK3
PCMSK2
PCMSK1
PCMSK0
EICRA
AMP2EN
AMP2IS
AMP2G1
AMP2G0
AMPCMP2
AMP2TS2
AMP2TS1
AMP2TS0
(0x76)
AMP1EN
AMP1IS
AMP1G1
AMP1G0
AMPCMP1
AMP1TS2
AMP1TS1
AMP1TS0
(0x75)
AMP0EN
AMP0IS
AMP0G1
AMP0G0
AMPCMP0
AMP0TS2
AMP0TS1
AMP0TS0
(0x74)
–
–
–
–
–
–
–
–
(0x73)
–
–
–
–
–
–
–
–
(0x72)
–
–
–
–
–
–
–
–
(0x71)
–
–
–
–
–
–
–
–
–
–
(0x70)
–
–
–
–
–
–
(0x6F)
–
–
ICIE1
–
–
OCIE1B
OCIE1A
OCIE0A
PCINT25
PCINT17
PCINT9
PCINT1
ISC01
PCIE1
–
TOIE1
TOIE0
PCINT24
PCINT16
PCINT8
PCINT0
ISC00
PCIE0
–
(0x6E)
–
–
–
–
–
OCIE0B
(0x6D)
–
–
–
–
–
PCINT26
(0x6C)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
(0x6B)
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
(0x6A)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
(0x69)
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
(0x68)
PCICR
–
–
–
–
PCIE3
PCIE2
(0x67)
Reserved
OSCCAL
Reserved
PRR
–
–
–
–
–
–
(0x66)
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
–
CAL0
–
(0x65)
–
–
–
–
–
–
(0x64)
–
PRCAN
PRPSC
PRTIM1
PRTIM0
PRSPI
PRLIN
–
PRADC
–
(0x63)
Reserved
Reserved
CLKPR
–
–
–
–
–
–
(0x62)
–
–
–
–
–
–
–
–
(0x61)
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
WDP1
Z
CLKPS0
WDP0
C
(0x60)
WDTCSR
SREG
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
I
T
H
S
V
N
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP0
–
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BLBSET
–
–
PGWRT
–
–
–
SPMIE
RWWSB
SIGRD
RWWSRE
PGERS
–
SPMEN
–
–
–
–
–
–
–
–
–
–
–
PUD
–
SPIPS
–
–
IVSEL
EXTRF
SM0
IVCE
PORF
SE
–
–
WDRF
SM2
BORF
SM1
–
MSMCR
MONDR
ACSR
Monitor Stop Mode Control Register
Monitor Data Register
AC3IF
AC2IF
–
AC1IF
AC0IF
AC3O
–
AC2O
–
AC1O
–
AC0O
–
Reserved
SPDR
–
SPD7
SPIF
SPIE
–
–
–
SPD6
WCOL
SPE
SPD5
SPD4
SPD3
–
SPD2
–
SPD1
–
SPD0
SPSR
–
–
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
–
CPHA
–
SPR1
–
Reserved
Reserved
PLLCSR
OCR0B
OCR0A
TCNT0
–
–
–
–
–
–
–
–
–
–
–
–
-
-
-
-
-
PLLF
OCR0B2
OCR0A2
TCNT02
CS02
–
PLLE
OCR0B1
OCR0A1
TCNT01
CS01
WGM01
–
PLOCK
OCR0B0
OCR0A0
TCNT00
CS00
OCR0B7
OCR0A7
TCNT07
FOC0A
COM0A1
TSM
–
OCR0B6
OCR0A6
TCNT06
FOC0B
COM0A0
ICPSEL1
–
OCR0B5
OCR0B4
OCR0B3
OCR0A3
TCNT03
WGM02
–
OCR0A5
OCR0A4
TCNT05
TCNT04
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
–
–
COM0B1
COM0B0
WGM00
PSRSYNC
EEAR8
EEAR0
EEDR0
EERE
GPIOR00
INT0
–
–
–
–
–
–
–
–
EEAR9
EEAR1
EEDR1
EEWE
GPIOR01
INT1
EEAR7
EEDR7
–
EEAR6
EEDR6
–
EEAR5
EEAR4
EEAR3
EEDR3
EERIE
GPIOR03
INT3
INTF3
EEAR2
EEDR2
EEMWE
GPIOR02
INT2
INTF2
EEDR
EEDR5
EEDR4
EECR
–
–
GPIOR0
EIMSK
GPIOR07
–
GPIOR06
–
GPIOR05
GPIOR04
–
–
–
–
EIFR
–
–
INTF1
INTF0
17
7647ES–AVR–07/12
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
PCIFR
GPIOR2
GPIOR1
Reserved
Reserved
TIFR1
–
–
–
–
PCIF3
PCIF2
GPIOR22
GPIOR12
–
PCIF1
GPIOR21
GPIOR11
–
PCIF0
GPIOR20
GPIOR10
–
GPIOR27
GPIOR26
GPIOR25
GPIOR24
GPIOR23
GPIOR17
GPIOR16
GPIOR15
GPIOR14
GPIOR13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ICF1
–
–
OCF1B
OCF0B
–
OCF1A
OCF0A
–
TOV1
TOV0
–
TIFR0
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTE2
DDE2
PINE2
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
–
PORTE1
DDE1
PINE1
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
–
PORTE0
DDE0
PINE0
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
–
–
–
–
–
–
PINE
–
–
–
–
–
PORTD
DDRD
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
–
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
–
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
–
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
–
PORTD3
DDD3
PIND3
PORTC3
DDC3
PINC3
PORTB3
DDB3
PINB3
–
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are
reserved.
18
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
5. Errata
5.1
Errata Summary
5.1.1
ATmega16M1/16C1/32M1/32C1 Rev. C (Mask Revision)
• LIN Break Delimiter
• ADC with with PSC2-synchronized
• ADC amplifier measurement is unstable
5.1.2
ATmega16M1/16C1/32M1/32C1 Rev. B (Mask Revision)
• The AMPCMPx bits return 0
• No comparison when amplifier is used as comparator input and ADC input
• CRC calculation of diagnostic frames in LIN 2.x.
• Wrong TSOFFSET manufacturing calibration value
• PD0-PD3 set to outputs and PD4 pulled down following power-on with external reset active.
• LIN Break Delimiter
• ADC with with PSC2-synchronized
• ADC amplifier measurement is unstable
• PSC Emulation
• Read / Write instructions of MUXn and REFS1:0
5.1.3
ATmega16M1/16C1/32M1/32C1 Rev. A (Mask Revision)
• Inopportune reset of the CANIDM registers
• The AMPCMPx bits return 0
• No comparison when amplifier is used as comparator input and ADC input
• CRC calculation of diagnostic frames in LIN 2.x
• PD0-PD3 set to outputs and PD4 pulled down following power-on with external reset active
• LIN Break Delimiter
• ADC with with PSC2-synchronized
• ADC amplifier measurement is unstable
• PSC Emulation
• Read / Write instructions of MUXn and REFS1:0
19
7647ES–AVR–07/12
5.1.4
Errata Description
1. Inopportune reset of the CANIDM registers
After the reception of a CAN frame in a MOb, the ID mask registers are reset.
Problem fix / workaround
Before enabling a MOb in reception, re-initialize the ID mask registers - CANIDM[4..1].
2. The AMPCMPx bits return 0
When they are read the AMPCMPx bits in AMPxCSR registers return 0.
Problem fix / workaround
If the reading of the AMPCMPx bits is required, store the AMPCMPx value in a variable
in memory before writing in the AMPxCSR register and read the variable when
necessary.
3. No comparison when amplifier is used as comparator input and ADC input
When it is selected as ADC input, an amplifier receives no clock signal when the ADC is
stopped. In that case, if the amplifier is also used as comparator input, no analog signal
is propagated and no comparison is done.
Problem fix / workaround
Select another ADC channel rather than the working amplified channel.
4. CRC calculation of diagnostic frames in LIN 2.x.
Diagnostic frames of LIN 2.x use “classic checksum” calculation. Unfortunately, the set-
ting of the checksum model is enabled when the HEADER is transmitted/received.
Usually, in LIN 2.x the LIN/UART controller is initialized to process “enhanced check-
sums” and a slave task does not know what kind of frame it will work on before
checking the ID.
Problem fix / workaround
This workaround is to be implemented only in case of transmission/reception of diag-
nostics frames.
a. Slave task of master node:
Before enabling the HEADER, the master must set the appropriate LIN13 bitvalue
in LINCR register.
b. For slaves nodes, the workaround is in 2 parts:
– Before enabling the RESPONSE, use the following function:
void lin_wa_head(void) {
unsigned char temp;
temp = LINBTR;
LINCR = 0x00;
// It is not a RESET !
LINBTR = (1<<LDISR)|temp;
LINCR = (1<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0);
LINDLR = 0x88;
// If it isn't already done
}
– Once the RESPONSE is received or sent (having RxOK or TxOK as well as
LERR), use the following function:
void lin_wa_tail(void)
LINCR = 0x00;
{
// It is not a RESET !
LINBTR = 0x00;
LINCR = (0<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0);
}
The time-out counter is disabled during the RESPONSE when the workaround is set.
20
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
5. Wrong TSOFFSET manufacturing calibration value.
Erroneous value of TSOFFSET programmed in signature byte.
(TSOFFSET was introduced from REVB silicon).
Problem fix / workaround
To identify RevB with wrong TSOFFSET value, check device signature byte at address
0X3F if value is not 0X42 (Ascii code ‘B’) then use the following formula.
TS_OFFSET(True) = (150*(1-TS_GAIN))+TS_OFFSET.
6. PD0-PD3 set to outputs and PD4 pulled down following power-on with external
reset active.
At power-on with the external reset signal active the four I/O lines PD0-PD3 may be
forced into an output state. Normally these lines should be in an input state. PD4 may
be pulled down with internal 220 kOhm resistor. Following release of the reset line
(whatever is the startup time) with the clock running the I/Os PD0-PD4 will adopt their
intended input state.
Problem fix / workaround
None
7. LIN Break Delimitter
In SLAVE MODE, a BREAK field detection error can occur under following conditions.
The problem occurs if 2 conditions occur simultaneously:
a. The DOMINANT part of the BREAK is (N+0.5)*Tbit long with N=13, 14,15, ...
b. The RECESSIVE part of the BREAK (BREAK DELIMITER) is equal to 1*Tbit. (see
note below)
The BREAK_high is not detected, and the 2nd bit of the SYNC field is interpreted as the
BREAK DELIMITER. The error is detected as a framing error on the first bits of the PID
or on subsequent Data or a Checksum error.
There is no error if BREAK_high is greater than 1*Tbit + 18%.
There is no problem in Master mode.
Note:
LIN2.1 Protocol Specification paragraph 2.3.1.1 Break field says: “A break field is always gener-
ated by the master task(in the master node) and it shall be at least 13 nominal bit times of
dominant value, followed by a break delimiter, as shown in Figure 5-1. The break delimiter shall
be at least one nominal bit time long.”
Figure 5-1. The Break Field
Frame
Header
Response
Response space
Break
field
Sync
field
Protected
identifier
field
Data 1
Data 2
Data N
Checksum
Inter-byte space
Inter-byte space
Break
delimiter
Break
Workaround
None
21
7647ES–AVR–07/12
8. ADC measurement reports abnormal values with PSC2-synchronized conver-
sions
When using ADC in synchronized mode, an unexpected extra Single ended conversion
can spuriously re-start. This can occur when the End of conversion and the Trigger
event occur at the same time.
Workaround
No workaround
9. ADC amplifier measurement is unstable
When switching from a single-ended ADC channel to an amplified channel, noise can
appear on the next ADC conversion.
Workaround
After switching from a single ended to an amplified channel, discard the first ADC
conversion.
10. PSC emulation
In emulation mode, TCNTn, OCRnx and ICRn 16-bit registers are accessed via the
TEMP register. This can induce an execution error, in step by step mode due to TEMP
register corruption.
Workaround
No workaround
11. Read / Write instructions of MUXn and REFS1:0 bits in the ADMUX Register dur-
ing Analog conversion
During Analog conversion, the set or clear instructions of ADMUX channel and refer-
ence selection bits will fail.The bits of the temporary buffer will be written in place of the
final bits.
Workaround
Wait for the end of ADC conversion before any write of new channel or reference selec-
tion values in ADMUX.
22
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
6. Ordering Information
Table 6-1.
ATmega16/32/64/M1/C1 Ordering Codes
Memory Size
PSC
Yes
Yes
Power Supply
2.7 - 5.5V
Ordering Code
Package
MA
Operation Range
-40°C to 125°C
-40°C to 125°C
16K
16K
MEGA16M1-15AZ
MEGA16M1-15MZ
2.7 - 5.5V
PV
32K
32K
32K
32K
32K
32K
No
No
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
MEGA32C1-15AZ
MEGA32C1-15MZ
MEGA32M1-15AZ
MEGA32M1-15MZ
MEGA32M1-ESAZ
MEGA32M1-ESMZ
MA
PV
MA
PV
MA
PV
-40°C to 125°C
-40°C to 125°C
Yes
Yes
Yes
Yes
-40°C to 125°C
-40°C to 125°C
Engineering Samples
Engineering Samples
64K
64K
64K
64K
64K
64K
64K
64K
No
No
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
2.7 - 5.5V
MEGA64C1-15AZ
MEGA64C1-15MZ
MEGA64C1-ESAZ
MEGA64C1-ESMZ
MEGA64M1-15AZ
MEGA64M1-15MZ
MEGA64M1-ESAZ
MEGA64M1-ESMZ
MA
PV
MA
PV
MA
PV
MA
PV
-40°C to 125°C
-40°C to 125°C
No
Engineering Samples
Engineering Samples
-40°C to 125°C
No
Yes
Yes
Yes
Yes
-40°C to 125°C
Engineering Samples
Engineering Samples
Note:
All packages are Pb free, fully LHF
7. Package Information
Package Type
MA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness
MA
PV
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PV, 32-Lead, 7.0x7.0 mm Body, 0.65 mm Pitch
Quad Flat No Lead Package (QFN)
23
7647ES–AVR–07/12
7.1
TQFP32
24
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel ATmega16/32/64/M1/C1
7.2
QFN32
25
7647ES–AVR–07/12
8. Datasheet Revision History for ATmega16/32/64/M1/C1
Please note that the following page numbers referred to in this section refer to the specific revi-
sion mentioned, not to this document.
8.1
Revision 7647ES
1. Section “Features” on page 2 updated
2. Table 0-1 “ATmega32/64/M1/C1 Product Line-up” on page 2 updated
26
Atmel ATmega16/32/64/M1/C1
7647ES–AVR–07/12
Atmel Corporation
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San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
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Business Campus
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