ATMEGA16M1-MU [ATMEL]
8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash; 8位微控制器与16/32 / 64K字节的系统内可编程闪存
| 型号： | ATMEGA16M1-MU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash |
| 文件： | 总22页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR ® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 16/32/64K Bytes Flash of In-System Programmable Program Memory
– 512B/1K/2K Bytes of In-System Programmable EEPROM
– 1/2/4K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data Retention: 20 years at 85°C/ 100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8-bit
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified
• LIN 2.1 and 1.3 Controller or 8-Bit UART
• One 12-bit High Speed PSC (Power Stage Controller)
– Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
– Variable PWM duty Cycle and Frequency
– Synchronous Update of all PWM Registers
– Auto Stop Function for Emergency Event
• Peripheral Features
ATmega16M1
ATmega32M1
ATmega64M1
– One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode
and Capture Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– One Master/Slave SPI Serial Interface
– 10-bit ADC
Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs
Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels
Internal Reference Voltage
Direct Power Supply Voltage Measurement
– 10-bit DAC for Variable Voltage Reference (Comparators, ADC)
– Four Analog Comparators with Variable Threshold Detection
– 100µA 2% Current Source (LIN Node Identification)
– Interrupt and Wake-up on Pin Change
Preliminary
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– On-chipTemperature Sensor
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– In-System Programmable via SPI Port
– High Precision Crystal Oscillator for CAN Operations (16 MHz)
– Internal Calibrated RC Oscillator ( 8 MHz)
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)
• Operating Voltage: 2.7V - 5.5V
• Extended Operating Temperature:
– -40°C to +85°C
• Core Speed Grade:
– 0 - 8MHz @ 2.7 - 4.5V
– 0 - 16MHz @ 4.5 - 5.5V
Note:
1. See “Data Retention” on page 9 for details.
8209C–AVR–05/10
ATmega16M1/32M1/64M1
1. Pin Configurations
Figure 1-1. ATmega16M1/32M1/64M1 TQFP32/QFN32 (7*7 mm) Package.
(PCINT18/PSCIN2/OC1A/MISO_A) PD2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB4 (AMP0+/PCINT4)
PB3 (AMP0-/PCINT3)
PC6 (ADC10/ACMP1/PCINT14)
AREF(ISRC)
(PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3
(PCINT9/PSCIN1/OC1B/SS_A) PC1
VCC
AGND
GND
AVCC
(PCINT10/T0/TXCAN) PC2
(PCINT11/T1/RXCAN/ICP1B) PC3
(PCINT0/MISO/PSCOUT2A) PB0
PC5 (ADC9/ACMP3/AMP1+/PCINT13)
PC4 (ADC8/ACMPN3/AMP1-/PCINT12)
2
8209C–AVR–05/10
ATmega16M1/32M1/64M1
1.1
Pin Descriptions
Table 1-1.
Pin out description
QFN32 Pin
Number
Mnemonic
GND
Type
Power
Power
Power
Name, Function & Alternate Function
5
20
4
Ground: 0V reference
AGND
VCC
Analog Ground: 0V reference for analog part
Power Supply
Analog Power Supply: This is the power supply voltage for analog
part
19
21
AVCC
AREF
Power
Power
For a normal use this pin must be connected.
Analog Reference : reference for analog converter . This is the
reference voltage of the A/D converter. As output, can be used by
external analog
ISRC (Current Source Output)
MISO (SPI Master In Slave Out)
PSCOUT2A(1) (PSC Module 2 Output A)
PCINT0 (Pin Change Interrupt 0)
8
9
PB0
PB1
I/O
I/O
MOSI (SPI Master Out Slave In)
PSCOUT2B(1) (PSC Module 2 Output B)
PCINT1 (Pin Change Interrupt 1)
ADC5 (Analog Input Channel 5 )
INT1 (External Interrupt 1 Input)
16
PB2
I/O
ACMPN0 (Analog Comparator 0 Negative Input)
PCINT2 (Pin Change Interrupt 2)
AMP0- (Analog Differential Amplifier 0 Negative Input)
PCINT3 (Pin Change Interrupt 3)
23
24
PB3
PB4
I/O
I/O
AMP0+ (Analog Differential Amplifier 0 Positive Input)
PCINT4 (Pin Change Interrupt 4)
ADC6 (Analog Input Channel 6)
INT2 (External Interrupt 2 Input)
26
PB5
I/O
ACMPN1 (Analog Comparator 1 Negative Input)
AMP2- (Analog Differential Amplifier 2 Negative Input)
PCINT5 (Pin Change Interrupt 5)
ADC7 (Analog Input Channel 7)
27
28
30
PB6
PB7
PC0
I/O
I/O
I/O
PSCOUT1B(1) (PSC Module 1 Output A)
PCINT6 (Pin Change Interrupt 6)
ADC4 (Analog Input Channel 4)
PSCOUT0B(1) (PSC Module 0 Output B)
SCK (SPI Clock)
PCINT7 (Pin Change Interrupt 7)
PSCOUT1A(1) (PSC Module 1 Output A)
INT3 (External Interrupt 3 Input)
PCINT8 (Pin Change Interrupt 8)
3
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Table 1-1.
Pin out description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function & Alternate Function
PSCIN1 (PSC Digital Input 1)
OC1B (Timer 1 Output Compare B)
SS_A (Alternate SPI Slave Select)
PCINT9 (Pin Change Interrupt 9)
3
6
7
PC1
I/O
T0 (Timer 0 clock input)
PC2
PC3
I/O
I/O
I/O
TXCAN (CAN Transmit Output)
PCINT10 (Pin Change Interrupt 10)
T1 (Timer 1 clock input)
RXCAN (CAN Receive Input)
ICP1B (Timer 1 input capture alternate B input)
PCINT11 (Pin Change Interrupt 11)
ADC8 (Analog Input Channel 8)
AMP1- (Analog Differential Amplifier 1 Negative Input)
ACMPN3 (Analog Comparator 3 Negative Input )
PCINT12 (Pin Change Interrupt 12)
17
PC4
ADC9 (Analog Input Channel 9)
AMP1+ (Analog Differential Amplifier 1 Positive Input)
ACMP3 (Analog Comparator 3 Positive Input)
PCINT13 (Pin Change Interrupt 13)
18
22
PC5
PC6
I/O
I/O
ADC10 (Analog Input Channel 10)
ACMP1 (Analog Comparator 1 Positive Input )
PCINT14 (Pin Change Interrupt 14)
D2A (DAC output )
25
29
32
PC7
PD0
PD1
I/O
I/O
I/O
AMP2+ (Analog Differential Amplifier 2 Positive Input)
PCINT15 (Pin Change Interrupt 15)
PSCOUT0A(1) (PSC Module 0 Output A)
PCINT16 (Pin Change Interrupt 16)
PSCIN0 (PSC Digital Input 0)
CLKO (System Clock Output)
PCINT17 (Pin Change Interrupt 17)
OC1A (Timer 1 Output Compare A)
PSCIN2 (PSC Digital Input 2)
1
2
PD2
PD3
I/O
I/O
MISO_A (Programming & alternate SPI Master In Slave Out)
PCINT18 (Pin Change Interrupt 18)
TXD (UART Tx data)
TXLIN (LIN Transmit Output)
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
MOSI_A (Programming & alternate Master Out SPI Slave In)
PCINT19 (Pin Change Interrupt 19)
4
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Table 1-1.
Pin out description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function & Alternate Function
ADC1 (Analog Input Channel 1)
RXD (UART Rx data)
RXLIN (LIN Receive Input)
12
PD4
I/O
ICP1A (Timer 1 input capture alternate A input)
SCK_A (Programming & alternate SPI Clock)
PCINT20 (Pin Change Interrupt 20)
ADC2 (Analog Input Channel 2)
13
14
PD5
PD6
I/O
I/O
ACMP2 (Analog Comparator 2 Positive Input )
PCINT21 (Pin Change Interrupt 21)
ADC3 (Analog Input Channel 3 )
ACMPN2 (Analog Comparator 2 Negative Input)
INT0 (External Interrupt 0 Input)
PCINT22 (Pin Change Interrupt 22)
ACMP0 (Analog Comparator 0 Positive Input )
PCINT23 (Pin Change Interrupt 23)
15
31
PD7
PE0
I/O
RESET (Reset Input)
I/O or I
OCD (On Chip Debug I/O)
PCINT24 (Pin Change Interrupt 24)
XTAL1 (XTAL Input)
10
11
PE1
PE2
I/O
I/O
OC0B (Timer 0 Output Compare B)
PCINT25 (Pin Change Interrupt 25)
XTAL2 (XTAL Output)
ADC0 (Analog Input Channel 0)
PCINT26 (Pin Change Interrupt 26)
Note:
1. Only for Atmega32M1/64M1.
2. On the engineering samples, the ACMPN3 alternate function is not located on PC4. It is
located on PE2.
2. Overview
The ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega16M1/32M1/64M1 achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
5
8209C–AVR–05/10
ATmega16M1/32M1/64M1
2.1
Block Diagram
Figure 2-1. Block Diagram
Data Bus 8-bit
Interrupt
Unit
Program
Counter
Status
and Control
Flash Program
Memory
SPI
Unit
32 x 8
General
Purpose
Registrers
Instruction
Register
Watchdog
Timer
4 Analog
Comparators
Instruction
Decoder
ALU
HW LIN/UART
Timer 0
Timer 1
ADC
Control Lines
Data
SRAM
EEPROM
DAC
MPSC
I/O Lines
CAN
Current Source
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega16M1/32M1/64M1 provides the following features: 16/32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM,
1/2/4K bytes SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one
Motor Power Stage Controller, two flexible Timer/Counters with compare modes and PWM, one
UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with program-
mable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator,
an SPI serial port, an On-chip Debug system and four software selectable power saving modes.
6
8209C–AVR–05/10
ATmega16M1/32M1/64M1
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN,
LIN/UART and interrupt system to continue functioning. The Power-down mode saves the regis-
ter contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except
ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Reso-
nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega16M1/32M1/64M1 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega16M1/32M1/64M1 AVR is supported with a full suite of program and system devel-
opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
2.2.2
2.2.3
GND
Ground.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16M1/32M1/64M1 as
listed on page 72.
2.2.4
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega16M1/32M1/64M1 as listed
on page 75.
7
8209C–AVR–05/10
ATmega16M1/32M1/64M1
2.2.5
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16M1/32M1/64M1 as
listed on page 79.
2.2.6
Port E (PE2..0) RESET/ XTAL1/
XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-
acteristics of PE0 differ from those of the other pins of Port E.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in “System and Reset Characteristics” on page 313. Shorter
pulses are not guaranteed to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page
82 and “Clock Systems and their Distribution” on page 27.
2.2.7
2.2.8
AVCC
AREF
AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should
be externally connected to VCC, even if the ADC, DAC are not used. If the ADC is used, it should
be connected to VCC through a low-pass filter.
This is the analog reference pin for the A/D Converter.
8
8209C–AVR–05/10
ATmega16M1/32M1/64M1
3. Disclaimer
4. Resources
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
6. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
9
8209C–AVR–05/10
ATmega16M1/32M1/64M1
7. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
Reserved
Reserved
Reserved
Reserved
Reserved
CANMSG
CANSTMPH
CANSTMPL
CANIDM1
CANIDM2
CANIDM3
CANIDM4
CANIDT1
CANIDT2
CANIDT3
CANIDT4
CANCDMOB
CANSTMOB
CANPAGE
CANHPMOB
CANREC
CANTEC
CANTTCH
CANTTCL
CANTIMH
CANTIML
CANTCON
CANBT3
CANBT2
CANBT1
CANSIT1
CANSIT2
CANIE1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MSG 7
TIMSTM15
TIMSTM7
IDMSK28
IDMSK20
IDMSK12
MSG 6
TIMSTM14
TIMSTM6
IDMSK27
IDMSK19
IDMSK11
MSG 5
TIMSTM13
TIMSTM5
IDMSK26
IDMSK18
IDMSK10
MSG 4
TIMSTM12
TIMSTM4
IDMSK25
IDMSK17
MSG 3
TIMSTM11
TIMSTM3
IDMSK24
IDMSK16
MSG 2
TIMSTM10
TIMSTM2
IDMSK23
IDMSK15
MSG 1
TIMSTM9
TIMSTM1
IDMSK22
IDMSK14
MSG 0
TIMSTM8
TIMSTM0
IDMSK21
IDMSK13
page 197
page 197
page 197
page 196
page 196
page 196
page 196
page 194
page 194
page 194
page 194
page 193
page 192
page 192
page 191
page 191
page 191
page 191
page 191
page 191
page 191
page 190
page 190
page 189
page 188
page 188
page 188
page 188
page 188
page 187
page 187
page 186
page 185
page 184
page 183
IDMSK
9
1
IDMSK
8
0
IDMSK
7
IDMSK
6
IDMSK5
IDMSK
4
IDMSK
3
IDMSK
2
IDMSK
IDMSK
RTRMSK
IDT23
–
IDEMSK
IDT21
IDT28
IDT20
IDT12
IDT27
IDT19
IDT11
IDT26
IDT18
IDT10
IDT25
IDT17
IDT24
IDT16
IDT22
IDT14
IDT15
IDT13
IDT
9
1
IDT
8
0
IDT
7
IDT
6
IDT5
IDT
4
IDT
3
IDT
2
IDT
IDT
RTRTAG
DLC2
CERR
INDX2
CGP2
REC2
TEC2
TIMTTC10
TIMTTC2
CANTIM10
CANTIM2
TPRSC2
PHS11
PRS1
BRP1
–
RB1TAG
DLC1
FERR
INDX1
CGP1
REC1
TEC1
TIMTTC9
TIMTTC1
CANTIM9
CANTIM1
TRPSC1
PHS10
PRS0
BRP0
–
RB0TAG
DLC0
AERR
INDX0
CGP0
REC0
TEC0
TIMTTC8
TIMTTC0
CANTIM8
CANTIM0
TPRSC0
SMP
–
CONMOB1
CONMOB0
RPLV
IDE
DLC3
SERR
AINC
CGP3
REC3
TEC3
TIMTTC11
TIMTTC3
CANTIM11
CANTIM3
TPRSC3
PHS12
PRS2
BRP2
–
DLCW
TXOK
RXOK
BERR
MOBNB3
MOBNB2
MOBNB1
MOBNB0
HPMOB3
HPMOB2
HPMOB1
HPMOB0
REC7
REC6
REC5
REC4
TEC7
TEC6
TEC5
TEC4
TIMTTC15
TIMTTC14
TIMTTC13
TIMTTC12
TIMTTC7
TIMTTC6
TIMTTC5
TIMTTC4
CANTIM15
CANTIM14
CANTIM13
CANTIM12
CANTIM7
CANTIM6
CANTIM5
CANTIM4
TPRSC7
TPRSC6
TPRSC5
TPRSC4
–
PHS22
PHS21
PHS20
–
SJW1
SJW0
–
–
BRP5
BRP4
BRP3
–
–
–
–
–
–
–
–
SIT5
SIT4
SIT3
SIT2
SIT1
SIT0
–
–
–
–
–
–
–
–
CANIE2
–
–
IEMOB5
IEMOB4
IEMOB3
–
IEMOB2
–
IEMOB1
–
IEMOB0
–
CANEN1
CANEN2
CANGIE
–
–
–
–
–
–
ENMOB5
ENMOB4
ENMOB3
ENERR
SERG
RXBSY
LISTEN
–
ENMOB2
ENBX
CERG
ENFG
TEST
–
ENMOB1
ENERG
FERG
BOFF
ENA/STB
–
ENMOB0
ENOVRT
AERG
ERRP
SWRES
–
ENIT
ENBOFF
ENRX
ENTX
CANGIT
CANIT
BOFFIT
OVRTIM
BXOK
CANGSTA
CANGCON
Reserved
Reserved
Reserved
Reserved
Reserved
LINDAT
–
OVRG
–
TXBSY
ABRQ
OVRQ
TTC
SYNTTC
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
/LAINC
LID3
LDATA2
LINDX2
LID2
LDATA1
LINDX1
LID1
LDATA0
LINDX0
LID0
LRXDL0
LDIV8
LDIV0
LBT0
LBERR
LENRXOK
LRXOK
LCMD0
–
page 224
page 223
page 223
page 222
page 222
page 222
page 222
page 221
page 220
page 219
page 218
LINSEL
–
–
–
–
LINIDR
LP1
LP0
LID5 / LDL1
LID4 / LDL0
LINDLR
LTXDL3
LTXDL2
LTXDL1
LTXDL0
LRXDL3
LDIV11
LDIV3
LBT3
LSERR
LENERR
LERR
LENA
–
LRXDL2
LDIV10
LDIV2
LBT2
LPERR
LENIDOK
LIDOK
LCMD2
–
LRXDL1
LDIV9
LDIV1
LBT1
LCERR
LENTXOK
LTXOK
LCMD1
–
LINBRRH
LINBRRL
LINBTR
–
–
–
–
LDIV7
LDIV6
LDIV5
LDIV4
LDISR
–
LBT5
LBT4
LINERR
LABORT
LTOERR
LOVERR
LFERR
LINENIR
–
–
–
–
LINSIR
LIDST2
LIDST1
LIDST0
LBUSY
LINCR
LSWRES
LIN13
LCONF1
LCONF0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
10
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBE)
(0xBD)
(0xBC)(5)
(0xBB)(5)
(0xBA)(5)
(0xB9)(5)
(0xB8)(5)
(0xB7)(5)
(0xB6)(5)
(0xB5)(5)
(0xB4)(5)
(0xB3)(5)
(0xB2)(5)
(0xB1)(5)
(0xB0)(5)
(0xAF)(5)
(0xAE)(5)
(0xAD)(5)
(0xAC)(5)
(0xAB)(5)
(0xAA)(5)
(0xA9)(5)
(0xA8)(5)
(0xA7)(5)
(0xA6)(5)
(0xA5)(5)
(0xA4)(5)
(0xA3)(5)
(0xA2)(5)
(0xA1)(5)
(0xA0)(5)
(0x9F)
Reserved
Reserved
PIFR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PEV2
PEV1
PEV0
PEOP
page 153
page 152
page 151
page 151
page 151
page 151
page 147
page 150
page 148
page 150
page 150
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
page 149
PIM
–
–
–
–
PEVE2
PAOC2
PAOC1
PAOC0
–
PEVE1
PRFM22
PRFM12
PRFM02
–
PEVE0
PRFM21
PRFM11
PRFM01
PCCYC
POEN0B
–
PEOPE
PRFM20
PRFM10
PRFM00
PRUN
PMIC2
POVEN2
PISEL2
PELEV2
PFLTE2
PMIC1
POVEN1
PISEL1
PELEV1
PFLTE1
PMIC0
POVEN0
PISEL0
PELEV0
PFLTE0
PCTL
PPRE1
PPRE0
PCLKSEL
–
POC
–
–
POEN2B
POEN2A
POEN1B
POPB
POEN1A
POPA
POEN0A
–
PCNF
–
–
PULOCK
PMODE
PSYNC
–
–
PSYNC21
PSYNC20
PSYNC11
POCR_RB11
POCR_RB3
POCR2SB11
POCR2SB3
POCR2RA11
POCR2RA3
POCR2SA11
POCR2SA3
POCR1SB11
POCR1SB3
POCR1RA11
POCR1RA3
POCR1SA11
POCR1SA3
POCR0SB11
POCR0SB3
POCR0RA11
POCR0RA3
POCR0SA11
POCR0SA3
–
PSYNC10
POCR_RB10
POCR_RB2
POCR2SB10
POCR2SB2
POCR2RA10
POCR2RA2
POCR2SA10
POCR2SA2
POCR1SB10
POCR1SB2
POCR1RA10
POCR1RA2
POCR1SA10
POCR1SA2
POCR0SB10
POCR0SB2
POCR0RA10
POCR0RA2
POCR0SA10
POCR0SA2
–
PSYNC01
POCR_RB9
POCR_RB1
POCR2SB9
POCR2SB1
POCR2RA9
POCR2RA1
POCR2SA9
POCR2SA1
POCR1SB9
POCR1SB1
POCR1RA9
POCR1RA1
POCR1SA9
POCR1SA1
POCR0SB9
POCR0SB1
POCR0RA9
POCR0RA1
POCR0SA9
POCR0SA1
–
PSYNC00
POCR_RB8
POCR_RB0
POCR2SB8
POCR2SB0
POCR2RA8
POCR2RA0
POCR2SA8
POCR2SA0
POCR1SB8
POCR1SB0
POCR1RA8
POCR1RA0
POCR1SA8
POCR1SA0
POCR0SB8
POCR0SB0
POCR0RA8
POCR0RA0
POCR0SA8
POCR0SA0
–
POCR_RBH
POCR_RBL
POCR2SBH
POCR2SBL
POCR2RAH
POCR2RAL
POCR2SAH
POCR2SAL
POCR1SBH
POCR1SBL
POCR1RAH
POCR1RAL
POCR1SAH
POCR1SAL
POCR0SBH
POCR0SBL
POCR0RAH
POCR0RAL
POCR0SAH
POCR0SAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AC3CON
AC2CON
AC1CON
AC0CON
Reserved
DACH
–
–
–
–
POCR_RB7
POCR_RB6
POCR_RB5
POCR_RB4
–
–
–
–
POCR2SB7
POCR2SB6
POCR2SB5
POCR2SB4
–
–
–
–
POCR2RA7
POCR2RA6
POCR2RA5
POCR2RA4
–
–
–
–
POCR2SA7
POCR2SA6
POCR2SA5
POCR2SA4
–
–
–
–
POCR1SB7
POCR1SB6
POCR1SB5
POCR1SB4
–
–
–
–
POCR1RA7
POCR1RA6
POCR1RA5
POCR1RA4
–
–
–
–
POCR1SA7
POCR1SA6
POCR1SA5
POCR1SA4
–
–
–
–
POCR0SB7
POCR0SB6
POCR0SB5
POCR0SB4
–
–
–
–
POCR0RA7
POCR0RA6
POCR0RA5
POCR0RA4
–
–
–
–
POCR0SA7
POCR0SA6
POCR0SA5
POCR0SA4
–
–
–
–
(0x9E)
–
–
–
–
–
–
–
–
(0x9D)
–
–
–
–
–
–
–
–
–
(0x9C)
–
–
–
–
–
–
–
(0x9B)
–
–
–
–
–
–
–
–
–
–
–
(0x9A)
–
–
–
–
–
(0x99)
–
–
–
–
–
–
–
–
(0x98)
–
–
–
–
–
–
–
–
(0x97)
AC3EN
AC2EN
AC1EN
AC0EN
–
AC3IE
AC2IE
AC1IE
AC0IE
–
AC3IS1
AC2IS1
AC1IS1
AC0IS1
–
AC3IS0
AC2IS0
AC1IS0
AC0IS0
–
–
AC3M2
AC2M2
AC1M2
AC0M2
–
AC3M1
AC2M1
AC1M1
AC0M1
–
AC3M0
AC2M0
AC1M0
AC0M0
–
page 260
page 260
page 259
page 258
(0x96)
–
(0x95)
AC1ICE
ACCKSEL
–
(0x94)
(0x93)
(0x92)
- / DAC9
- / DAC8
- / DAC7
DAC5 / -
DATS1
–
- / DAC6
DAC4 / -
DATS0
–
- / DAC5
DAC3 / -
–
- / DAC4
DAC2 / -
DALA
DAC9 / DAC3
DAC1 / -
DAOE
DAC8 / DAC2
DAC0 /
DAEN
page 268
page 268
page 267
(0x91)
DACL
DAC7 / DAC1 DAC6 /DAC0
(0x90)
DACON
DAATE
–
DATS2
–
(0x8F)
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
–
–
–
–
(0x8E)
–
–
–
–
–
–
–
–
(0x8D)
–
–
–
–
–
–
–
–
(0x8C)
–
–
–
–
–
–
–
–
(0x8B)
OCR1B15
OCR1B7
OCR1A15
OCR1A7
ICR115
ICR17
TCNT115
TCNT17
–
OCR1B14
OCR1B6
OCR1A14
OCR1A6
ICR114
ICR16
TCNT114
TCNT16
–
OCR1B13
OCR1B5
OCR1A13
OCR1A5
ICR113
ICR15
TCNT113
TCNT15
–
OCR1B12
OCR1B4
OCR1A12
OCR1A4
ICR112
ICR14
TCNT112
TCNT14
–
OCR1B11
OCR1B3
OCR1A11
OCR1A3
ICR111
ICR13
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
ICR12
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
page 128
page 128
page 128
page 128
page 129
page 129
page 128
page 128
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
ICR1L
ICR11
ICR10
(0x85)
TCNT1H
TCNT111
TCNT13
–
TCNT110
TCNT12
–
TCNT19
TCNT11
–
TCNT18
TCNT10
–
(0x84)
TCNT1L
(0x83)
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
(0x82)
FOC1A
ICNC1
COM1A1
–
FOC1B
ICES1
COM1A0
AMP2PD
ADC6D
–
–
–
–
–
–
–
page 127
page 126
page 124
page 248
page 248
(0x81)
–
WGM13
COM1B0
AMP0PD
ADC4D
–
WGM12
–
CS12
CS11
CS10
(0x80)
COM1B1
ACMP0D
ADC5D
–
–
WGM11
ADC9D
ADC1D
–
WGM10
ADC8D
ADC0D
–
(0x7F)
AMP0ND
ADC3D
–
ADC10D
ADC2D
–
(0x7E)
DIDR0
ADC7D
–
(0x7D)
Reserved
11
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7C)
(0x7B)
ADMUX
ADCSRB
ADCSRA
ADCH
REFS1
ADHSM
ADEN
REFS0
ISRCEN
ADSC
ADLAR
–
MUX3
MUX2
MUX1
MUX0
page 244
page 246
page 245
page 247
page 247
page 250
page 250
page 249
AREFEN
–
ADTS3
ADTS2
ADTS1
ADTS0
(0x7A)
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
- / ADC9
- / ADC8
- / ADC7
- / ADC6
- / ADC5
- / ADC4
ADC9 / ADC3
ADC8 / ADC2
(0x78)
ADCL
ADC7 / ADC1 ADC6 / ADC0
ADC5 / -
ADC4 / -
ADC3 / -
ADC2 / -
ADC1 / -
ADC0 /
(0x77)
AMP2CSR
AMP1CSR
AMP0CSR
Reserved
Reserved
Reserved
Reserved
Reserved
TIMSK1
TIMSK0
PCMSK3
PCMSK2
PCMSK1
PCMSK0
EICRA
AMP2EN
AMP2IS
AMP2G1
AMP2G0
AMPCMP2
AMP2TS2
AMP2TS1
AMP2TS0
(0x76)
AMP1EN
AMP1IS
AMP1G1
AMP1G0
AMPCMP1
AMP1TS2
AMP1TS1
AMP1TS0
(0x75)
AMP0EN
AMP0IS
AMP0G1
AMP0G0
AMPCMP0
AMP0TS2
AMP0TS1
AMP0TS0
(0x74)
–
–
–
–
–
–
–
–
(0x73)
–
–
–
–
–
–
–
–
(0x72)
–
–
–
–
–
–
–
–
(0x71)
–
–
–
–
–
–
–
–
(0x70)
–
–
–
–
–
–
–
–
(0x6F)
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
page 129
page 101
page 63
page 64
page 64
page 64
page 61
(0x6E)
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
(0x6D)
–
–
–
–
–
PCINT26
PCINT25
PCINT24
(0x6C)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
(0x6B)
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
(0x6A)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
(0x69)
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
(0x68)
Reserved
Reserved
OSCCAL
Reserved
PRR
–
–
–
–
–
–
–
–
(0x67)
–
–
–
–
–
–
–
–
(0x66)
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
page 35
page 42
(0x65)
–
–
–
–
–
–
–
–
(0x64)
–
PRCAN
PRPSC
PRTIM1
PRTIM0
PRSPI
PRLIN
PRADC
(0x63)
Reserved
Reserved
CLKPR
–
–
–
–
–
–
–
–
(0x62)
–
–
–
–
–
–
–
–
(0x61)
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 36
page 51
page 11
page 14
page 14
(0x60)
WDTCSR
SREG
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
I
T
H
S
V
N
Z
C
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPL
SP7
SP6
SP5
–
SP4
SP3
SP2
SP1
SP0
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BLBSET
–
–
PGWRT
–
–
–
SPMIE
RWWSB
–
RWWSRE
PGERS
–
SPMEN
–
page 277
–
–
–
–
–
–
–
PUD
–
SPIPS
–
–
–
IVSEL
EXTRF
SM0
IVCE
PORF
SE
page 58 & page 84
page 51
–
–
–
WDRF
SM2
BORF
SM1
–
–
page 38
MSMCR
MONDR
ACSR
Monitor Stop Mode Control Register
Monitor Data Register
reserved
reserved
AC3IF
AC2IF
AC1IF
AC0IF
AC3O
–
AC2O
–
AC1O
–
AC0O
–
page 262
Reserved
SPDR
–
–
–
–
SPD7
SPD6
SPD5
SPD4
SPD3
–
SPD2
–
SPD1
–
SPD0
page 163
page 162
page 161
SPSR
SPIF
WCOL
–
–
SPI2X
SPR0
SPCR
SPIE
SPE
DORD
MSTR
CPOL
–
CPHA
–
SPR1
–
Reserved
Reserved
PLLCSR
OCR0B
OCR0A
TCNT0
–
–
–
–
–
–
-
–
-
–
–
–
–
–
–
-
-
-
PLLF
OCR0B2
OCR0A2
TCNT02
CS02
–
PLLE
OCR0B1
OCR0A1
TCNT01
CS01
WGM01
–
PLOCK
OCR0B0
OCR0A0
TCNT00
CS00
page 35
page 101
page 101
page 101
page 100
page 97
page 133
page 22
page 22
page 22
page 22
page 26
page 61
page 62
page 63
OCR0B7
OCR0A7
TCNT07
FOC0A
COM0A1
TSM
OCR0B6
OCR0A6
TCNT06
FOC0B
COM0A0
ICPSEL1
–
OCR0B5
OCR0B4
OCR0B3
OCR0A3
TCNT03
WGM02
–
OCR0A5
OCR0A4
TCNT05
TCNT04
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
–
–
COM0B1
COM0B0
WGM00
PSRSYNC
EEAR8
EEAR0
EEDR0
EERE
GPIOR00
INT0
–
–
–
–
–
–
–
–
–
EEAR9
EEAR1
EEDR1
EEWE
GPIOR01
INT1
EEAR7
EEDR7
–
EEAR6
EEDR6
–
EEAR5
EEAR4
EEAR3
EEDR3
EERIE
GPIOR03
INT3
INTF3
PCIF3
EEAR2
EEDR2
EEMWE
GPIOR02
INT2
INTF2
PCIF2
EEDR
EEDR5
EEDR4
EECR
–
–
GPIOR0
EIMSK
GPIOR07
–
GPIOR06
–
GPIOR05
GPIOR04
–
–
–
–
–
–
EIFR
–
–
INTF1
PCIF1
INTF0
PCIF0
PCIFR
–
–
12
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
GPIOR2
GPIOR1
Reserved
Reserved
TIFR1
GPIOR27
GPIOR26
GPIOR25
GPIOR24
GPIOR23
GPIOR22
GPIOR21
GPIOR20
page 26
page 26
GPIOR17
GPIOR16
GPIOR15
GPIOR14
GPIOR13
GPIOR12
GPIOR11
GPIOR10
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ICF1
–
–
OCF1B
OCF0B
–
OCF1A
OCF0A
–
TOV1
TOV0
–
page 130
page 102
TIFR0
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTE2
DDE2
PINE2
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
–
PORTE1
DDE1
PINE1
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
–
PORTE0
DDE0
PINE0
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
–
page 85
page 85
page 85
page 85
page 85
page 85
page 84
page 84
page 84
page 84
page 84
page 84
–
–
–
–
–
PINE
–
–
–
–
–
PORTD
DDRD
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
–
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
–
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
–
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
–
PORTD3
DDD3
PIND3
PORTC3
DDC3
PINC3
PORTB3
DDB3
PINB3
–
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are
reserved.
13
8209C–AVR–05/10
ATmega16M1/32M1/64M1
8. Errata
8.1
Errata ATmega16M1
The revision letter in this section refers to revisions of the ATmega16M1 device.
8.1.1
Rev. A
Not samplet
8.2
Errata ATmega32M1
The revision letter in this section refers to revisions of the ATmega32M1 device.
8.2.1
Rev. A
Not samplet
8.3
Errata ATmega64M1
The revision letter in this section refers to revisions of the ATmega64M1 device.
8.3.1
Rev. A
Not samplet
14
8209C–AVR–05/10
ATmega16M1/32M1/64M1
9. Ordering Information
9.1
ATmega16M1
Speed
Power Supply
Ordering Code
Package
32A
Operation Range
ATmega16M1 - AU
ATmega16M1 - MU
Industrial
16MHz
2.7 - 5.5V
(-40°C to 85°C)
PV
Note:
All packages are Pb free, fully LHF
Package Type
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
PV, 32-Lead, 7.0x7.0 mm Body, 0.65 mm Pitch Quad Flat No Lead Package (QFN)
32A
PV
15
8209C–AVR–05/10
ATmega16M1/32M1/64M1
9.2
ATmega32M1
Speed
Power Supply
Ordering Code
Package
32A
Operation Range
ATmega32M1 - AU
ATmega32M1 - MU
Industrial
16MHz
2.7 - 5.5V
(-40°C to 85°C)
PV
Note:
All packages are Pb free, fully LHF
Package Type
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
PV, 32-Lead, 7.0x7.0 mm Body, 0.65 mm Pitch Quad Flat No Lead Package (QFN)
32A
PV
16
8209C–AVR–05/10
ATmega16M1/32M1/64M1
9.3
ATmega64M1
Speed
Power Supply
Ordering Code
Package
32A
Operation Range
ATmega64M1 - AU
ATmega64M1 - MU
Industrial
16MHz
2.7 - 5.5V
(-40°C to 85°C)
PV
Note:
All packages are Pb free, fully LHF
Package Type
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
PV, 32-Lead, 7.0x7.0 mm Body, 0.65 mm Pitch Quad Flat No Lead Package (QFN)
32A
PV
17
8209C–AVR–05/10
ATmega16M1/32M1/64M1
10. Packaging Information
10.1 32A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
0.15
1.05
9.25
7.10
9.25
7.10
0.45
0.20
0.75
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
8.75
6.90
8.75
6.90
0.30
0.09
0.45
1.00
9.00
7.00
9.00
7.00
–
D1
E
Note 2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
C
–
3. Lead coplanarity is 0.10 mm maximum.
L
–
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
32A
B
R
18
8209C–AVR–05/10
ATmega16M1/32M1/64M1
10.2 PV
19
8209C–AVR–05/10
ATmega16M1/32M1/64M1
11. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
11.1 8209C – 05/10
11.2 8209B – 10/09
11.3 8209A – 08/09
1.
2.
Replaced 32M1-A package information drawing with PV drawing on page 334.
Updated ordering information with correct info on PV package.
1.
2.
Updated “Temperature Measurement” on page 238.
Updated “Manufacturing Calibration” on page 239.
1.
Initial revision.
20
8209C–AVR–05/10
ATmega16M1/32M1/64M1
Table of Contents
Features ..................................................................................................... 1
1
2
Pin Configurations ................................................................................... 2
1.1
Pin Descriptions .................................................................................................3
Overview ................................................................................................... 5
2.1
2.2
Block Diagram ...................................................................................................6
Pin Descriptions .................................................................................................7
3
4
5
6
7
8
Disclaimer ................................................................................................. 9
Resources ................................................................................................. 9
About Code Examples ............................................................................. 9
Data Retention .......................................................................................... 9
Register Summary ................................................................................. 10
Errata ....................................................................................................... 14
8.1
8.2
8.3
Errata ATmega16M1 .......................................................................................14
Errata ATmega32M1 .......................................................................................14
Errata ATmega64M1 .......................................................................................14
9
Ordering Information ............................................................................. 15
9.1
9.2
9.3
ATmega16M1 ..................................................................................................15
ATmega32M1 ..................................................................................................16
ATmega64M1 ..................................................................................................17
10 Packaging Information .......................................................................... 18
10.1
10.2
32A ..................................................................................................................18
PV ....................................................................................................................19
11 Datasheet Revision History ................................................................... 20
11.1
11.2
11.3
8209C – 05/10 .................................................................................................20
8209B – 10/09 .................................................................................................20
8209A – 08/09 .................................................................................................20
Table of Contents....................................................................................... i
i
8209C–AVR–05/10
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
avr@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF
THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof AVR®, and others are registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
8209C–AVR–05/10
相关型号：
©2020 ICPDF网 联系我们和版权申明