ATMEGA16U2-AU [ATMEL]
8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller; 8位微控制器具有ISP功能的Flash和USB控制器8/16 / 32K字节型号: | ATMEGA16U2-AU |
厂家: | ATMEL |
描述: | 8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller |
文件: | 总21页 (文件大小:341K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Non-volatile Program and Data Memories
– 8K/16K/32K Bytes of In-System Self-Programmable Flash
– 512/512/1024 EEPROM
– 512/512/1024 Internal SRAM
8-bit
Microcontroller
with
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by on-chip Boot Program hardware-activated after
reset
True Read-While-Write Operation
– Programming Lock for Software Security
• USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
8/16/32K Bytes
of ISP Flash
and USB
IN or Out Directions
Controller
Bulk, Interrupt and IsochronousTransfers
Programmable maximum packet size from 8 to 64 bytes
Programmable single or double buffer
– Suspend/Resume Interrupts
ATmega8U2
ATmega16U2
ATmega32U2
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
• Peripheral Features
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
PWM channels)
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
(three 8-bit PWM channels)
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• On Chip Debug Interface (debugWIRE)
• Special Microcontroller Features
Summary
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
• I/O and Packages
– 22 Programmable I/O Lines
– QFN32 (5x5mm) / TQFP32 packages
• Operating Voltages
– 2.7 - 5.5V
• Operating temperature
– Industrial (-40°C to +85°C)
• Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
Note:
1. See “Data Retention” on page 6 for details.
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
1. Pin Configurations
Figure 1-1. Pinout
32 31 30 29 28 27 26 25
Reset (PC1 / dW)
XTAL1
(PC0) XTAL2
GND
1
2
3
4
24
23
22
21
20
19
18
17
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
VCC
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
QFN32
5
6
7
8
PB5 (PCINT5)
(AIN0 / INT1) PD1
PB4 (T1 / PCINT4)
(RXD1 / AIN1 / INT2) PD2
PB3 (PDO / MISO / PCINT3)
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
Reset (PC1 / dW)
24
XTAL1
1
2
3
4
5
6
7
8
(PC0) XTAL2
GND
PC6 (OC.1A / PCINT8)
23
22
21
20
19
18
17
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
VCC
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
VQFP32
PB6 (PCINT6)
PB5 (PCINT5)
(AIN0 / INT1) PD1
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
(RXD1 / AIN1 / INT2) PD2
9 10 11 12 13 14 15 16
Note:
The large center pad underneath the VQFP and QFN package should be soldered to ground on
the board to ensure good mechanical stability.
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
2. Overview
The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching
1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
PD7 - PD0
PC7 - PC0
PB7 - PB0
PORTC DRIVERS
PORTD DRIVERS
PORTB DRIVERS
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
8-BIT DA TA BUS
VCC
GND
POR - BOD
RESET
INTERNAL
OSCILLATOR
CALIB. OSC
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
COUNTER
STACK
POINTER
Debug-Wire
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
INSTRUCTION
REGISTER
TIMER/
COUNTERS
PROGRAMMING
LOGIC
GENERAL
PURPOSE
REGISTERS
UVcc
X
Y
Z
INSTRUCTION
DECODER
INTERRUPT
UNIT
ON-CHIP
3.3V
REGULATOR
UCap
CONTROL
LINES
1uF
ALU
EEPROM
PLL
STATUS
REGISTER
D+/SCK
D-/SDATA
USB
PS/2
SPI
USART1
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
3
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega8U2/16U2/32U2 provides the following features: 8K/16K/32K Bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512/512/1024 Bytes EEPROM,
512/512/1024 SRAM, 22 general purpose I/O lines, 32 general purpose working registers, two
flexible Timer/Counters with compare modes and PWM, one USART, a programmable Watch-
dog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for
accessing the On-chip Debug system and programming and five software selectable power sav-
ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware
Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device
is sleeping. This allows very fast start-up combined with low power consumption. In Extended
Standby mode, the main Oscillator continues to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega8U2/16U2/32U2 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega8U2/16U2/32U2 are supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
Ground.
2.2.2
2.2.3
GND
AVCC
AVCC is the supply voltage pin (input) for all analog features (Analog Comparator, PLL). It
should be externally connected to VCC through a low-pass filter.
2.2.4
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8U2/16U2/32U2 as
listed on page 74.
4
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
2.2.5
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of various special features of the ATmega8U2/16U2/32U2 as
listed on page 77.
2.2.6
Port D (PD7..PD0)
Port D serves as analog inputs to the analog comparator.
Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-
cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
D-
USB Full Speed Negative Data Upstream Port
USB Full Speed Positive Data Upstream Port
USB Ground.
D+
UGND
UVCC
UCAP
USB Pads Internal Regulator Input supply voltage.
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1µF).
2.2.12
RESET/PC1/dW
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in “System Control and
Reset” on page 47. Shorter pulses are not guaranteed to generate a reset. This pin alternatively
serves as debugWire channel or as generic I/O. The configuration depends on the fuses RST-
DISBL and DWEN.
2.2.13
2.2.14
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.
XTAL2/PC0
5
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4. Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
6. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
Reserved
Reserved
Reserved
Reserved
UPOE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UPWE1
UPWE0
UPDRV1
UPDRV0
SCKI
DATAI
DPI
DMI
page 195
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UEINT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EPINT4:0
-
page 222
Reserved
UEBCLX
UEDATX
UEIENX
-
-
-
-
-
BYCT7:0
DAT7:0
page 221
page 221
page 220
page 218
page 217
page 216
page 215
page 214
page 214
page 214
page 219
FLERRE
NAKINE
-
-
NAKOUTE
RXSTPE
-
RXOUTE
CTRLDIR
STALLEDE
TXINE
UESTA1X
UESTA0X
UECFG1X
UECFG0X
UECONX
UERST
-
-
-
-
CURRBK1:0
NBUSYBK1:0
ALLOC
CFGOK
-
OVERFI
UNDERFI
DTSEQ1:0
EPBK1:0
EPSIZE2:0
-
EPTYPE1:0
-
-
-
-
-
-
EPDIR
EPEN
-
-
STALLRQ
STALLRQC
RSTDT
-
-
-
-
EPRST4:0
UENUM
-
-
-
-
-
EPNUM2:0
UEINTX
FIFOCON
NAKINI
RWAL
NAKOUTI
RXSTPI
RXOUTI
STALLEDI
TXINI
Reserved
UDMFN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FNCERR
-
-
page 213
page 213
page 213
page 212
page 211
page 210
page 209
UDFNUMH
UDFNUML
UDADDR
UDIEN
FNUM10:8
FNUM7:0
ADDEN
UADD6:0
-
UPRSME
EORSME
WAKEUPE
EORSTE
SOFE
-
SUSPE
UDINT
-
UPRSMI
EORSMI
WAKEUPI
EORSTI
SOFI
-
SUSPI
UDCON
-
-
-
RPUTX
-
RSTCPU
RMWKUP
DETACH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USBCON
Reserved
Reserved
Reserved
Reserved
Reserved
CLKSTA
CLKSEL1
CLKSEL0
Reserved
UDR1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USBE
-
FRZCLK
-
-
-
-
-
page 195
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXTON
EXCKSEL0
CLKS
-
-
-
RCCKSEL1
EXSUT1
-
-
RCCKSEL0
EXSUT0
-
-
-
EXCKSEL2
EXTE
-
RCON
page 38
page 38
page 37
RCCKSEL3
RCSUT1
-
RCCKSEL2
RCSUT0
-
EXCKSEL3
EXCKSEL1
RCE
-
-
-
-
USART1 I/O Data Register
- USART1 Baud Rate Register High Byte
page 167
page 171
page 171
page 171
page 169
page 168
page 167
UBRR1H
UBRR1L
UCSR1D
UCSR1C
UCSR1B
UCSR1A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
USART1 Baud Rate Register Low Byte
-
-
-
-
-
-
CTSEN
RTSEN
UMSEL11
UMSEL10
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
RXCIE1
TXCIE1
UDRIE1
RXEN1
TXEN1
UCSZ12
RXB81
TXB81
RXC1
TXC1
UDRE1
FE1
DOR1
PE1
U2X1
MPCM1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR1CH
OCR1CL
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter1 - Output Compare Register C High Byte
Timer/Counter1 - Output Compare Register C Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
Timer/Counter1 - Counter Register High Byte
page 135
page 135
page 135
page 135
page 135
page 135
page 135
page 135
page 134
page 134
ICR1L
TCNT1H
TCNT1L
Timer/Counter1 - Counter Register Low Byte
Reserved
TCCR1C
TCCR1B
TCCR1A
Reserved
Reserved
ACMUX
-
-
-
-
-
-
-
-
FOC1A
FOC1B
FOC1C
-
-
-
-
-
page 134
page 133
page 129
ICNC1
ICES1
-
WGM13
WGM12
CS12
CS11
CS10
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CMUX2
CMUX1
CMUX0
page 225
8
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7C)
(0x7B)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TIMSK1
TIMSK0
Reserved
PCMSK1
PCMSK0
EICRB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(0x7A)
-
-
-
-
-
-
-
-
(0x79)
-
-
-
-
-
-
-
-
(0x78)
-
-
-
-
-
-
-
-
(0x77)
-
-
-
-
-
-
-
-
(0x76)
-
-
-
-
-
-
-
-
(0x75)
-
-
-
-
-
-
-
-
(0x74)
-
-
-
-
-
-
-
-
(0x73)
-
-
-
-
-
-
-
-
(0x72)
-
-
-
-
-
-
-
-
-
-
(0x71)
-
-
-
-
-
-
(0x70)
-
-
-
-
-
-
OCIE1B
OCIE0B
-
-
-
(0x6F)
-
-
ICIE1
-
OCIE1C
OCIE1A
OCIE0A
-
TOIE1
TOIE0
-
page 135
page 106
(0x6E)
-
-
-
-
-
(0x6D)
-
-
-
-
PCINT12
PCINT4
ISC60
ISC20
-
-
PCINT11
PCINT3
ISC51
ISC11
-
(0x6C)
-
PCINT7
ISC71
ISC31
-
-
PCINT6
ISC70
ISC30
-
-
PCINT5
ISC61
ISC21
-
PCINT10
PCINT2
ISC50
ISC10
-
PCINT9
PCINT1
ISC41
ISC01
PCIE1
-
PCINT8
PCINT0
ISC40
ISC00
PCIE0
-
page 87
page 87
page 85
page 84
page 86
(0x6B)
(0x6A)
(0x69)
EICRA
(0x68)
PCICR
(0x67)
Reserved
OSCCAL
PRR1
-
-
-
-
-
-
(0x66)
Oscillator Calibration Register
page 38
page 46
page 46
page 196
page 57
page 39
page 56
page 9
(0x65)
PRUSB
-
-
-
-
-
-
PRUSART1
(0x64)
PRR0
-
-
PRTIM0
-
PRTIM1
PRSPI
-
-
(0x63)
REGCR
WDTCKD
CLKPR
WDTCSR
SREG
-
-
-
-
-
-
-
REGDIS
(0x62)
-
-
WDEWIFCM
WCLKD2
WDEWIF
WDEWIE
WCLKD1
WCLKD0
(0x61)
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
(0x60)
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
I
T
H
S
V
N
Z
C
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
page 12
page 12
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PGERS
-
-
SPMEN
-
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
page 242
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WDRF
SM2
-
-
BORF
SM1
-
IVSEL
EXTRF
SM0
-
IVCE
PORF
SE
page 65, 82
page 55
USBRF
-
-
page 45
Reserved
DWDR
-
debugWIRE Data Register
page 245
page 224
ACSR
ACD
-
ACBG
-
ACO
-
ACI
-
ACIE
-
ACIC
-
ACIS1
-
ACIS0
-
Reserved
SPDR
SPI Data Register
-
page 147
page 146
page 145
page 24
page 24
page 40
page 106
page 106
page 106
page 105
page 105
page 89
page 20
page 20
page 20
page 21
page 25
page 86
page 86
page 86
SPSR
SPIF
SPIE
WCOL
SPE
-
-
-
-
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
CPHA
SPR1
GPIOR2
GPIOR1
PLLCSR
OCR0B
OCR0A
TCNT0
General Purpose I/O Register 2
General Purpose I/O Register 1
-
-
-
PLLP2
PLLP1
PLLP0
PLLE
PLOCK
Timer/Counter0 Output Compare Register B
Timer/Counter0 Output Compare Register A
Timer/Counter0 (8 Bit)
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
FOC0A
COM0A1
TSM
FOC0B
-
-
WGM02
CS02
CS01
CS00
COM0A0
COM0B1
COM0B0
-
-
-
-
WGM01
PSRASY
WGM00
-
-
-
-
-
-
PSRSYNC
-
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
EEPROM Data Register
EEDR
EECR
-
-
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
GPIOR0
EIMSK
General Purpose I/O Register 0
INT7
INTF7
-
INT6
INTF6
-
INT5
INTF5
-
INT4
INTF4
-
INT3
INTF3
-
INT2
INTF2
-
INT1
INTF1
PCIF1
INT0
INTF0
PCIF0
EIFR
PCIFR
9
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
Reserved
Reserved
Reserved
Reserved
TIFR1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICF1
-
OCF1C
OCF1B
OCF1A
TOV1
page 136
page 107
TIFR0
-
-
-
-
-
OCF0B
OCF0A
TOV0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTD
DDRD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
-
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
-
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
-
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
-
PORTD3
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
-
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
-
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
-
page 83
page 83
page 83
page 82
page 82
page 82
page 82
page 82
page 82
DDD3
PIND
PIND3
PORTC
DDRC
-
-
PINC
-
PORTB
DDRB
PORTB3
DDB3
PINB
PINB3
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Moreover reserved bits are not
guaranteed to be read as “0”. Reserved I/O memory addresses should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O reg-
isters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega8U2/16U2/32U2 is
a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for
the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
10
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
7. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
Indirect Jump to (Z)
PC ← PC + k + 1
PC ← Z
None
None
None
None
None
None
None
I
2
2
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
4
PC ← Z
4
k
Direct Subroutine Call
Subroutine Return
PC ← k
5
PC ← STACK
5
RETI
Interrupt Return
PC ← STACK
5
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
P,b
P,b
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
I/O(P,b) ← 0
None
None
2
2
1
1
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Z,C,N,V
Logical Shift Right
11
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd
Rd
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
s
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd ← (X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
None
None
None
None
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
12
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
8. Ordering Information
8.1
ATmega8U2
Speed
Power Supply
Ordering Code
ATmega8U2-AU
ATmega8U2-MU
Package
Operational Range
32A
16 MHz
2.7 - 5.5V
-40°C to +85°C
32M1-A
Package Type
32A
32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package
32-pad, 5 x 5 x 1 mm body, pad pitch 0.50 mm Quad Flat No lead (QFN)
32M1
13
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
8.2
ATmega16U2
Speed
Power Supply
Ordering Code
ATmega16U2-AU
ATmega16U2-MU
Package
Operational Range
32A
16 MHz
2.7 - 5.5V
-40°C to +85°C
32M1-A
Package Type
32A
32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package
32-pad, 5 x 5 x 1 mm body, pad pitch 0.50 mm Quad Flat No lead (QFN)
32M1
14
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
8.3
ATmega32U2
Speed
Power Supply
Ordering Code
ATmega32U2-AU
ATmega32U2-MU
Package
Operational Range
32A
16 MHz
2.7 - 5.5V
-40°C to +85°C
32M1-A
Package Type
32A
32-lead, 7 x7 x 1.2 mm, lead pitch 0.8 mm Thin Quad Flat Package
32-pad, 5 x 5 x 1 mm body, pad pitch 0.50 mm Quad Flat No lead (QFN)
32M1
15
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
9. Packaging Information
9.1
QFN32
16
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
9.2
TQFP32
17
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
10. Errata
10.1 Errata ATmega8U2
The revision letter in this section refers to the revision of the ATmega8U2 device.
10.1.1
rev. A and rev B
• Full Swing oscillator
1. Full Swing oscillator
The maximum frequency for the Full Swing Crystal Oscillator is 8MHz. For Crystal frequen-
cies > 8MHz the Full Swing Crystal Oscillator is not guaranteed to operate correctly.
Problem fix/Workaround
If a Crystal with frequency > 8MHz is used, the Low Power Crystal Oscillator option should
be used instead. See table 8-1 for an overview of the Device Clocking Options. Note that the
Low Power Crystal Oscillator will not provide full rail-to-rail swing on the XTAL2 pin. If sys-
tem clock output is needed to drive other clock inputs while running from the Low Power
Crystal Oscillator, the system clock can be output on PORTC7 by programming the CKOUT
fuse.
10.2 Errata ATmega16U2
The revision letter in this section refers to the revision of the ATmega16U2 device.
10.2.1
rev. A and rev B
• Full Swing oscillator
1. Full Swing oscillator
The maximum frequency for the Full Swing Crystal Oscillator is 8MHz. For Crystal frequen-
cies > 8MHz the Full Swing Crystal Oscillator is not guaranteed to operate correctly.
Problem fix/Workaround
If a Crystal with frequency > 8MHz is used, the Low Power Crystal Oscillator option should
be used instead. See table 8-1 for an overview of the Device Clocking Options. Note that the
Low Power Crystal Oscillator will not provide full rail-to-rail swing on the XTAL2 pin. If sys-
tem clock output is needed to drive other clock inputs while running from the Low Power
Crystal Oscillator, the system clock can be output on PORTC7 by programming the CKOUT
fuse.
10.3 Errata ATmega32U2
The revision letter in this section refers to the revision of the ATmega32U2 device.
10.3.1
rev. C
No Known Errata
18
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
10.3.2
rev. A and rev B
• Full Swing oscillator
1. Full Swing oscillator
The maximum frequency for the Full Swing Crystal Oscillator is 8MHz. For Crystal frequen-
cies > 8MHz the Full Swing Crystal Oscillator is not guaranteed to operate correctly.
Problem fix/Workaround
If a Crystal with frequency > 8MHz is used, the Low Power Crystal Oscillator option should
be used instead. See table 8-1 for an overview of the Device Clocking Options. Note that the
Low Power Crystal Oscillator will not provide full rail-to-rail swing on the XTAL2 pin. If sys-
tem clock output is needed to drive other clock inputs while running from the Low Power
Crystal Oscillator, the system clock can be output on PORTC7 by programming the CKOUT
fuse.
19
7799CS–AVR–12/09
ATmega8U2/16U2/32U2
11. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
11.1 Rev. 7799C – 12/09
1.
Updated “Features” on page 1.
2.
3.
4.
5.
6.
7.
8.
9.
Added description of “AVCC” on page 4.
Updated Figure 7-2 on page 18.
Updated Figure 20-3 on page 186 and Figure 20-4 on page 187.
Updated “Fuse Bits” on page 247.
Updated “DC Characteristics” on page 264.
Updated Table 26-3 on page 267, by removing Vrst.
Updated Table 26-4 on page 268.
Updated “Typical Characteristics” on page 273.
10. Added new “Errata” on page 299.
11.2 Rev. 7799B – 06/09
1.
Updated “Typical Characteristics” on page 273.
11.3 Rev. 7799A – 03/09
1.
Initial revision.
20
7799CS–AVR–12/09
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