ATF1508ASV-15QI160 [ATMEL]
Highperformance EE PLD; 高性能EE PLD
| 型号： | ATF1508ASV-15QI160 |
| 厂家： | 
ATMEL |
| 描述： | Highperformance EE PLD |
| 文件： | 总22页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
• Flexible Logic Macrocell
High-
performance
EE PLD
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
• Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
ATF1508ASV
ATF1508ASVL
• Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent-latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 1408E–09/00
84-lead PLCC
Top View
100-lead TQFP
Top View
I/O/PD1 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
73 I/O
74 GND
73 I/O/TDO
72 I/O
72 GND
71 I/O/TDO
70 I/O
VCCIO
I/O/TDI
I/O
I/O 16
71 I/O
I/O
70 I/O
I/O 17
69 I/O
I/O
69 I/O
I/O 18
68 I/O
I/O
68 I/O
GND 19
I/O 20
67 I/O
I/O
67 I/O
66 VCCIO
65 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
I/O 21
I/O 22
64 I/O
64 I/O
I/O/TMS 23
I/O 24
63 I/O
I/O 13
63 I/O
62 I/O/TCK
61 I/O
I/O 14
62 I/O/TCK
61 I/O
I/O 25
I/O/TMS 15
I/O 16
VCCIO 26
I/O 27
60 I/O
60 I/O
59 GND
58 I/O
I/O 17
59 GND
58 I/O
I/O 28
VCCIO 18
I/O 19
I/O 29
57 I/O
57 I/O
I/O 20
56 I/O
I/O 30
56 I/O
I/O 21
55 I/O
I/O 31
55 I/O
I/O 22
54 I/O
GND 32
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
100-lead PQFP
Top View
160-lead PQFP
Top View
N/C
N/C
1
2
3
4
5
6
7
8
9
120 N/C
119 N/C
118 N/C
117 N/C
116 N/C
115 N/C
114 N/C
113 GND
112 I/O/TDO
111 I/O
110 I/O
109 I/O
108 I/O
107 I/O
106 I/O
105 I/O
104 VCCIO
103 I/O
102 I/O
101 I/O
100 I/O
99 I/O/TCK
98 I/O
I/O
1
2
3
4
5
6
7
8
9
80 I/O
N/C
I/O
I/O/PD1
I/O
79 I/O
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 I/O
73 I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
53 VCCIO
52 I/O
51 I/O
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
VCCIO
I/O/TDI
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
GND 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O/TMS 22
I/O 23
I/O 24
I/O 25
VCCIO 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
N/C 34
N/C 35
N/C 36
N/C 37
N/C 38
N/C 39
N/C 40
I/O
I/O
I/O 10
I/O 11
I/O 12
GND 13
I/O 14
I/O 15
I/O 16
I/O/TMS 17
I/O 18
I/O 19
97 I/O
VCCIO 20
I/O 21
96 I/O
95 GND
94 I/O
I/O 22
93 I/O
I/O 23
92 I/O
I/O 24
91 I/O
I/O 25
90 I/O
I/O 26
89 I/O
I/O 27
88 I/O
GND 28
I/O 29
87 N/C
86 N/C
85 N/C
84 N/C
83 N/C
82 N/C
81 N/C
I/O 30
ATF1508ASV(L)
2
ATF1508ASV(L)
Block Diagram
6 to 12
3
Description
The ATF1508ASV(L) is a high-performance, high-density
complex programmable logic device (CPLD) that utilizes
Atmel’s proven electrically-erasable technology. With 128
logic macrocells and up to 100 inputs, it easily integrates
logic from several TTL, SSI, MSI, LSI and classic PLDs.
The ATF1508ASV(L)’s enhanced routing switch matrices
increase usable gate count and increase odds of success-
ful pin-locked design modifications.
Product Terms and Select Mux
Each ATF1508ASV(L) macrocell has five product terms.
Each product term receives as its inputs all signals from
both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
The ATF1508ASV(L) has up to 96 bi-directional I/O pins
and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can also
serve as a global control signal, register clock, register
reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
OR/XOR/CASCADE Logic
The ATF1508ASV(L)’s logic structure is designed to effi-
ciently support all types of logic. Within a single macrocell,
all the product terms can be routed to the OR gate, creating
a 5-input AND/OR sum term. With the addition of the
CASIN from neighboring macrocells, this can be expanded
to as many as 40 product terms with little additional delay.
Each of the 128 macrocells generates a buried feedback
that goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term that
goes to a regional bus. Cascade logic between macrocells
in the ATF1508ASV(L) allows fast, efficient generation of
complex logic functions. The ATF1508ASV(L) contains
eight such logic chains, each capable of creating sum term
logic with a fan-in of up to 40 product terms.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high- or low-level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
The ATF1508ASV(L) macrocell, shown in Figure 1, is flexi-
ble enough to support highly-complex logic functions oper-
ating at high-speed. The macrocell consists of five
sections: product terms and product term select multi-
plexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
Flip-flop
The ATF1508ASV(L)’s flip-flop has very flexible data and
control functions. The data input can come from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows cre-
ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and
SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
Unused macrocells are automatically disabled by the com-
piler to decrease power consumption. A security fuse,
when programmed, protects the contents of the
ATF1508ASV(L). Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the security fuse.
The clock itself can either be the Global CLK Signal (GCK)
or an individual product term. The flip-flop changes state on
the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip-flop’s asynchronous reset
signal (AR) can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset
(AP) can be a product term or always off.
The ATF1508ASV(L) device is an in-system programmable
(ISP) device. It uses the industry-standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
ATF1508ASV(L)
4
ATF1508ASV(L)
Figure 1. ATF1508ASV(L) Macrocell
Output Select and Enable
The switch matrix in each logic block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals can be selected as inputs to the logic
block.
The ATF1508ASV(L) macrocell output can be selected as
registered or combinatorial. The buried feedback signal can
be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
Foldback Bus
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration. all the macrocell resources are still available,
including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be
selected as one of the global OUTPUT enable signals. The
device has six global OE signals.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
Open-collector Output Option
This option enables the device output to provide control
signals such as an interrupt that can be asserted by any of
the several devices.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 128 macrocells.
5
Programmable Pin-keeper Option for
Inputs and I/Os
I/O Diagram
The ATF1508ASV(L) offers the option of programming all
input and I/O pins so that “pin-keeper” circuits can be uti-
lized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-
level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Input Diagram
All ATF1508 also have an optional power-down mode. In
this mode, current drops to below 10 mA. When the power-
down option is selected, either PD1 or PD2 pins (or both)
can be used to power down the part. The power-down
option is selected in the design source file. When enabled,
the device goes into power-down when either PD1 or PD2
is high. In the power-down mode, all internal logic signals
are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power-down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate bur-
ied foldback and cascade logic signals.
Speed/Power Management
The ATF1508ASV(L) has several built-in speed and power
management features. The ATF1508ASV(L) contains cir-
cuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This
not only reduces power consumption during inactive peri-
ods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
All power-down AC characteristic parameters are com-
puted from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder,
tRPA, must be added to the AC parameters, which include
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
To further reduce power, each ATF1508ASV(L) macrocell
has a reduced-power bit feature. This feature allows indi-
vidual macrocells to be configured for maximum power-
savings. This feature may be selected as a design option.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
ATF1508ASV(L)
6
ATF1508ASV(L)
fuse verify is inhibited. However, User Signature and
device ID remains accessible.
Design Software Support
ATF1508ASV(L) designs are supported by several third-
party tools. Automated fitters allow logic synthesis using a
variety of high-level description languages and formats.
Programming
ATF1508ASV(L) devices are in-system programmable
(ISP) devices utilizing the 4-pin JTAG protocol. This capa-
bility eliminates package handling normally required for
programming and facilitates rapid design iterations and
field changes.
Power-up Reset
The ATF1508ASV is designed with a power-up reset, a
feature critical for state machine initialization. At a point
delayed slightly from VCC crossing VRST, all registers will be
initialized, and the state of each output will depend on the
polarity of its buffer. However, due to the asynchronous
nature of reset and uncertainty of how VCC actually rises in
the system, the following conditions are required:
Atmel provides ISP hardware and software to allow pro-
gramming of the ATF1508ASV(L) via the PC. ISP is per-
formed by using either a download cable, a comparable
board tester or a simple microprocessor interface.
To allow ISP programming support by the Automated Test
Equipment (ATE) vendors, Serial Vector Format (SVF) files
can be created by the Atmel ISP software. Conversion to
other ATE tester format beside SVF is also possible
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin
high, and,
ATF1508ASV(L) devices can also be programmed using
standard third-party programmers. With third-party pro-
grammer, the JTAG ISP port can be disabled thereby
allowing four additional I/O pins to be used for logic.
3. The clock must remain stable during TD.
The ATF1508ASV has two options for the hysteresis about
the reset level, VRST, Small and Large. To ensure a robust
operating environment in applications where the device is
operated near 3.0V, Atmel recommends that during the fit-
ting process users configure the device with the Power-up
Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on
the command line after “filename.POF”. To allow the regis-
ters to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
Contact your local Atmel representatives or Atmel PLD
applications for details.
ISP Programming Protection
The ATF1508ASV(L) has a special feature that locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condi-
tion. In addition the pin-keeper option preserves the former
state during device programming.
4. If VCC falls below 2.0V, it must shut off com-
pletely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced
by several hundred microamps as well.
All ATF1508ASV(L) devices are initially shipped in the
erased state thereby making them ready to use for ISP.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1508ASV(L) fuse patterns. Once programmed,
Note:
For more information refer to the “Designing for In-Sys-
tem Programmability with Atmel CPLDs” application
note.
7
DC and AC Operating Conditions
Commercial
0°C - 70°C
3.0V - 3.6V
Industrial
-40°C - 85°C
3.0V - 3.6V
Operating Temperature (Ambient)
VCC (3.3V) Power Supply
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
VIN = VCC
-2
-10
10
µA
Input or I/O High
Leakage Current
IIH
2
µA
µA
Tri-State Output
Off-State Current
IOZ
VO = VCC or GND
-40
40
Com.
Ind.
115
135
5
mA
mA
µA
Std Mode
Power Supply
Current, Standby
VCC = Max
IN = 0, VCC
ICC1
V
Com.
Ind.
“L” Mode
“PD” Mode
Std Mode
5
µA
Power Supply Current,
Power-down Mode
VCC = Max
IN = 0, VCC
ICC2
0.1
5
mA
V
Com.
Ind.
60
80
mA
mA
V
Reduced-power Mode
Supply Current, Standby
VCC = Max
(2)
ICC3
VIN = 0, VCC
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
1.7
0.8
VCCIO + 0.3
0.45
V
Com.
Ind.
V
VIN = VIH or VIL
Output Low Voltage (TTL)
VCC = Min, IOL = 8 mA
0.45
V
VOL
Com.
Ind.
0.2
V
VIN = VIH or VIL
Output Low Voltage (CMOS)
VCC = Min, IOL = 0.1 mA
0.2
V
Output High Voltage
– 3.3V (TTL)
VIN = VIH or VIL
VCC = Min, IOH = -2.0 mA
2.4
V
V
VOH
Output High Voltage
– 3.3V (CMOS)
VIN = VIH or VIL
VCCIO = Min, IOH = -0.1 mA
V
CCIO - 0.2
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
Pin Capacitance
Typ
Max
8
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
pF
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin
during programming) has a maximum capacitance of 12 pF.
ATF1508ASV(L)
8
ATF1508ASV(L)
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Timing Model
U
9
AC Characteristics(1)
-15
-20
Symbol
tPD1
tPD2
tSU
Parameter
Min
3
Max
15
Min
Max
20
Units
ns
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
3
12
16
ns
11
0
13.5
0
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
3
3
ns
1.0
2.0
MHz
ns
9
12
5
5
5
4
6
6
7
4
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
fCNT
tACNT
fACNT
fMAX
tIN
Array Clock Output Delay
Array Clock High Time
15
18.5
ns
6
6
8
8
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
13
13
17
17
ns
76.9
66
MHz
ns
76.9
100
58.8
83.3
MHz
MHz
ns
2
2
2.5
2.5
2
tIO
ns
tFIN
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Foldback Term Delay
8
10
1
ns
Cascade Logic Delay
1
ns
Logic Array Delay
6
8
ns
Logic Control Delay
3.5
3
4.5
3
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
tOD1
tOD2
tOD3
tZX1
3
3
5
7
4
4
6
9
ns
ns
ns
(Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF)
ATF1508ASV(L)
10
ATF1508ASV(L)
AC Characteristics(1) (Continued)
-15
-20
Symbol
Parameter
Min
Max
Min
Max
Units
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
tZX2
7
9
ns
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF)
tZX3
tXZ
10
6
11
7
ns
ns
Output Buffer Disable Delay
(CL = 5 pF)
tSU
Register Setup Time
Register Hold Time
5
4
2
2
6
5
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
2
2
2.5
3
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
6
7
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
6
7
tGLOB
tPRE
tCLR
tUIM
tRPA
2
3
4
5
4
5
2
2.5
13
Reduced-Power Adder(2)
10
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
Input Test Waveforms and
Measurement Levels
Output AC Test Loads
3.0V
703
8060
tR, tF = 1.5 ns typical
11
Power-down Mode
The ATF1508ASV(L) includes two pins for optional pin-
controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the
PD1 and PD2 pin is high, the device supply current is
reduced to less than 5 mA. During power-down, all output
data and internal logic states are latched and held. There-
fore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset
will remain at high-Z. During power-down, all input signals
except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to
indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD
pin logic array input. However, buried logic resources in
this macrocell may still be used.
Power Down AC Characteristics(1)(2)
-15
-20
Symbol Parameter
Min
15
Max
Min
20
Max
Units
ns
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
15
20
ns
15
20
ns
25
25
25
1
30
30
30
1
ns
ns
ns
µs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
µs
1
1
µs
1
1
µs
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
ATF1508ASV(L)
12
ATF1508ASV(L)
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
(BST) capture registers. Input to the capture register chain
is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device
and to load data into the update registers. Control signals
are generated internally by the JTAG TAP controller. The
BSC configuration for the input and I/O pins and macrocells
are shown below.
JTAG-BST Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled
by the Test Access Port (TAP) controller in the
ATF1508ASV(L). The boundary-scan technique involves
the inclusion of a shift-register stage (contained in a bound-
ary-scan cell) adjacent to each component so that signals
at component boundaries can be controlled and observed
using scan testing principles. Each input pin and I/O pin
has its own Boundary-scan Cell (BSC) in order to support
boundary-scan testing. The ATF1508ASV(L) does not cur-
rently include a Test Reset (TRST) input pin because the
TAP controller is automatically reset at power-up. The six
JTAG-BST modes supported include: SAMPLE/PRE-
LOAD, EXTEST, BYPASS and IDCODE. BST on the
ATF1508ASV(L) is implemented using the Boundary-scan
Definition Language (BSDL) described in the JTAG specifi-
cation (IEEE Standard 1149.1). Any third-party tool that
supports the BSDL format can be used to perform BST on
the ATF1508ASV(L).
BSC Configuration Pins and
Macrocells (Except JTAG TAP Pins)
The ATF1508ASV(L) also has the option of using four
JTAG-standard I/O pins for in-system programming (ISP).
The ATF1508ASV(L) is programmable through the four
JTAG pins using programming-compatible with the IEEE
JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG
ISP interface. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
Note:
The ATF1508ASV(L) has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
JTAG Boundary-scan Cell (BSC)
Testing
Boundary-scan Definition Language
(BSDL) Models for the ATF1508
These are now available in all package types via the Atmel
web site. These models can be used for Boundary-scan
Test Operation in the ATF1508ASV(L) and have been
scheduled to conform to the IEEE 1149.1 standard.
The ATF1508ASV(L) contains up to 96 I/O pins and four
input pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundary-
scan cell (BSC) in order to support boundary-scan testing
as described in detail by IEEE Standard 1149.1. A typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
13
BSC Configuration for Macrocell
Pin BSC
TDO
0
DQ
Pin
1
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
1
0
D Q
D Q
1
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
ATF1508ASV(L)
14
ATF1508ASV(L)
ATF1508ASV(L) Dedicated Pinouts
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
84-lead J-lead
100-lead PQFP
100-lead TQFP
160-lead PQFP
2
1
92
91
90
89
87
3,43
6
90
89
88
87
85
1,41
4
142
141
140
139
137
63,159
9
84
INPUT/GCLK1
I/O/GCLK3
83
81
I/O/PD (1, 2)
12,45
14
I/O/TDI(JTAG)
I/O/TMS(JTAG)
I/O/TCK(JTAG)
I/O/TDO(JTAG)
23
17
64
75
15
62
73
22
62
99
71
112
7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
GND
VCC
3,13,26,38,
43,53,66,78
5,20,36,41,
53,68,84,93
3,18,34,39,
51,66,82,91
8,26,55,61,79,104,133,143
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
N/C
-
-
-
# of SIGNAL PINS
68
84
80
84
80
100
96
# USER I/O PINS
OE (1, 2)
64
Global OE pins
Global Clear pin
Global Clock pins
Power-down pins
GCLR
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for boundary-scan testing or in-system programming
Ground pins
VCC
VCC pins for the device
15
ATF1508ASV(L) I/O Pinouts
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
1
PLB
A
MC
33
PLB
C
-
-
4
-
2
-
160
-
-
-
27
-
25
-
41
-
2
A
34
C
A/
PD1
3
12
3
1
159
35
C
31
26
24
33
4
5
A
A
A
A
A
A
A
A
A
A
A
A
-
11
10
-
-
2
-
100
99
-
158
153
152
-
36
37
38
39
40
41
42
43
44
45
46
47
C
C
C
C
C
C
C
C
C
C
C
C
-
30
29
-
-
-
32
31
30
-
25
24
-
23
22
-
6
1
7
-
8
9
-
100
99
-
98
97
-
151
150
-
28
-
23
22
-
21
20
-
29
28
-
9
10
11
12
13
14
15
-
-
8
-
98
-
96
-
149
147
146
145
-
27
-
21
-
19
-
27
25
24
23
-
6
5
-
96
95
-
94
93
-
25
24
-
19
18
-
17
16
-
C/
TMS
16
A
4
94
92
144
48
23
17
15
22
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
22
-
16
-
14
-
21
-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
41
-
39
-
37
-
59
-
21
-
15
-
13
-
20
19
18
16
-
40
-
38
-
36
-
58
57
56
54
-
20
-
14
12
-
12
10
-
39
-
37
35
-
35
33
-
-
-
18
17
-
11
10
-
9
15
14
-
37
36
-
34
33
-
32
31
-
53
52
-
8
-
16
-
9
7
13
12
11
10
-
35
-
32
-
30
-
51
50
49
48
-
-
-
15
-
8
6
34
-
31
30
-
29
28
-
7
5
-
-
-
-
B/
TDI
32
14
6
4
9
64
D
33
29
27
43
65
66
E
E
44
-
42
-
40
-
62
-
97
98
G
G
63
-
65
-
63
-
100
-
ATF1508ASV(L)
16
ATF1508ASV(L)
ATF1508ASV(L) I/O Pinouts (Continued)
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
MC
PLB
E/
PD2
67
45
43
41
63
99
G
64
66
64
101
68
69
70
71
72
73
74
75
76
77
78
79
E
E
E
E
E
E
E
E
E
E
E
E
-
46
-
-
-
64
65
67
-
100
101
102
103
104
105
106
107
108
109
110
111
G
G
G
G
G
G
G
G
G
G
G
G
-
65
-
-
-
102
103
105
-
44
46
-
42
44
-
67
69
-
65
67
-
-
-
48
49
-
47
48
-
45
46
-
68
69
-
67
68
-
70
71
-
68
69
-
106
107
-
50
-
49
-
47
-
70
71
72
73
-
69
-
72
-
70
-
108
109
110
111
-
51
-
50
51
-
48
49
-
70
-
73
74
-
71
72
-
-
-
G/
TDO
80
E
52
52
50
78
112
71
75
73
112
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
-
-
54
-
52
-
80
-
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
-
77
-
75
-
121
-
54
-
55
-
53
-
88
89
90
91
-
73
-
78
-
76
-
122
123
128
129
-
55
56
-
56
57
-
54
55
-
74
75
-
79
80
-
77
78
-
57
-
58
59
-
56
57
-
92
93
-
76
-
81
82
-
79
80
-
130
131
-
-
-
58
-
60
-
58
-
94
96
97
98
-
77
-
83
-
81
-
132
134
135
136
-
60
61
-
62
63
-
60
61
-
79
80
-
85
86
-
83
84
-
F/
TCK
H/
GCLK3
96
62
64
62
99
128
81
87
85
137
17
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
200
100
0
800
700
600
500
400
STANDARD POWER
STANDARD & REDUCED POWER MODE
REDUCED POWER
2.50
2.75
3.00
3.25
3.50
3.75
4.00
2.50
2.75
3.00
3.25
3.50
3.75
4.00
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
250.0
200.0
150.0
100.0
50.0
125.0
100.0
75.0
50.0
25.0
0.0
STANDARD POWER
STANDARD POWER
REDUCED POWER
REDUCED POWER MODE
0.0
0.00
0.00
5.00
10.00
15.00
20.00
20.00
40.00
60.00
80.00
100.00
FREQUENCY (MHz)
FREQUENCY (MHz)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW POWER ("L") MODE
(TA = 25°C, F = 0)
10
9
8
7
6
5
4
3
2
1
0
2.50
2.75
3.00
3.25
3.50
3.75
4.00
SUPPLY VOLTAGE (V)
ATF1508ASV(L)
18
ATF1508ASV(L)
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V,TA = 25°C)
0
-2
10
0
-4
-10
-20
-30
-40
-50
-60
-70
-6
-8
-10
-12
-14
-16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.75
3.00
3.25
3.50
3.75
4.00
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
100
80
60
40
20
0
40
35
30
25
20
0
0.5
1
1.5
2
2.5
3
3.5
4
2.75
3.00
3.25
3.50
3.75
4.00
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT CURRENT vs. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
15
10
5
0
-20
-40
0
-60
-5
-80
-100
-10
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0
0.5
1
1.5
2
2.5
3
3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
19
ATF1508ASV(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
15
8
8
100
ATF1508ASV-15 JC84
ATF1508ASV-15 QC100
ATF1508ASV-15 AC100
ATF1508ASV-15 QC160
84J
Commercial
100Q
100A
160Q
(0°C to 70°C)
100
ATF1508ASV-15 JI84
ATF1508ASV-15 QI100
ATF1508ASV-15 AI100
ATF1508ASV-15 QI160
84J
Industrial
100Q
100A
160Q
(-40°C to +85°C)
20
12
12
83.3
83.3
ATF1508ASVL-20 JC84
ATF1508ASVL-20 QC100
ATF1508ASVL-20 AC100
ATF1508ASVL-20 QC160
84J
Commercial
100Q
100A
160Q
(0°C to 70°C)
ATF1508ASVL-20 JI84
ATF1508ASVL-20 QI100
ATF1508ASVL-20 AI100
ATF1508ASVL-20 QI160
84J
Industrial
100Q
100A
160Q
(-40°C to +85°C)
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q
100A
160Q
100-lead, Plastic Quad Pin Flat Package (PQFP)
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160-lead, Plastic Quad Pin Flat Package (PQFP)
ATF1508ASV(L)
20
ATF1508ASV(L)
Packaging Information
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q, 100-lead, Plastic Gull Wing Quad Flat
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AF
Package (PQFP)
Dimensions in Millimeters and (Inches)
17.44 (0.687)
PIN 1 ID
16.95 (0.667)
20.12 (.792)
19.87 (.782)
0.65 (0.026) BSC
0.41 (0.016)
0.22 (0.009)
23.45 (0.923)
22.95 (0.904)
14.12 (0.556)
13.87 (0.546)
3.40 (.134) MAX
7
0.25 (0.010)
0.10 (0.004)
0
1.03 (0.041)
0.73 (0.028)
0.10 (0.004) MIN
*Controlling dimension: Millimeters
100A, 100-lead, Very Thin (1.0mm) Plastic Gull
Wing Quad Flat Package (TQFP)
160Q, 160-lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Millimeters and (Inches)*
Dimensions in Millimeters and (Inches)
1.238(31.45)
1.218(30.95)
16.25(0.640)
15.75(0.620)
SQ
PIN 1 ID
PIN 1 ID
0.27(0.011)
0.17(0.007)
.016(0.40)
.008(0.20)
.0256(0.65) BSC
0.56(0.022)
0.44(0.018)
1.106(28.10)
1.098(27.90)
1.05(0.041)
0.95(0.037)
14.10(0.555)
13.90(0.547)
SQ
.157(3.97)
.127(3.22)
7
0
0.20(0.008)
0.10(0.004)
.009(0.23)
.004(0.10)
0-7
.037(0.95)
.025(0.65)
0.15(0.006)
0.05(0.002)
.020(0.50)
.002(0.05)
0.75(0.030)
0.45(0.018)
*Controlling dimension: Millimeters
*Controlling dimension: Millimeters
21
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