ATA5749-6DQ [ATMEL]
Fractional-N PLL Transmitter IC; 小数N分频PLL发射器IC
| 型号： | ATA5749-6DQ |
| 厂家： | 
ATMEL |
| 描述： | Fractional-N PLL Transmitter IC |
| 文件： | 总26页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fully Integrated Fractional-N PLL
• ASK and Closed Loop FSK Modulation
• Output Power Up to +12.5 dBm from 300 MHz to 450 MHz
• Current Consumption is Scaled by Output Power Programming
• Fast Crystal Oscillator Start-up Time of Typically 200 µs
• Low Current Consumption of Typically 7.3 mA at 5.5 dBm
• Only One 13.0000 MHz Crystal for 314.1 MHz to 329.5 MHz and 424.5 MHz to 439.9 MHz
Operation
Fractional-N
PLL Transmitter
IC
• Single Ended RF Power Amplifier Output
• Many Software Programmable Options Using SPI:
– Output Power from –0.5 dBm to +12.5 dBm
– RF Frequency from 300 MHz to 450 MHz with Different Crystals
– FSK Deviation with 396 Hz Resolution
– CLK Output Frequency 3.25 MHz or 1.625 MHz
• Data Rate Up to 40 kbit/s (Manchester)
ATA5749
• 4 KV HBM ESD Protection Including XTO
• Operating Temperature Range of –40°C to +125°C
• Supply Voltage Range of 1.9V to 3.6V
• TSSOP10 Package
Preliminary
Benefits
• Robust Crystal Oscillator with Fast Start Up and High Reliability
• Lower Inventory Costs and Reduced Part Number Proliferation
• Longer Battery Lifetime
• Supports Multi-channel Operation
• Wide Tolerance Crystal Possible with PLL Software Compensation
1. Description
The ATA5749 is a fractional-N-PLL transmitter IC for 300 MHz to 450 MHz operation
and is especially targeted for Tire Pressure Sensor Gauges, Remote Keyless Entry,
and Passive Entry and other automotive applications. It operates at data rates up to
40 kbit/s Manchester for ASK and FSK with a typical 5.5 dBm output power at 7.3 mA.
Transmitter parameters such as output power, output frequency, FSK deviation, and
current consumption can be programmed using the SPI interface. This fully integrated
PLL transmitter IC simplifies RF board design and results in very low material costs.
9128D–RKE–01/09
Figure 1-1. Block Diagram
ATA5749
1
2
3
4
5
10
CLK
XTO_RDY
EN
Power
up/down
CLK_DRV
1
XTO Signal
4 or 8
Fractional-N-PLL
CLK_ON
DIV_CNTRL
FSK_mod
9
SDIN_TXDIN
GND
FREQ[0:14]
FSEP[0:7]
Frac.
Div.
Digital
Control
and
433_N315
Registers
ASK_mod
8
SCK
PFD
CP
VS
PWR[0:3]
7
ANT2
XTO1
LP
XTO
(FOX)
PA
6
ANT1
XTO2
VCO
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ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
2. Pin Configuration
Figure 2-1. TSSOP10 Package Pinout
CLK
1
2
3
4
5
10 EN
SDIN_TXDIN
SCK
9
8
7
6
GND
VS
ATA5749
ANT2
XTO1
XTO2
ANT1
Table 2-1.
Pin Description
Symbol
CLK
Pin
1
Function
CLK output
2
SDIN_TXDIN
SCK
Serial bus data input and TX data input
Serial bus clock input
Antenna interface
3
4
ANT2
5
ANT1
Antenna interface
6
XTO2
Crystal/CLOAD2 connection
Crystal/CLOAD1 connection
Supply input
7
XTO1
8
VS
9
GND
Supply GND
10
EN
Enable input
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9128D–RKE–01/09
3. Functional Description
3.1
Fractional-N PLL
The ATA5749 block diagram is shown in Figure 1-1 on page 2. The operation of the PLL is
determined by the contents of a 32-bit configuration register. The 15-bit value FREQ is used with
the 1-bit 434_N315 flag to determine the RF carrier frequency. This results in a user-selectable
frequency step size of 793 Hz (with 13.000 MHz crystal). With this level of resolution, it is possi-
ble to compensate for crystal tolerance by adjusting the value of FREQ accordingly. This
enables the use of lower cost crystals without compromising final accuracy. In addition, software
programming of RF carrier frequency allows this device to be used in some multi-channel
applications.
Modulation type is selected with the 1-bit ASK_NFSK flag. FSK modulation is achieved by mod-
ifying the divider block in the feedback loop. The benefit to this approach is that performance-
reducing RF spurs (common in applications that create FSK by “pulling” the load capacitance in
the crystal oscillator circuit) are completely eliminated. The 8-bit value FSEP establishes the
FSK frequency deviation. It is possible to obtain FSK frequency deviations from ±396 Hz to
±101 KHz in steps of ±396 Hz.
The PLL lock time is 1280/(external crystal frequency) and amounts to 98.46 µs when using a
13.0000 MHz crystal. When added to the crystal oscillator start-up time, a very fast
time-to-transmit is possible (typically 300 µs). This feature extends battery life in applications like
Tire Pressure Monitoring Systems, where the message length is often shorter than 10 ms and
the time “wasted” during start-up and settling time becomes more significant.
3.2
Selecting the RF Carrier Frequency
The fractional divider can be programmed to generate an RF output frequency fRF according to
the formulas shown in Table 3-1. Note that in the case of fRF ASK, the FSEP/2 value is rounded
down to the next integer value if FSEP is an odd number.
Table 3-1.
RF Output Parameter Formulas
RF Output Parameter
S434_N315 = LOW
S434_N315 = HIGH
fRF_FSK_LOW
(24 + (FREQ + 0.5)/16384) × fXTO
(32.5 + (FREQ + 0.5)/16384) × fXTO
(24 + (FREQ + FSEP + 0.5)/16384)
(32.5 + (FREQ + FSEP + 0.5)/16384)
fRF_FSK_HIGH
fDEV__FSK
fRF ASK
× fXTO
× fXTO
FSEP/32768 × fXTO
FSEP/32768 × fXTO
(24 + (FREQ + FSEP/2 + 0.5)/16384) (32.5 + (FREQ + FSEP/2 + 0.5)/16384)
× fXTO × fXTO
FSEP can take on the values of 1 to 255. Using a 13.000 MHz crystal, the range of frequency
deviation fDEV_FSK is programmable from ±396 Hz to ±101.16 kHz in steps of ±396 Hz. For
example, with FSEP = 100 the output frequency is FSK modulated with fDEV_FSK = ±39.6 kHz.
FREQ can take values in the range of values 2500 and 22000. Using a 13.0000 MHz crystal, the
output frequency fRF can be programmed to 315 MHz by setting FREQ[0:14] = 3730,
FSEP[0:7] = 100 and S434_N315 = 0. By setting FREQ[0:14] = 14342, FSEP[0:7] = 100 and
S434_N315 = 1, 433.92 MHz can be realized.
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ATA5749 [Preliminary]
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ATA5749 [Preliminary]
The PA is enabled when the PLL is locked and the configuration register programming is com-
pleted. Upon enabling PA at FSK-mode, the RF output power will be switched on. At ASK mode,
the input signal must be additionally set high for RF at output pins. The output power is user pro-
grammable from –0.5 dBm to +12.5 dBm in steps of approximately 1 dB. Changing the output
power requirements, you also modify the current consumption. This gives the user the option to
optimize system performance (RF link budget versus battery life). The PA is implemented as a
Class-C amplifier, which uses an open-collector output to deliver a current pulse that is nearly
independent from supply voltage and temperature. The working principle is shown in Figure 3-1.
Figure 3-1. Class C Power Amplifier Output
VANT1
VS
IANT2
IPulse = (PWR[0:3])
VS
VANT1
L1
Power Meter
ANT1
5
C2
IANT2
50Ω
ZLOPT
ANT2
4
The peak value of this current pulse IPulse is calibrated during ATA5749 production to about
±20%, which corresponds to about 1.5 dB variation in output power for a given power setting
under typical conditions. The actual value of IPulse can be programmed with the 4-bit value in
PWR. This allows the user to scale both the output power and current consumption to optimal
levels.
ASK modulation is achieved by using the SDIN_TXDIN signal where a HIGH on this pin corre-
sponds to RF carrier “ON” and a LOW corresponds to RF “OFF”. FSK uses the same signal path
but HIGH switch on the upper FSK-frequency.
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3.3
Crystal Oscillator
The crystal oscillator (XTO) is an amplitude-regulated Pierce oscillator. It has fixed function and
is not programmable. The oscillator is enabled when the EN is “set”. After the oscillator’s output
amplitude reaches an acceptable level, the XTO_RDY flag is “set”. The CLK-pin becomes active
if CLK_ON is set. The PLL receives its reference frequency.
Typically, this process takes about 200 µs when using a small sized crystal with a motional
capacitance of 4 fF. This start-up time strongly depends on the motional capacitance of the crys-
tal and is lower with higher motional capacitance.
The high negative starting impedance of RXTO12_START > 1500Ω is important to minimize the fail-
ure rate due to the “sleeping crystal” phenomena (more common among very small sized
3.2 mm × 2.5 mm crystals).
3.4
Clock Driver
The clock driver block shown in Figure 1-1 on page 2 is programmed using the CLK_ONLY,
CLK_ON, and DIV_CNTRL bits in the configuration register. When CLK_ONLY is “clear”, normal
operation is selected and the fractional-N PLL is operating. When CLK_ON is “set”, the CLK out-
put is enabled. The crystal clock divider ratio can be set to divide by 4 when DIV_CNTRL is “set”
and divide by 8 when DIV_CNTRL is “clear”. With a 13.0000 MHz crystal, this yields an output of
3.25 MHz or 1.625 MHz, respectively. When CLK_ON is “clear”, no clock is available at CLK and
the transmitter has less current consumption.
The CLK signal can be used to clock a microcontroller. It is CMOS compatible and can drive up
to 20 pF of load capacitance at 1.625 MHz and up to 10 pF at 3.25 MHz. When the device is in
power-down mode, the CLK output stays low. Upon power up, CLK output remains low until the
amplitude detector of the crystal oscillator detects sufficient amplitude and XTO_RDY and
CLK_ON are “set”. After this takes place, CLK output becomes active. The CLK output is syn-
chronized with the XTO_RDY signal so that the first period of the CLK output is always a full
period (no CLK output spike at activation).
To lower overall current consumption, it is possible to power down the entire chip except for the
crystal oscillator block. This can be achieved when the CLK_ONLY is “set”.
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ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
4. Application
4.1
Typical Application
Figure 4-1. Typical Application Circuit
IO1
ATA5749
1
10
CLK
XTO_RDY
EN
Power
up/down
CLK_DRV
CLK
Micro-
1
XTO Signal
controller
4 or 8
IO2
Fractional-N-PLL
CLK_ON
DIV_CNTRL
FSK_mod
IO3
2
9
8
7
6
GND
FREQ[0:14]
SDIN_TXDIN
FSEP[0:7]
Frac.
Div.
Digital
C6
Control
and
433_N315
Registers
3
ASK_mod
SCK
PFD
CP
VS
PWR[0:3]
VS
C3
C4
4
ANT2
XTO1
Loop
antenna
LP
XTAL
XTO
(FOX)
5
PA
ANT1
XTO2
VCO
C5
C2
L1
C1
VS
Figure 4-1 shows the typical application circuit. For C6, the supply-voltage blocking capacitor,
value of 68 nF X7R is recommended. C2 and C3 are NPO capacitors used to match the loop
antenna impedance to the power amplifier optimum load impedance. They are based on the
PCB trace antenna and are ≤ 20 pF NPO capacitors. C1 (typically 1 nF X7R) is needed for the
supply blocking of the PA. In combination with L1 (200 nH to 300 nH), they prevent the power
amplifier from coupling to the supply voltage and disturbing PLL operation. They should be
placed close to pin 5. L1 also provides a low resistive path to VS to deliver the DC current to
ANT1.
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9128D–RKE–01/09
The PCB loop antenna should not exceed a trace width of 1.5 mm otherwise the Q-factor of the
loop antenna is too high. C4 and C5 should be selected so that the XTO runs on the load reso-
nance frequency of the crystal. A crystal with a load capacitance of 9 pF is recommended for
proper start-up behavior and low current consumption. When determining values for C4 and C5,
a parasitic capacitance of 3 pF should be included. With value of 15 pF for C4 and C5, an effec-
tive load capacitance of 9 pF can be achieved e.g. 9 pF = (15 pF + 3 pF)/2. The supply VS is
typically delivered from a single Li-Cell.
4.1.1
Antenna Impedance Matching
The maximum output power is achieved by using load impedances according to Table 4-1 and
Table 4-2 on page 9 and the output power. The load impedance ZLOPT is defined as the imped-
ance seen from the ATA5749 ANT1, ANT2 into the matching network. This is not the output
impedance of the IC but essentially the peak voltage divided by the peak current with some addi-
tional parasitic effects (Cpar). Table 4-1 and Table 4-2 do not contain information pertaining to
C3 in Figure 4-2, which is an option for better matching at low power steps.
Figure 4-2 is the circuit that was used to obtain the typical output power measurements in Figure
4-3 on page 10 and typical current consumption in Figure 4-4 on page 10. Table 4-1 and Table
4-2 on page 9 provide recommended values and performance info at various output power lev-
els. For reference, ZLOPT is defined as the impedance seen from the ATA5749 ANT1, ANT2 into
the matching network.
Figure 4-2. Output Power Measurement Circuit
ZLOPT
ANT2
4
Power Meter
ANT1
5
C2
PA
50Ω
C3
L1
C1
VS
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ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
The used parts at Table 4-1 and Table 4-2 on page 9 are:
Inductors: high Q COILCRAFT 0805CS; Capacitors: AVX ACCU-P 0402
Table 4-1.
Measured PA Matching at 315 MHz (CLK_ON = “LOW”) at Typ. Samples
PWR
Register
Desired
Power (dBm)
L1
(nH)
C1
(pF)
C2
(pF)
RLOPT
(Ω)
ZLOPT
(Ω)
Cpar
(pF)
Actual Power
(dBm)
3
4
–0.5
1.0
110
100
100
100
82
1.2
1.5
1.5
1.5
1.8
2.2
2.7
2.7
3.3
3.6
4.7
5.6
5.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
2950
1940
1550
1250
1000
730
110 + 540j
150 + 520j
190 + 520j
220 + 480j
240 + 430j
280 + 360j
290 + 300j
290 + 290j
280 + 225j
250 + 150j
215 + 85j
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
–0.37
1.12
2.11
3.23
4.38
5.42
7.14
8.22
8.63
9.79
10.52
11.67
13
5
2.5
6
3.5
7
4.5
8
5.5
82
9
6.5
68
580
10
11
12
13
14
15
7.5
68
460
8.5
68
350
9.5
56
320
10.5
11.5
12.5
47
250
47
190
180 + 50j
47
160
160 + 45j
Table 4-2.
Measured PA Matching at 433.92 MHz (CLK_ON = “LOW”) at Typ. Samples
PWR
Register
Desired
Power (dBm)
L1
(nH)
C1
(pF)
C2
(pF)
RLOPT
(Ω)
ZLOPT
(Ω)
Cpar
(pF)
Actual Power
(dBm)
3
4
–0.5
1.0
68
56
56
47
47
47
43
36
33
36
36
27
27
0,9
2.7 + 2.2
1.2
1.5
1.5
1.5
5.6
5.6
5.6
1
2800
1850
1450
1150
950
60 + 400j
90 + 390j
110 + 380j
130 + 370j
150 + 350j
180 + 300j
200 + 270j
210 + 230j
200 + 170j
195 + 150j
175 + 100j
150 + 70j
130 + 50j
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
–0.62
1.3
5
2.5
2.73
3.03
4.63
6.18
6.66
7.91
8.68
9.8
6
3.5
1.8
7
4.5
1.6
8
5.5
1.8
680
9
6.5
2.2
560
10
11
12
13
14
15
7.5
2.4
1
450
8.5
3
1
340
9.5
2.7
1
310
10.5
11.5
12.5
3.6
1
230
10.49
11.6
12.5
4.7
1
180
4.7
1
150
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9128D–RKE–01/09
Figure 4-3. Typical Measured Output Power
15
V
S = 3.6V, PWR[0:15] = 15]
315 MHz
433 MHz
13
11
VS = 3.0V, PWR[0:15] = 15
9
7
V
S = 1.9V, PWR[0:15] = 15
VS = 3.6V, PWR[0:15] = 8
VS = 3.0V, PWR[0:15] = 8
VS = 1.9V, PWR[0:15] = 8
5
3
1
-40
27
85
125
Temperature [ C]
˚
Figure 4-4. Typical Current Consumption I at Port VS
23
315MHz
433MHz
VS = 3.6V, PWR[0:15] = 15
21
19
17
15
13
11
9
VS = 3.0V, PWR[0:15] = 15
S = 1.9V, PWR[0:15] = 15
V
VS = 3.6V, PWR[0:15] = 8
S = 3.0V, PWR[0:15] = 8
V
7
VS = 1.9V, PWR[0:15] = 8
5
-40
27
85
125
Temperature [ C]
˚
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ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
5. Pulling of Frequency due to ASK Modulation (PA Switching)
The switching effect on VCO frequency in ASK Mode is very low if a correct PCB layout and
decoupling is used. Therefore, power ramping is not needed to achieve a clean spectrum (see
Figure 5-1).
Figure 5-1. Typical RF Spectrum of 40 kHz ASK Modulation at Pout = 12.5 dBm
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9128D–RKE–01/09
6. Configuration Register
6.1
General Description
The user must program all 32 bits of the configuration register upon power up (EN = HIGH) or
whenever changes to operating parameters are desired. The configuration register bit assign-
ments and descriptions can be found in Table 6-1 and Table 6-2.
Table 6-1.
MSB
Organization of the Control Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLK_ S434_ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ
ONLY N315 [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1]
Frequency Adjust = FREQ[0..14]
FREQ[0] + 2 × FREQ[1] + 4 × FREQ[2] + ... + FREQ[14] × 16384 = 0..32767
LSB
15
FREQ FSEP FSEP FSEP FSEP FSEP FSEP FSEP FSEP DIV_
[0] [7] [6] [5] [4] [3] [2] [1] [0] CNTRL
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PWR PWR PWR PWR ASK_ CLK_
[3] [2] [1] [0] NFSK ON
0
FSK Shift = FSEP[0..7]
Output Power = PWR[0..3]
FSEP[0] + ... + FSEP[7] × 128 = 0..255
PWR[0] + .. + PWR[3] × 8 = 0..15
Table 6-2.
Name
Control Register Functional Descriptions
Bit No.
Size
Remarks
Activates/deactivates CLK_ONLY Mode
Low = Normal Mode
High = Clock Only Mode (Figure 4-1 on page 7)
CLK_ONLY
S434_N315
31
1
VCO band selection
High = 367 MHz to 450 MHz
Low = 300 MHz to 368 MHz
30
1
PLL frequency adjust
See Table 6-1 for formula
FREQ[0:14]
FSEP[0:7]
15 ... 29
7 ... 14
15
8
FSK deviation adjust
See Table 6-1 for formula
CLK output divider ratio
Low = fXTO/8
High = fXTO/4
DIV_CNTRL
PWR[0:3]
6
2 ... 5
1
1
4
1
PA output power adjustment
See Table 4-1 and Table 4-2 on page 9
Modulation type
Low = FSK
ASK_NFSK
High = ASK
CLK_DRV port control
HIGH = CLK port is ON
LOW = CLK port is OFF
CLK_ON
0
1
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ATA5749 [Preliminary]
6.2
Programming
The configuration register is programmed serially using the SPI bus, starting with the MSB. It
consists of the Enable line (EN), the Data line (SDIN_TXDIN), and the SPI-Bus Clock (SCK).
The SDIN_TXDIN data is loaded on the positive edge of the SCK. The contents of the configura-
tion register become programmed on the negative SCK edge of the last bit (LSB) of the
programming sequence. The timing of this bus is shown in Figure 6-1. Note that the maximum
usable clock speed on the SPI bus is limited to 2 MHz.
Figure 6-1. SPI Bus Timing
EN
TSCK_High
TSDIN_TXDIN_setup
TEN_setup
TSCK_Cycle
TSCK_Low
SCK
THold
TSetup
SDIN_TXDIN
MSB
X
MSB-1
X
At the conclusion of the 32 bit programming sequence, the SDIN_TXDIN line becomes the mod-
ulation input for the RF transmitter. After programming is complete, the SCK signal has no effect
on the device. To disable the transmitter and enter the OFF Mode, EN and SDIN_TXDIN must
be returned to the LOW state. For clarity, several additional timing diagrams are included. Figure
6-2 shows the situation when the programming terminates faster then the XTO is ready.
Figure 6-2. Timing Diagram if Register Programming is Faster than ΔTXTO
ΔTXTO
EN (Input)
SDIN_TXDIN
(Input)
32-bit Configuration
TX-Data
SCK (Input)
X
X
X
TPLL
CLK (Output)
PA (Output
Power)
FSK;
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
OFF_
Mode
Start_Up_
Mode_1
Start_Up_
Mode_2
TX_
Mode1
OFF_Mode
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9128D–RKE–01/09
Figure 6-3 shows the combination with slow programming and a faster ramp up of XTO. A dia-
gram of the operating modes is shown in Figure 6-5 and a description of which circuit blocks are
active is provided in Table 6-3 on page 15. This also contains the information needed for the cal-
culation of consumed charge for one operation cycle.
Figure 6-3. Timing Diagram if Programming is Slower than TXTO
ΔTXTO
EN (Input)
TPLL
SDIN_TXDIN
(Input)
32-bit Configuration
TX-Data
SCK (Input)
X
X
CLK (Output)
PA (Output
Power)
FSK;
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
OFF_
Mode
Start_Up_
Mode_1
Start_Up_
Mode_2
TX_
Mode1
OFF_Mode
6.3
Reprogramming without Stopping the Crystal Oscillator
After the configuration register is programmed and RF data transmission is completed, the OFF
mode is normally entered. This stops the crystal oscillator and PLL. If it is desirable to modify the
contents of the configuration register without entering the OFF mode, the Reset_Register_Mode
can be used. To enter the Reset_Register_Mode, the SDIN_TXDIN must be asserted HIGH
while the EN is asserted LOW for at least 10 µs Reset_min time. This state is shown in Figure
6-4 on page 15, State Diagram of Operating Modes. In Reset_Register_Mode, the PA and frac-
tional PLL remain OFF but the XTO remains active. This state must stay for minimum 10 µs. At
the next step you must rise first EN and SDIN_TXDIN 10 µs delayed. While in this mode, the
32 bit configuration register data can be sent on the SPI bus as shown in Figure 6-2 on page 13.
After data transmission, the device can be switched back to OFF_Mode by asserting EN, SCK,
and SDIN_TXDIN to a LOW state. An example of programming from the Reset_Register_Mode
is shown in Figure 6-4 on page 15.
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ATA5749 [Preliminary]
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ATA5749 [Preliminary]
Figure 6-4. Timing Diagram when using Reset_Register_Mode
TEN_Reset
TPLL
TPLL
EN (Input)
TEN_setup
TSDIN_TXDIN_setup
SDIN_TXDIN
(Input)
32-bit
TX_
32-bit
TX_
Configuration
Data
Configuration
Data
SCK (Input)
CLK (Output)
PA (Output
Power)
FSK;
FSK;
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
TX_Mode2
ASK:
TX_Mode1 and
TX_Mode2
Start_Up_ Start_Up_
Reset_
Con-
Con-
OFF_
Mode
Mode_1
Mode_2
Register_ figuration_ figuration_
Mode
Mode_1
Mode_2
TX_Mode1
TX_Mode1
Table 6-3.
Active Circuits as a Function of Operating Mode
Operating Mode
OFF_Mode
Active Circuit Blocks
-none-
Start_Up_Mode_1
Start_Up_Mode_2
TX_Mode1
Power up/down; XTO; digital control
Power up/down; XTO; digital control; fractional-N-PLL
Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1)
Power up/down; XTO; digital control; fractional-N-PLL; CLK_DRV(1); PA
Power up/down; XTO; digital control; CLK_DRV(1)
Power up/down; XTO; digital control; CLK_DRV(1)
Power up/down; XTO; digital control; CLK_DRV(1)
TX_Mode2
Clock_Only_Mode
Reset_Register_Mode
Configuration_Mode_1
Configuration_Mode_2
Power up/down; XTO; digital control; CLK_DRV(1); fractional-N-PLL
Note:
1. Only if activated with CLK_ON = HIGH
15
9128D–RKE–01/09
Figure 6-5. State Diagram of Operating Modes
OFF_Mode
EN = 'High'
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
Start-Up_Mode_1
EN = 'Low'
SDIN_TXDIN = 'Low'
CLK_Only = 'Low'
register parity programmed
CLK_Only = 'High'
register programmed
XTO_RDY = 'High'
1
2
CLK_Only = 'Low'
register programmed
XTO_RDY = 'High'
2
ASK_NFSK = 'Low' or
(ASK_NFSK = 'High' and
SDIN_TXDIN = 'High')
Start-Up_Mode_2
3
PLL locked
TX_Mode_2
TX_Mode_1
Clock_only_Mode
CLK_Only = 'Low'
register programmed
2
ASK_NFSK = 'High' and
SDIN_TXDIN = 'Low'
CLK_Only = 'High'
register programmed
2
Configuration_Mode_2
CLK_Only = 'Low'
register parity programmed
1
EN = 'Low'
SDIN_TXDIN = 'High'
EN = 'Low'
SDIN_TXDIN = 'High'
EN = 'Low'
SDIN_TXDIN = 'High'
Configuration_Mode_1
1 )"register partly programmed": negative SCK
edge of 32-bit register programming MSB-1
(S433_N315)
EN = 'High'
SDIN_TXDIN = 'Low'
2 ) "register programmed'" negative SCK
edge of 32-bit register programming LSB
(CLK_ON)
Reset_Register_Mode
3 ) "PLL locked" 1280 XTO cycles (TPLL) after
register programmed and XTO_RDY = 'High'
To transition from one state to another, only the
conditions next to the transition arrows must be
fulfilled. No additional settings are required.
16
ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
7. ESD Protection Circuit
Figure 7-1. ESD Protection Circuit
VS
ANT1
ANT2
CLK
SCK
EN
XTO2
XTO1
SDIN_TXDIN
GND
8. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
Max.
+4.0
100
Unit
V
Supply voltage
–0.3
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Ptot
mW
°C
Tj
150
Tstg
–55
–40
+125
+125
°C
Tamb1
°C
Ambient temperature in power-down mode for 30 minutes
without damage with VS ≤ 3.2V, VENABLE < 0.25V or
ENABLE is open, VASK < 0.25V, VFSK < 0.25V
Tamb2
175
°C
ESD (Human Body Model ESD S5.1) every pin
excluding pin 5 (ANT1)
HBM
HBM
MM
–4
–2
+4
+2
kV
kV
V
ESD (Human Body Model ESD S5.1) for pin 5 (ANT1)
ESD (Machine Model JEDEC A115A) every pin
excluding pin 5 (ANT1)
–200
–150
+200
ESD (Machine Model JEDEC A115A) for pin 5 (ANT1)
ESD – STM 5.3.1-1999 every pin
MM
+150
750
V
V
CDM
9. Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance, junction ambient
RthJA
170
K/W
17
9128D–RKE–01/09
10. Electrical Characteristics
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz,
f
CLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF,
C0 = 1.5 pF, CLOAD = 9 pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
V(SDIN_TXDIN,SCK,EN) = Low
Supply current,
OFF_Mode
1.1
T
T
T
amb ≤ +25°C
amb ≤ +85°C
amb ≤ +125°C
5, 8
IS_Off_Mode
1
20
265
100
350
7000
nA
nA
nA
A
Supply current,
TX_Mode1
1.2
1.3
1.4
VS ≤ 3.0V
5, 8
5, 8
5, 8
IS_TX_Mode1
IS_TX_Mode2
3.6
7.3
480
4.7
8.8
mA
mA
µA
A
A
A
Supply current,
TX_Mode2
VS ≤ 3.0V
PWR[0:3] = 8 (5.5 dBm)
Supply current,
CLK_Only_Mode
IS_CLK_Only _
VS ≤ 3.0V
680
Mode
VS ≤ 3.0V
CLK_ON = “Low”
IS = IS_any_Mode + ΔICLKoff1
Supply current
1.5 reduction, Clock Driver
off
5, 8
ΔICLKoff1
–250
150
–300
µA
B
(can be applied to all modes
except Off_Mode, add Typ. to
Typ. and Max. to Max. values)
VS ≤ 3.0V
DIV_CNTRL = “High”
fCLK = 3.24 MHz
Supply current
1.6 increase, Clock Driver
higher frequency
IS= IS_any__Mode + ΔICLKhigh
5, 8
5, 8
ΔICLKhigh
190
680
µA
µA
B
A
(can be applied to all modes
except Off_Mode add Typ. to
Typ. and Max. to Max. values)
IS_Reset_
Reset_Register_Mode /
1.7
Register_Mode /
IS_Configuration
VS ≤ 3.0V
Configuration_Mode_1
_ Mode_1
IS_Configuration
Configuration_Mode_2/
1.8
/
_Mode_2
VS ≤ 3.0V
VS ≤ 3.0V
5, 8
5, 8
4.7
mA
µA
A
A
Start_Up_Mode_2
IS_Start_Up
_Mode_2
IS_Start_Up
_Mode_1
1.9 Start_Up_Mode_1
300
2
Power Amplifier (PA)
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 4
ZLOAD = ZLOPT according Table
4-1 and Table 4-2 on page 9
Output power 1,
TX_Mode2
2.1
(5)
POUT_1
–1.0
+1.0
+3.0
dBm
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
18
ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz,
fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF,
C0 = 1.5 pF, CLOAD = 9 pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS = 3.0V
PWR[0:3] = 4
5, 8
IS_P1
5.4
6.7
mA
A
Supply current 1,
TX_Mode2
2.2
2.3
2.4
2.5
2.6
VS = 3.6V
PWR[0:3] = 4
5, 8
(5)
IS_P1
7.0
7.0
mA
A
A
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 8
ZLOAD = ZLOPT according to Table
4-1 and Table 4-2 on page 9
Output power 2,
TX_Mode2
POUT_2
4.0
5.5
7.3
dBm
VS = 3.0V, PWR[0:3] = 8
[typ. 5.5 dBm; see 2.3]
5, 8
5, 8
IS_P2
IS_P2
8.8
9.1
mA
mA
A
A
Supply current 2,
TX_Mode2
VS = 3.6V, PWR[0:3] = 8
[typ. 5.5 dBm; see 2.3]
VS = 3.0V, Tamb = 25°C
PWR[0:3] = 15
ZLOAD = ZLOPT according to Table
4-1 and Table 4-2 on page 9
Output power 3,
TX_Mode2
(5)
POUT_3
11.0
12.5
20.2
14.0
dBm
A
VS = 3.0V
PWR[0:3] = 15
5, 8
5, 8
IS_P3
IS_P3
23.5
24.5
mA
mA
A
A
Supply current 3,
TX_Mode2
VS = 3.6V
PWR[0:3] = 15
Tamb = –40°C to +125°C
VS = 1.9V to 3.6V
Output Power Variation
Pout = POUT_x + ΔPOUT
2.7 for full temperature and
supply voltage range
(5)
ΔPOUT
–4.0
+1.5
dB
B
(can be applied to all power
levels)
3
Crystal Oscillator (XTO)
Maximum series
3.1 resistance RM of XTAL C0 < 2.0 pF
after start-up
6, 7
6, 7
RM_MAX
170
15
Ω
D
D
Motional capacitance of
3.2
Recommended values
CM
2
4.0
fF
XTAL
C0 < 2.0 pF
CM = 4.0 fF
RM = 20Ω
Stabilized Amplitude
XTAL
3.3
6, 7
6, 7
mVpp
ppm
A
C
CLOAD = 9 pF
V(XTO2) – V(XTO1)
V(XTO1)
VppXTO21
VppXTO1
640
320
1.0 < C0 < 2.0 pF
RM < 170Ω
3.4 temperature and supply CLOAD = 9 pF
change 4 fF < CM < 10 fF
CM < 15 fF
Pulling of fXTO versus
ΔfRF
–3
–5
+3
+5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
19
9128D–RKE–01/09
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz,
fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF,
C0 = 1.5 pF, CLOAD = 9 pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
DC voltage after XTAL V(XTO2) – V(XTO1)
3.5
6, 7
VDC_XTO
40
mV
C
amplitude stable
XTO running
This value is important for
crystal oscillator start-up
behavior
Negative real part of
3.6 XTO impedance at
begin of start-up
C0 < 2.0 pF,
8 pF < CLOAD < 10 pF
6, 7 RXTO12_START –1500
–2200
Ω
B
D
FXTAL = 13.000 MHz
11.0 MHz < FXTAL < 14.8 MHz
–1300
Recommended values for proper
start-up and low current
consumption
External Capacitors
Quality NPO
C4
C5
3.7
6, 7
–5%
15
+5%
pF
C4, C5
CLOAD = (C4 + CXTO1) ×
(C5 + CXTO2) /
(C4 + C5 + CXTO1 + CXTO2
)
CLoad_nom = 9 pF (inc. PCB)
Pin Capacitance
3.8
The PCB Capacitance of about
1 pF has to be added
CXTO1
CXTO2
–15%
–15%
2
2
+15%
+15%
6, 7
pF
C
B
XTO1 and XTO2
Time between EN = “High” and
XTO_RDY = “High”
C0 < 2.0 pF, 4 fF < CM < 15 fF
C0 < 2.0 pF, 2 fF < CM < 15 fF
RM < 170Ω
Crystal oscillator
3.9
0.20
0.32
0.3
0.5
6, 7, 1
ΔTXTO
ms
start-up time
11.0 MHz < FXTAL < 14.8 MHz
Maximum shunt
3.10
Required for stable operation of
capacitance C0 of XTAL XTO, CLoad > 7. 5 pF
6, 7
6, 7
C0_MAX
fXTO
1.5
3.0
pF
D
C
Oscillator frequency
XTO
433.92 MHz and 315 MHz other
frequencies
13.0000
3.11
4
MHz
11.0
14.8
Fractional-N-PLL
Frequency range of RF S434_N315 = “LOW”
300
367
368
450
4.1
5
fRF
MHz
µs
A
B
frequency
S434_N315 = “HIGH”
Time between
XTO_RDY= “High” and Register
98.46
4.2 Locking time of the PLL programmed till PLL is locked
XTO = 13.0000 MHz
1, 5
ΔTPLL
1280/
fXTO
f
other fXTO
Unity gain loop frequency of
synthesizer
4.3 PLL loop bandwidth
5
5
fLoop_PLL
LPLL
140
280
–83
380
–76
kHz
B
A
In Loop phase noise
4.4
25 kHz distance to carrier
dBc/Hz
PLL
A
C
Out of Loop Phase
noise (VCO)
At 1 MHz
At 36 MHz
Lat1M
Lat36M
–91
–122
–84
–115
dBc/Hz
dBc/Hz
4.5
5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
20
ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
10. Electrical Characteristics (Continued)
VS = 1.9V to 3.6V Tamb = –40°C to +125°C, CLK_ON = “High”; DIV_CNTRL = “Low”, CLOAD_CLK = 10 pF. fXTO = 13.0000 MHz,
fCLK = 1.625 MHz unless otherwise specified. If crystal parameters are important values correspond to a crystal with CM = 4.0 fF,
C0 = 1.5 pF, CLOAD = 9 pF and RM ≤ 170Ω. Typical values are given at VS = 3.0V and Tamb = 25°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Duty cycle of the modulation
signal = 50%, (this corresponds
to 40 kBit/s Manchester coding
and 80 kBit/s NRZ coding)
FSK modulation
frequency
4.6
2, 5
FMOD_FSK
0
40
kHz
B
Duty cycle of the modulation
signal = 50%, (this corresponds
to 40 kBit/s Manchester coding
and 80 kBit/s NRZ coding)
ASK modulation
frequency
4.7
2, 5
5
FMOD_ASK
0
40
kHz
dBc
B
B
At fRF ±fXTO / 8
At fRF ±fXTO / 4
At fRF ±fXTO
–47
–47
–60
4.8 Spurious emission
Spur
DIV_CNTRL = “High”
At fRF ± fXTO / 4
At fRF ± fXTO
4.9 Spurious emission
4.10 Spurious emission
5
5
Spur
Spur
–47
–58
dBc
dBc
B
B
CLK_ON = “Low”
At f0 ± fXTO
–60
ASK_NFSK = “High”
TX_Mode_2
FREQ[0:14] = 3730,
FSEP[0:7] = 101
S434_N315 = “Low”
fRF ±3.00 MHz
–50
–50
4.11 Fractional Spurious
5
Spur
dBc
B
fRF ±6.00 MHz
FREQ[0:14] = 14342,
FSEP[0:7] = 101
S434_N315 = “High”
fRF ±3.159 MHz
–50
–50
fRF ± 9,840MHz
±0.396
±101.16
kHz
Hz
A
A
fXTO = 13.0000 MHz
other fXTO
see Table 3-1 on page 4
FSK frequency
4.12
fXTO
/
fXTO
/
5
fdev
deviation
32768
128.5
793
fXTO = 13.0000 MHz
other fXTO
fXTO
16384
/
4.13 Frequency resolution
ΔfPLL
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
(Pin Number) in brackets mean they are measured matched to 50Ω according to Figure 4-2 on page 8 with component values
and optimum load impedances according to Table 4-1 and Table 4-2 on page 9
21
9128D–RKE–01/09
11. Timing Characteristics (ATA5749)
VS = 1.9V to 3.6V, Tamb = –40°C to +125°C. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND
(pin 9). Parameters where crystal relevant parameters are important correspond to a crystal with CM = 4.0 fF, C0 = 1.5 pF, CLOAD = 9 pF
and RM ≤ 170Ω unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
EN set-up time to rising
edge of SCK
1.1
1.2
1.3
1.4
1, 10
TEN_setup
10
µs
C
SDIN_TXDIN set-up time
to falling edge of EN
TSDIN_TXDIN
2, 10
2, 3
125
10
ns
ns
ns
C
C
C
_setup
SDIN_TXDIN set-up time
to rising edge of SCK
TSetup
THold
SDIN_TXDIN hold time
from rising edge of SCK
2, 3
10
1.5 SCK Cycle time
3
3
3
TSCK_Cycle
TSCK_High
TSCK_Low
500
200
200
ns
ns
ns
C
C
C
1.6 SCK high time period
1.7 SCK low time period
EN low time period with
1.8 SDIN_TXDIN = “High” for
register reset
2, 10
TEN_Reset
10
us
C
f
XTO = 13.000 MHz
Clock output frequency
1.9 (CMOS microcontroller
compatible)
DIV_CNTRL = “High”
(fCLK = fXTO / 4)
DIV_CNTRL = “Low”
(fCLK = fXTO / 8)
3.25
1
fCLK
MHz
A
1.625
Cload ≤ 20 pF,
DIV_CNTRL = “Low”
(fclk = fXTO / 8)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 1.625 MHz
Clock output minimum
1.10
1
1
1
1
TCLKLH
TCLKLH
TCLKLH
TCLKLH
125
62.5
125
220
110
180
90
ns
ns
ns
ns
A
A
C
C
“High” and “Low” time
Cload ≤ 10 pF,
DIV_CNTRL = “High”
(fclk = fXTO / 4)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 3.25 MHz
Clock output minimum
1.11
“High” and “Low” time
Cload ≤ 20 pF,
DIV_CNTRL = “Low”
(fclk = fXTO / 8)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 1.85 MHz
Clock output minimum
1.12
“High” and “Low” time
Cload ≤ 10 pF,
DIV_CNTRL = “High”
(fclk = fXTO / 4)
“High” = 0.8 × VS,
“Low” = 0.2 × VS,
fCLK < 3.7 MHz
Clock output minimum
1.13
62.6
“High” and “Low” time
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
12. Digital Port Characteristics
VS = 1.9V to 3.6V, Tamb = 40°C to +125°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C, all inputs are
Schmitt trigger interfaces.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
250
250
250
Max.
Unit
Type*
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
0.25
VS
380
V
V
kΩ
1.1 SDIN_TXDIN
VS – 0.25
160
A
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
0.25
VS
380
V
V
kΩ
1.2 SCK
VS – 0.25
160
A
A
“Low” level input voltage
“High” level input voltage
Internal pull-down resistor
VII
Vih
RPDN
0
0.25
VS
380
V
V
kΩ
1.3 EN input
VS – 0.25
160
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
23
9128D–RKE–01/09
13. Ordering Information
Extended Type Number
Package
Remarks
ATA5749-6DQ
MSOP10
-
14. Package Information
Package: TSSOP 10
(acc. to JEDEC Standard MO-187)
Dimensions in mm
Not indicated tolerances ± 0.05
3±0.1
3±0.1
0.25
3.8±0.3
4.9±0.1
0.5 nom.
4 x 0.5 = 2 nom.
10 9 8 7 6
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5095.01-4
Issue: 3; 16.09.05
1 2 3 4 5
24
ATA5749 [Preliminary]
9128D–RKE–01/09
ATA5749 [Preliminary]
15. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Features on page 1 changed
9128D-RKE-01/09
• Section 8 “Absolute Maximum Ratings” on page 17 changed
• Features on page 1 changed
9128C-RKE-10/08
9128B-RKE-08/08
• Section 8 “Absolute Maximum Ratings” on page 17 changed
• Section 12 “Digital Port Characteristics” on page 23 changed
• Put datasheet in the newest template
• Features on page 1 changed
• Section 1 “Description” on page 1 changed
• Figure 1-1 “Block Diagram” on page 2 changed
• Section 3.1 “Fractional-N PLL” on page 4 changed
• Section 3.4 “Clock Driver” on page 6 changed
• Figure 4-1 “Typical Application Circuit” on page 7 changed
• Figure 4-2 “Output Power Measurement Circuit” on page 8 changed
• Section 10 “Electrical Characteristics” numbers 4.2, 4.12 and 4.13 on
pages 20 to 21 changed
25
9128D–RKE–01/09
Headquarters
International
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