ATA5756-6DQY [ATMEL]
UHF ASK/FSK Transmitter; 超高频ASK / FSK发射器
| 型号： | ATA5756-6DQY |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK Transmitter |
| 文件： | 总20页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• PLL Transmitter IC with Single-ended Output
• High Output Power (6 dBm) at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Typical Values
• Divide by 24 (ATA5756) and 32 (ATA5757) Blocks for 13 MHz Crystal Frequencies and
for Low XTO Start-up Times
• Modulation Scheme ASK/FSK with Internal FSK Switch
• Up to 20 kBaud Manchester Coding, Up to 40 kBaud NRZ Coding
• Power-down Idle and Power-up Modes to Adjust Corresponding Current Consumption
through ASK/FSK/Enable Input Pins
UHF ASK/FSK
Transmitter
• ENABLE Input for Parallel Usage of Controlling Pins in a 3-wire Bus System
• CLK Output Switches ON if the Crystal Current Amplitude has Reached 35% to 80% of
its Final Value
• Crystal Oscillator Time Until CLK Output is Activated, Typically 0.6 ms
• Supply Voltage 2.0 V to 3.6 V in Operation Temperature Range of -40°C to +125°C
• ESD Protection at all Pins (4 kV HBM)
ATA5756
ATA5757
• Small Package TSSOP10
Benefits
• Low Parasitic FSK Switch Integrated
• Very Short and Reproducible Time to Transmit Typically < 0.85 ms
• 13.125 MHz/13.56 MHz Crystals Give Opportunity for Small Package Sizes
1. Description
The ATA5756/ATA5757 is a PLL transmitter IC which has been developed for the
demands of RF low-cost transmission systems at data rates up to 20 kBaud Man-
chester coding and 40 kBaud NRZ coding. The transmitting frequency range is
313 MHz to 317 MHz (ATA5756) and 432 MHz to 448 MHz (ATA5757), respectively.
It can be used in both FSK and ASK systems. Due to its shorten crystal oscillator set-
tling time it is well suited for Tire Pressure Monitoring (TPM) and for Passive Entry Go
applications.
Figure 1-1. System Block Diagram
UHF ASK/FSK
TPM and Remote control
UHF ASK/FSK
Remote control receiver
transmitter
1 Li cell
ATA5756/
ATA5757
U3741B/
U3745B/
T5743/
Demod.
1...3
Control
µC
Encoder
ATARx9x
T5744/
PLL
IF Amp
Keys
Antenna Antenna
XTO
VCO
PLL
XTO
Power
amp.
LNA
VCO
4702J–RKE–09/08
2. Pin Configuration
Figure 2-1. Pinning TSSOP10
10
1
2
3
4
5
ENABLE
GND
CLK
ASK
9
8
7
ATA5756
ATA5757
VS
FSK
ANT2
ANT1
XTO1
XTO2
6
Table 2-1.
Pin
Pin Description
Symbol
Function
Configuration
VS
Clock output signal for the
microcontroller.
The clock output frequency is set by the
crystal to fXTAL/8.
100
100
The CLK output stays Low in
power-down mode and after enabling of
the PLL.
CLK
1
CLK
The CLK output switches on if the
oscillation amplitude of the crystal has
reached a certain level.
200k
ASK
50k
VRef = 1.1V
Switches on the power amplifier for
ASK modulation and enables the PLL
and XTO if the ENABLE pin is open
2
ASK
200k
20 µA
FSK
200k
VRef = 1.1V
Switches off the FSK switch (switch has
high Z if signal at pin FSK is High) and
enables the PLL and the XTO if the
ENABLE pin is open
5 µA
3
FSK
200k
2
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
Table 2-1.
Pin Description (Continued)
Pin
Symbol
Function
Configuration
4
ANT2
Emitter of antenna output stage
ANT1
5
ANT1
Open collector antenna output
ANT2
210 µA
(FSK < 0.25V)
AND
(ENABLE > 1.7V)
6
XTO2
Diode switch, used for FSK modulation
XTO2
VS
VS
1.5k
1.2k
7
XTO1
Connection for crystal
XTO1
182 µA
8
9
VS
Supply voltage
Ground
See ESD protection circuitry (see Figure 4-9 on page 14)
See ESD protection circuitry (see Figure 4-9 on page 14)
GND
VS
ENABLE input
30 µA
If ENABLE is connected to GND and
the ASK or FSK pin is High, the device
stays in idle mode.
In normal operation ENABLE is left
open and ASK or FSK is used to enable
the device.
(FSK >1.7 V ) OR
(ASK > 1.7 V)
10
ENABLE
ENABLE
150k
250k
3
4702J–RKE–09/08
Figure 2-2. Block Diagram
ATA5756 /
ATA5757
Power up/down
EN
CLK
ENABLE
10
f
1
8
f
24/
32
ASK
GND
9
2
OR
PFD
CP
LF
FSK
VS
8
3
Ampl. OK
ANT2
XTO1
7
XTO
4
EN
ANT1
XTO2
6
PA
VCO
5
PLL
3. General Description
This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmit-
ters for TPM and RKE applications. The VCO is locked to 24 × fXTAL/32 × fXTAL for
ATA5756/ATA5757. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a
315 MHz/433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal con-
nected in series to GND are needed as external elements in an ASK system. The internal FSK
switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator
needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical
characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter
time will result.
The CLK output is switched on if the amplitude of the current flowing through the crystal has
reached 35% to 80% of its final value. This is synchronized with the 1.64/1.69 MHz CLK output.
As a result, the first period of the CLK output is always a full period. The PLL is then locked
<250 µs after CLK output activation. This means an additional wait time of ≥250 µs is necessary
before the PA can be switched on and the data transmission can start. This results in a signifi-
cantly lower time of about 0.85 ms between enabling the ATA5756/ATA5757 and the beginning
of the data transmission which saves battery power especially in tire pressure monitoring
systems.
4
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
The power amplifier is an open-collector output delivering a current pulse which is nearly inde-
pendent from the load impedance and can therefore be controlled via the connected load
impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high
power efficiency for the power amplifier results if an optimized load impedance of
Z
Load, opt = 380 Ω + j340 Ω (ATA5756) at 315 MHz and ZLoad, opt = 280 Ω + j310 Ω (ATA5757) at
433.92 MHz is used at the 3-V supply voltage.
4. Functional Description
If ASK = Low, FSK = Low and ENABLE = open or Low, the circuit is in power-down mode con-
suming only a very small amount of current so that a lithium cell used as power supply can work
for many years.
If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input
pins. This means, the IC can be switched on by either the FSK of the ASK input.
If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO
and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can
be used to control other devices. This can help to save ports on the microcontroller in systems
where other devices with 3-wire interface are used.
With FSK = High and ASK = Low and ENABLE = open or High, the PLL and the XTO are
switched on and the power amplifier is off. When the amplitude of the current through the crystal
has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The
CLK output stays Low until the CLK driver has been activated. The driver is activated synchro-
nously with the CLK output frequency, hence, the first pulse on the CLK output is a complete
period. The PLL is then locked within <250 µs after the CLK driver has been activated, and the
transmitter is then ready for data transmission.
With ASK = High the power amplifier is switched on. This is used to perform the ASK modula-
tion. During ASK modulation the IC is enabled with the FSK or the ENABLE pin.
With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To
achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of
the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the
switch is off.
The different modes of the ATA5756/ATA5757 are listed in Table 4-1, the corresponding current
consumption values can be found in the table “Electrical Characteristics” on page 15.
Table 4-1.
ASK Pin
Low
ATA5756/ATA5757 Modes
FSK Pin
Low
ENABLE Pin
Mode
Low/open
High
Power-down mode, FSK switch High Z
Power-up, PA off, FSK switch Low Z
Power-up, PA off, FSK switch High Z
Power-up, PA on, FSK switch Low Z
Power-up, PA on, FSK switch High Z
Idle mode, FSK switch High Z
Idle mode, FSK switch High Z
Low
Low
Low
High
High/open
High/open
High/open
Low
High
Low
High
High
Low/High
High
High
Low/High
Low
5
4702J–RKE–09/08
4.1
Transmission with ENABLE = open
4.1.1
ASK Mode
The ATA5756/ATA5757 is activated by ENABLE = open, FSK = High, ASK = Low. The microcon-
troller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated
automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another
time period of ≤250 µs, the PLL is locked and ready to transmit. The output power can then be
modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcon-
troller returns back to internal clocking. Then, the ATA5756/ATA5757 is switched to power-down
mode with FSK = Low.
Figure 4-1. Timing ASK Mode with ENABLE not Connected to the Microcontroller
ΔTXTO
> 250 µs
FSK
ASK
CLK
Power-up, Power-up,
Power-up,
PA off
Power-down
Power-down
PA on
(High)
PA off
(Low)
4.1.2
FSK Mode
The ATA5756/ATA5757 is activated by FSK = High, ASK = Low. The microcontroller is then
switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically
(i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of
≤250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with
ASK = H. The ATA5756/ATA5757 is then ready for FSK modulation. The microcontroller starts to
switch on and off the capacitor between the crystal load capacitor and GND by means of pin
FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is
lower, if FSK = H output frequency is higher. After transmission, FSK stays High and ASK is
switched to Low and the microcontroller returns back to internal clocking. Then, the
ATA5756/ATA5757 is switched to power-down mode with FSK = Low.
Figure 4-2. Timing FSK Mode with ENABLE not Connected to the Microcontroller
ΔTXTO
> 250 µs
FSK
ASK
CLK
Power-up, Power-up,
PA on PA off
(fRF = High) (fRF = Low)
Power-up,
PA off
Power-down
Power-down
6
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
4.2
Transmission with ENABLE = High
4.2.1
FSK Mode
The ATA5756/ATA5757 is activated by ENABLE = High, FSK = High and ASK = Low. The micro-
controller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated
automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another
time period of ≤250 µs, the PLL is locked and ready to transmit. The power amplifier is switched
on with ASK = H. The ATA5756/ATA5757 is then ready for FSK modulation. The microcontroller
starts to switch on and off the capacitor between the crystal load capacitor and GND by means
of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency
is lower, if FSK = H output frequency is higher. After transmission, ASK is switched to Low and
the microcontroller returns back to internal clocking. Then, the ATA5756/ATA5757 is switched to
power-down mode with ENABLE = Low and FSK = Low.
Figure 4-3. Timing FSK Mode with ENABLE Connected to the Microcontroller
ΔTXTO
> 250 µs
ENABLE
FSK
ASK
CLK
Power-up, Power-up,
PA on PA off
(fRF = High) (fRF = Low)
Power-up,
PA off
Power-down
Power-down
4.2.2
ASK Mode
The ATA5756/ATA5757 is activated by ENABLE = High, FSK = High and ASK = Low. After acti-
vation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver
is activated automatically (the microcontroller waits until the XTO and CLK are ready). After
another time period of ≤250 µs, the PLL is locked and ready to transmit. The output power can
then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the
microcontroller returns back to internal clocking. Then, the ATA5756/ATA5757 is switched to
power-down mode with ENABLE = Low and FSK = Low.
7
4702J–RKE–09/08
Figure 4-4. Timing ASK Mode with ENABLE Connected to the Microcontroller
ΔTXTO
> 250 µs
ENABLE
FSK
ASK
CLK
Power-up, Power-up,
Power-up,
PA off
Power-down
Power-down
PA on
(High)
PA off
(Low)
4.3
Accuracy of Frequency Deviation
The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the fol-
lowing tolerances are considered. One important aspect is that the values of C0 and CM of typical
crystals are strongly correlated which reduces the tolerance of the frequency deviation.
Figure 4-5. Tolerances of Frequency Modulation
~
VS
CStray
XTAL
CM LM
RS
C4
C0
C5
Crystal equivalent circuit
CSwitch
Using a crystal with a motional capacitance of CM = 4.37 fF ±15%, a nominal load capacitance of
CLNOM = 18 pF and a parallel capacitance of C0 = 1.30 pF correlated with CM results in
C0 = 297 × CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the
internal FSK switch with CSwitch = 0.9 pF ±20% and estimated parasites of CStray = 0.7 pF ±10%,
the resulting C4 and C5 values are C4 = 10 pF ±1% and C5 = 15 pF ±1% for a nominal frequency
deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz.
8
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
4.4
Accuracy of the Center Frequency
The imaginary part of the impedance in large signal steady state oscillation IMXTO, seen into the
pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of the XTO oscillation
frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment
tolerance, temperature stability and ageing) and the influence to the center frequency due to tol-
erances of C4, C5, CSwitch and CStray. The nominal value of IMXTO = 110 Ω, CSwitch and CStray
should be absorbed into the C4 and C5 values by using a crystal with known frequency and
choosing C4 and C5, so that the XTO center frequency equals the crystal frequency, and the fre-
quency deviation is as expected. Then, from the nominal value, the IMXTO has ±90 Ω tolerances,
using the pulling formula P = -IMXTO × CM × π × fXTO with fXTO = 13.56 MHz and CM = 4.4 fF an
additional frequency tolerance of P = ±16.86 ppm results. If using crystals with other CM the
additional frequency tolerance can be calculated in the same way. For example, a lower
CM = 3.1 fF will reduce the frequency tolerance to 11.87 ppm, where a higher CM = 5.5 fF
increases the tolerance to 21.07 ppm.
4.5
CLK Output
An output CLK signal of 1.64 MHz (ATA5756 operating at 315 MHz) and 1.69 MHz (ATA5757
operating at 433.92 MHz) is provided for a connected microcontroller. The delivered signal is
CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than
20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. After
enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has
reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its
output signal so that the first period of the CLK output signal is a full period.
4.5.1
4.5.2
Clock Pulse Take-over by Microcontroller
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x
microcontroller family provides the special feature of starting with an integrated RC oscillator to
switch on the ATA5756/ATA5757’s external clocking and to wait automatically until the CLK out-
put of the ATA5756/ATA5757 is activated. After a time period of 250 µs the message can be sent
with crystal accuracy.
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of ZLoad, opt = 380 Ω + j340 Ω (ATA5756) at 315 MHz and
Z
Load, opt = 280 Ω + j310 Ω (ATA5757) at 433.92 MHz. A low resistive path to VS is required to
deliver the DC current (see Figure 4-6 on page 10).
The power amplifier delivers a current pulse and the maximum output power is delivered to a
resistive load if the 0.66 pF output capacitance of the power amplifier is compensated by the
load impedance.
At the ANT1 pin, the RF output amplitude is about VS - 0.5 V.
The load impedance is defined as the impedance seen from the ATA5756’s ANT1, ANT2 into
the matching network. Do not mix up this large-signal load impedance with a small-signal input
impedance delivered as an input characteristic of RF amplifiers.
The latter is measured from the application into the IC instead of from the IC into the application
for a power amplifier.
9
4702J–RKE–09/08
The 0.66 pF output capacitance absorbed into the load impedance a real impedance of 684 Ω
(ATA5756) at 315 MHz and 623 Ω (ATA5757) at 433.92 MHz should be measured with a net-
work analyses at pin 5 (ANT1) with the ATA5756/ATA5757 soldered, an optimized antenna
connected and the power amplifier switched off.
Less output power is achieved by lowering the real parallel part where the parallel imaginary part
should be kept constant. Lowering the real part of the load impedance also reduces the supply
voltage dependency of the output power.
Output power measurement can be done with the circuit as shown in Figure 4-6. Please note
that the component values must be changed to compensate the individual board parasitics until
the ATA5756/ATA5757 has the right load impedance. Also, the damping of the cable used to
measure the output power must be calibrated.
Figure 4-6. Output Power Measurement ATA5756/ATA5757
V
S
C1 = 1n
L1 = 68 nH/ 39 nH
Power
meter
ANT1
ANT2
Z = 50
C2 = 2.2 pF/1.8 pF
ZLopt
Rin
50
~
Table 4-2 and Table 4-3 show the output power and the supply current versus temperature and
supply voltage.
Table 4-2.
Output Power and Supply Current versus Temperature and Supply
Voltage for the ATA5756 with ZLoad = 380 Ω + j340 Ω (Correlation Tested)
VS = 2.0 V
(dBm/mA)
VS = 3.0 V
(dBm/mA)
VS = 3.6 V
(dBm/mA)
Ambient Temperature
Tamb = -40°C
3.1 ±1.5 / 7.2
3.0 ±1.5 / 7.5
3.0 ±1.5 / 7.5
2.5 ±1.5 / 7.6
6.1 +2/-3 / 7.7
6.0 ±2 / 8.1
7.1 +2/-3 / 7.9
7.4 ±2 / 8.3
Tamb = +25°C
Tamb = +85°C
Tamb = +125°C
5.8 +2/-3 / 8.2
5.5 +2/-3 / 8.2
7.2 +2/-3 / 8.5
6.5 +2/-3 / 8.5
Table 4-3.
Output Power and Supply Current versus Temperature and Supply
Voltage for the ATA5757 with ZLoad = 280 Ω + j310 Ω (Correlation Tested)
Ambient
VS = 2.0 V
(dBm/mA)
VS = 3.0 V
(dBm/mA)
VS = 3.6 V
(dBm/mA)
Temperature
Tamb = -40°C
Tamb = +25°C
Tamb = +85°C
Tamb = +125°C
3.3 ±1.5 / 7.6
3.0 ±1.5 / 8.0
2.8 ±1.5 / 8.0
2.7 ±1.5 / 8.1
6.2 +2/-3 / 8.1
6.0 ±2 / 8.5
7.1 +2/-3 / 8.4
7.5 ±2 / 8.8
5.7 +2/-3 / 8.6
5.5 +2/-3 / 8.7
6.8 +2/-3 / 8.8
6.6 +2/-3 / 8.9
10
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
4.6
Application Circuits
For the supply voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Figure
4-7 on page 12 and Figure 4-8 on page 13). C1 and C2 are used to match the loop antenna to
the power amplifier. For C2, two capacitors in series should be used to achieve a better toler-
ance value and to enable it to realize ZLoad,opt by using capacitors with standard values.
Together with the pins of ATA5756 and the PCB board wires, C1 forms a series resonance loop
that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally,
the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and
ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L1 (50 nH to 100 nH) can be printed on the PCB. C4 should be selected so that the XTO runs on
the load resonance frequency of the crystal. Normally, a value of 10 pF results in a 12 pF
load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of
the XTO1 pin.
11
4702J–RKE–09/08
Figure 4-7. ASK Application Circuit
VDD
1
S1
S2
BPXY
ATARx9x
VS
VSS
20
BPXY
BPXY
OSC1
7
BPXY
ATA5756/ATA5757
Power up/down
ENABLE
EN
f
CLK
1
10
8
f
24/
32
ASK
2
GND
9
OR
C3
PFD
FSK
3
VS
8
CP
LF
C2
VS
Ampl. OK
ANT2
4
XTO1
7
XTAL
XTO
Loop
Antenna
C1
C4
EN
ANT1
5
XTO2
6
PA
VCO
PLL
L1
VS
12
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
Figure 4-8. FSK Application Circuit
VDD
1
S1
S2
BPXY
ATARx9x
VS
VSS
20
BPXY
BPXY
OSC1
7
BPXY
ATA5756/ATA5757
Power up/down
ENABLE
EN
f
CLK
1
10
8
f
24/
32
ASK
2
GND
9
OR
C3
PFD
FSK
3
VS
8
CP
LF
C2
VS
Ampl. OK
XTO1
7
ANT2
4
XTAL
XTO
Loop
Antenna
C1
EN
ANT1
5
XTO2
6
C5
PA
VCO
C4
PLL
L1
VS
13
4702J–RKE–09/08
Figure 4-9. ESD Protection Circuit
VS
ANT1
ANT2
ASK
XTO2
CLK
FSK
XTO1
ENABLE
GND
5. Absolute Maximum Ratings
Parameters
Symbol
Minimum
Maximum
Unit
V
Supply voltage
VS
Ptot
Tj
5
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
100
150
125
125
mW
°C
Tstg
Tamb1
-55
-55
°C
°C
Ambient temperature in power-down mode for
15 minutes without damage with VS ≤ 3.2 V
VENABLE < 0.25 V or ENABLE is open,
VASK < 0.25 V, VFSK < 0.25 V
Tamb2
175
°C
V
Input voltage
VmaxASK
-0.3
(VS + 0.3)(1)
Note:
1. If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.
6. Thermal Resistance
Parameters
Symbol
Value
170
Unit
Junction ambient
RthJA
K/W
14
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
7. Electrical Characteristics
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
VENABLE < 0.25 V or ENABLE is open,
VASK < 0.25 V, VFSK < 0.25 V
Tamb = 25°C
Supply current,
power-down mode
IS_Off
1
100
350
7,000
nA
nA
nA
Tamb = -40°C to +85°C
Tamb = -40°C to +125°C
VENABLE < 0.25 V, VS ≤ 3.2 V
ASK,FSK can be Low or High
Supply current, idle mode
IS_IDLE
IS
100
4.6
µA
Supply current, power-up, PA off,
FSK switch High Z
VS ≤ 3.2 V, VFSK > 1.7 V,
3.6
mA
VASK < 0.25 V ENABLE is open
VS ≤ 3.2 V, CCLK ≤ 10 pF
VFSK > 1.7 V, VASK > 1.7 V
ENABLE is open
ATA5756
Supply current, power-up, PA on,
FSK switch High Z
IS_Transmit1
8.1
8.5
9.8
10.5
mA
mA
ATA5757
VS ≤ 3.2 V, CCLK ≤ 10 pF
VFSK< 0.25 V, VASK > 1.7 V
ENABLE is open
ATA5756
Supply current, power-up, PA on,
FSK Low Z
IS_Transmit2
8.4
8.8
10.2
11.0
mA
mA
ATA5757
VS = 3.0 V, Tamb = 25°C,
f = 315 MHz for ATA5756,
ZLoad, opt = (380 + j340) Ω
f = 433.92 MHz for ATA5757,
ZLoad, opt = (280 + j310) Ω
Output power
POut
4
1
6
8
dBm
dBm
dBc
Output power for the full
temperature and supply voltage
range
Tamb = -40°C to +125°C,
VS = 2.0 V to 3.2 V
POut
8.2
fCLK = fXT0/8
Load capacitance at pin CLK ≤ 20 pF
f0 ± fCLK
f0 ± fXT0
other spurious are lower
Spurious emission
Harmonics
Spour
-42
-60
With 50 Ω matching network
according to Figure 4-6 on page 10
2nd
3rd
-16
-15
dBc
dBc
f
XTO = f0/24 ATA5756
fXTO = f0/32 ATA5757
fXTAL = resonant frequency of the
XTAL, CM = 4.37 fF, load capacitance
selected accordingly
Oscillator frequency XTO
(= phase comparator frequency)
ΔfXTO
T
amb = -40°C to +85°C
-14.0
-17.5
fXTAL
fXTAL
+14.0
+17.5
ppm
ppm
Tamb = -40°C to +125°C
15
4702J–RKE–09/08
7. Electrical Characteristics (Continued)
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Since pulling P is
Imaginary part of XTO1
Impedance in steady state
oscillation
P = -IMXTO × CM × π × fXTO
ΔfXTO can be calculated out of IMXTO
with CM = 4.37 fF
IMXTO
j20
j110
j200
Ω
Real part of XTO1 impedance in
small signal oscillation
This value is important for crystal
oscillator start-up
REXTO
-650
-1100
Ω
Time between ENABLE of the IC with
FSK = H and activation of the CLK
output. The CLK is activated
synchronously to the output frequency
if the current through the XTAL has
reached 35% to 80% of its maximum
amplitude. Crystal parameters:
CM = 4.37 fF, C0 = 1.3 pF,
Crystal oscillator start-up time
ΔTXTO
0.6
1.4
ms
CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF,
RS ≤ 60 Ω
Current flowing through the crystal in
steady state oscillation (peak-to-peak
value)
XTO drive current
IDXTO
300
µApp
µs
Time between the activation of CLK
and when the PLL is locked
(transmitter ready for data
transmission)
Locking time of the PLL
ΔTPLL
250
-76
PLL loop bandwidth
fLoop_PLL
LPLL
250
-85
kHz
In loop phase noise PLL
25 kHz distance to carrier
dBc/Hz
at 1 MHz
at 36 MHz
Lat1M
Lat36M
-90
-121
-84
-115
dBc/Hz
dBc/Hz
Phase noise VCO
ATA5756
ATA5757
310
432
317
448
MHz
MHz
Frequency range of VCO
fVCO
fCLK
Clock output frequency (CMOS
microcontroller compatible)
ATA5756
ATA5757
f0/192
f0/256
MHz
ns
Clock output minimum High and
Low time
CLoad ≤ 20 pF, High = 0.8 × Vs,
Low = 0.2 × VS, fCLK < 1.7 MHz
TCLKLH
125
Series resonance resistance of
the resonator seen from pin
XTO1
For proper detection of the XTO
amplitude
Rs_max
CL_max
150
5
Ω
Capacitive load at Pin XTO1
pF
This corresponds to 20 kBaud in
Manchester coding and 40 kBaud in
NRZ coding
FSK modulation frequency rate
fMOD_FSK
0
20
kHz
FSK switch OFF resistance
FSK switch OFF capacitance
FSK switch ON resistance
High Z
RSWIT_OFF
CSWIT_OFF
RSWIT_ON
50
kΩ
pF
Ω
High Z capacitance
Low Z
0.75
0.9
1.1
130
175
Duty cycle of the modulation signal =
50%, this corresponds to 20 kBaud in
Manchester coding and 40 kBaud in
NRZ coding
ASK modulation frequency rate
fMOD_ASK
0
20
kHz
16
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
7. Electrical Characteristics (Continued)
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
VS
30
V
V
µA
ASK input
1.7
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
VS
30
V
V
µA
FSK input
1.7
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IInh
IInl
0.25
VS
40
V
V
µA
µA
1.7
-40
-40
ENABLE input
Input current Low
40
17
4702J–RKE–09/08
8. Ordering Information
Extended Type Number
Package
Remarks
ATA5756-6DQY
ATA5756-6DPY
TSSOP10
Pb-free
ATA5757-6DQY
ATA5757-6DPY
TSSOP10
Pb-free
9. Package Information TSSOP10
Package: TSSOP 10
(acc. to JEDEC Standard MO-187)
Dimensions in mm
Not indicated tolerances ± 0.05
3±0.1
3±0.1
0.25
3.8±0.3
4.9±0.1
0.5 nom.
4 x 0.5 = 2 nom.
10 9 8 7 6
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5095.01-4
Issue: 3; 16.09.05
1 2 3 4 5
18
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Page1: PB-free logo deleted
4702J-RKE-07/08
• Page 18: Ordering Information changed
• Put datasheet in a new template
4702I-RKE-11/05
4702H-RKE-09/04
• First page: Pb-free logo added
• Page 18: Ordering Information and package drawing changed
• Electrical Characteristics table, page 15, row “Output power for the full...”.
-> maximum value changed
• Electrical Characteristics table, page 15, row “Output power variation...”.
-> the word “variation” deleted
4702G-RKE-08/04
4702F-RKE-08/04
• Preliminary deleted
• Abs. Max. Ratings table (page 14): row “Input voltage” added
• Abs. Max. Ratings table (page 14): table note 1 added
• El. Char. table (page 17): rows “ASK input”, “FSK input“, “ENABLE input”
maximum values changed
4702E-RKE-07/04
19
4702J–RKE–09/08
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4702J–RKE–09/08
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