AT94S40AL-25BQL [ATMEL]
Field Programmable Gate Array, 2304 CLBs, 40000 Gates, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-144;
| 型号： | AT94S40AL-25BQL |
| 厂家： | 
ATMEL |
| 描述： | Field Programmable Gate Array, 2304 CLBs, 40000 Gates, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-144 栅 |
| 文件： | 总31页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC™) and Secure Configuration EEPROM Memory
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
• Field Programmable System Level Integrated Circuit (FPSLIC)
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core and
Extensive Data and Instruction SRAM
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
• Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE Std. 1149.1 Compliant) Interface
– Extensive On-chip Debugging Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
• AVR Fixed Peripherals
– Industry-standard 2-wire Serial Interface
Program
Storage
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
EEPROM
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
– FPGA Macro Library of Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
AT94S
Secure Series
Programmable
SLI
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 5V Tolerant I/O
• 3.3V 33 MHz PCI Compliant FPGA I/O
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
Rev. 2314D–FPSLI–2/04
Description
The AT94S Series (Secure FPSLIC family) shown in Table 1 is a combination of the
popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories
and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripher-
als. Extensive data and instruction SRAM as well as device control and management
logic are included in this multi-chip module (MCM).
The embedded AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA
with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port
SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss
of data) and 5,000 to 40,000 usable gates.
Table 1. The AT94S Series Family
Device
AT94S05AL
1 Mbit
5K
AT94S10AL
1 Mbit
10K
AT94S40AL
1 Mbit
40K
Configuration Memory Size
FPGA Gates
FPGA Core Cells
FPGA SRAM Bits
FPGA Registers (Total)
Maximum FPGA User I/O
AVR Programmable I/O Lines
Program SRAM Bytes
Data SRAM Bytes
Hardware Multiplier (8-bit)
2-wire Serial Interface
UARTs
256
576
2304
2048
436
4096
846
18432
2862
95
143
287
8
16
16
4K - 16K
4K - 16K
Yes
20K - 32K
4K - 16K
Yes
20K - 32K
4K - 16K
Yes
Yes
Yes
Yes
2
2
2
Watchdog Timer
Yes
Yes
Yes
Timer/Counters
3
3
3
Real-time Clock
Yes
Yes
Yes
JTAG ICE
Yes
Yes
Yes
@ 25 MHz
19 MIPS
30 MIPS
3.0 - 3.6V
19 MIPS
30 MIPS
3.0 - 3.6V
19 MIPS
30 MIPS
3.0 - 3.6V
Typical AVR
Throughput
@ 40 MHz
Operating Voltage
2
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Figure 1. AT94S Architecture
PROGRAMMABLE I/O
5 - 40K Gates FPGA
Configuration Logic
Up to 16
Decoded
Address Lines
Configuration
EEPROM
I/O
Up to 16K x 16
Program
SRAM Memory
For ISP
and Chip
Erase
4 Interrupt Lines
I/O
2-wire Serial
Unit
Two Serial
UARTs
I/O
with
Multiply
Two 8-bit
Timer/Counters
Up to
16K x 8
Data
SRAM
16 Prog. I/O
Lines
I/O
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe-
cuting powerful instructions in a single-clock-cycle, and allows system designers to
optimize power consumption versus processing speed. The AVR core is based on an
enhanced RISC architecture that combines a rich instruction set with 32 general-pur-
pose working registers. All 32 registers are directly connected to the Arithmetic Logic
Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code-efficient while
achieving throughputs up to ten times faster than conventional CISC microcontrollers at
the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA
configuration SRAM and AVR instruction code SRAM are automatically loaded at sys-
tem power-up using Atmel’s in-system programmable AT17 Series EEPROM
configuration memories, which are part of the AT94S Multi-chip Module (MCM).
State-of-the-art FPSLIC design tools, System Designer™, were developed in conjunc-
tion with the FPSLIC architecture to help reduce overall time-to-market by integrating
microcontroller development and debugging, FPGA development, place and route, and
complete system co-verification in one easy-to-use software tool.
3
2314D–FPSLI–2/04
Internal Architecture For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K
FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on
the Atmel web site at http://www.atmel.com. This document only describes the differ-
ences between the AT94S Secure FPSLIC and the AT94K FPSLIC.
FPSLIC and
Configurator
Interface
•
•
Fully In-System Programmable and Re-programmable
When Security Bit Set:
–
–
–
Data Verification Disabled
Data Transfer to FPSLIC not Externally Visible
Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip
Erase
•
When Security Bit Cleared:
–
–
–
Entire Chip Erase Performed
In-System Programming Enabled
Data Verification Enabled
External Data pins allow for In-System Programming of the device and setting of the
EEPROM-based security bit. When the security bit is set (active) this programming con-
nection will only respond to a device erase command. Data cannot be read out of the
external programming/data pins when the security bit is set. The part can be re-pro-
grammed, but only after first being erased.
Programming and
Configuration Timing
Characteristics
Atmel’s Configurator Programming Software (CPS), available from the Atmel web site
(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the pro-
gramming algorithm for the embedded configurator; however, if you are planning to
write your own software or use other means to program the embedded configurator, the
section below includes the algorithm and other details.
The FPSLIC Configurator The FPSLIC Configurator is a serial EEPROM memory which is used to load program-
mable devices. This document describes the features needed to program the
Configurator from within its programming mode (i.e., when SER_EN is driven Low).
Reference schematics are supplied for ISP applications.
Serial Bus Overview
The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided
by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro-
vide data and control information.
Information is transmitted on the serial bus in messages. Each MESSAGE is preceded
by a Start Condition and ends with a Stop Condition. The message consists of an inte-
ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth
Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted
byte. This is possible because devices may only drive the cSDA line Low. The system
must provide a small pull-up current (1 kΩ equivalent) for the cSDA line.
The MESSAGE FORMAT for read and write instructions consists of the bytes shown in
“Bit Format” on page 5.
While writing, the programmer is responsible for issuing the instruction and data. While
reading, the programmer issues the instruction and acknowledges the data from the
Configurator as necessary.
4
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a
byte-by-byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be
“initialized” except by explicitly writing a known value to each location using the serial
protocol described herein.
Bit Format
Data on the cSDA pin may change only during the cSCK Low time; whereas Start and
Stop Conditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
START
DEVICE
MS EEPROM
(NEXT) EEPROM
LS EEPROM
DATA
STOP
DATA
CONDITION ADDRESS ADDRESS BYTE ADDRESS BYTE ADDRESS BYTE BYTE 1
CONDITION
BYTE n
ACK BIT
(CONFIGURATOR)
Current Address Read (Extended to Sequential Read) Instruction Message Format
STOP
CONDITION
DATA
BYTE n
DATA
BYTE 1
START
CONDITION
DEVICE
ADDRESS
ACK BIT
(PROGRAMMER)
ACK BIT
(CONFIGURATOR)
Start and Stop
Conditions
The Start Condition is indicated by a high-to-low transition of the cSDA line when the
cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition
of the cSDA line when the cSCK line is High, as shown in Figure 2.
The Start Condition will return the device to the state where it is waiting for a Device
Address (its normal quiescent mode).
The Stop Condition initiates an internally timed write signal whose maximum duration is
tWR (refer to AC Characteristics table for actual value). During this time, the Configurator
must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines
are ignored until the cycle is completed. Since the write cycle typically completes in less
than tWR seconds, we recommend the use of “polling” as described in later sections.
Input levels to all other pins should be held constant until the write cycle has been
completed.
Acknowledge Bit
The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving
the byte. The receiving Configurator can accept the byte by asserting a Low value on
the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally
pulled up to) a High value on the cSDA line. All bytes from accepted messages must be
terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,
when the cSDA line is released during an exchange of control between the Configurator
and the programmer, the cSDA line may be pulled High temporarily due to the open-col-
lector output nature of the line. Control of the line must resume before the next rising
edge of the clock.
5
2314D–FPSLI–2/04
Bit Ordering Protocol
Device Address Byte
The most significant bit is the first bit of a byte transmitted on the cSDA line for the
Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser sig-
nificant bits until the eighth bit, the least significant bit, is transmitted. However, for Data
Bytes (both writing and reading), the first bit transmitted is the least significant bit. This
protocol is shown in the diagrams below.
The contents of the Device Address Byte are shown below, along with the order in which
the bits are clocked into the device.
The CE pin cannot be used for device selection in programming mode (i.e., when
SER_EN is drive Low).
Figure 2. Start and Stop Conditions
cSCK
8th Bit
ACK BIT
cSDA
Byte n
t
WR
STOP
START
Condition
Condition
Device Address Byte
MSB
LSB
R/W
8th
1
0
1
0
0
1
1
1st
2nd
3rd
4th
5th
6th
7th
Where:R/W= 1 Read
= 0 Write
EEPROM Address
512-Kbit/1-Mbit Page Length
Byte Order
MSB
LSB
MSB
LSB
MSB
LSB
0
0
0
0
0
0
0
AE16 ACK AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 ACK AE7
AE6 AE5 AE4 AE3 AE2 AE1 AE0 ACK
2nd 3rd 4th 5th 6th 7th 8th
1st 2nd 3rd 4th 5th 6th 7th
8th
1st
2nd 3rd
4th
5th
6th
7th
8th
1st
512-Kbit Address Space
1-Mbit Address Space
The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is
followed by an Acknowledge Bit (provided by the Configurator). These bytes define the
normal address space of the Configurator. The order in which each byte is clocked into
the Configurator is also indicated. Unused bits in an Address Byte must be set to “0”.
Exceptions to this are when reading Device and Manufacturer Codes.
6
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
Programming Summary:
Write to Whole Device
2. Data byte received/sent LSB to MSB.
START
EEPROM Address is Defined as:
SER_EN ≤ Low
AT17LV010 0000 000x9 x8x7x6x5 x4x3x2x1 x0000 0000
PAGE_COUNT ≤ 0
Note:
where Xn ... X0 is (PAGE_COUNT)\b
Send Start Condition
BYTE_COUNT ≤ 0
T_BYTE
AT17LV010
128
Send Device Address
($A6)
ACK?
ACK?
ACK?
ACK?
ACK?
No
No
No
No
No
T_PAGE
AT17LV010
1024
Yes
Send MSB of
EEPROM Address(1)
Yes
START CONDITION
Middle Byte
EEPROM Address
cSCK
cSDA
Yes
Send LSB of
EEPROM Address(1)
STOP CONDITION
Yes
cSCK
cSDA
Send Data Byte(2)
BYTE_COUNT ≤
BYTE_COUNT+1
Yes
DATA BIT
BYTE_COUNT =
T_BYTE?
No
cSCK
cSDA
Send Stop Condition
PAGE_COUNT ≤
PAGE_COUNT+1
PAGE_COUNT =
T_PAGE?
No
Yes
ACK BIT
cSCK
Send Start Condition
ACK
cSDA
Send Device Address
($A7)
ACK?
No
No
Yes
1st Data Byte
Value Changed Due
to Write?
SER_EN ≤ High
Low-power (Standby)
Yes
Power-Cycle EEPROM
(Latches 1st Byte for
FPGA Download
Operations)
END
7
2314D–FPSLI–2/04
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
Programming Summary:
Read from Whole Device
2. Data byte received/sent LSB to MSB
START
EEPROM Address is Defined as:
SER_EN ≤ Low
AT17LV010
00 00 00 \h
131072 \d
TT_BYTE
AT17LV010
Send Start Condition
START CONDITION
Send Device Address
($A6)
ACK?
ACK?
No
No
No
No
cSCK
cSDA
Yes
Middle Byte
EEPROM Address
STOP CONDITION
cSCK
Yes
Send MSB of
ACK?
ACK?
EEPROM Address(1)
cSDA
Yes
Send LSB of
SAMPLE DATA BIT
EEPROM Address(1)
cSCK
Yes
cSDA
Send Start condition
BYTE_COUNT ≤ 0
ACK BIT
cSCK
Send Device Address
($A7)
ACK?
No
cSDA
ACK
Yes
Read Data Byte(2)
BYTE_COUNT ≤
BYTE_COUNT+1
BYTE_COUNT=
TT_BYTE?
Send ACK
No
Yes
Sent Stop Condition
SER_EN ≤ High
Low-power (Standby)
END
8
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Data Byte
LSB
D0
MSB
D1
D2
D3
4th
D4
5th
D5
6th
D6
7th
D7
8th
1st
2nd
3rd
The organization of the Data Byte is shown above. Note that in this case, the Data Byte
is clocked into the device LSB first and MSB last.
Writing
Writing to the normal address space takes place in pages. A page is 128-bytes long in
the 1-Mbit part. The page boundaries are, respectively, addresses where AE0 down to
AEOS are all zero, and AE6 down to AE0 are all zero. Writing can start at any address
within a page and the number of bytes written must be 128 for the 1-Mbit part. The first
byte is written at the transmitted address. The address is incremented in the Configura-
tor following the receipt of each Data Byte. Only the lower 7 bits of the address are
incremented. Thus, after writing to the last byte address within the given page, the
address will roll over to the first byte address of the same page. A Write Instruction con-
sists of:
a Start Condition
a Device Address Byte with R/W = 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge Bit from the Configurator
One or more Data Bytes (sent to the
Configurator)
Each followed by an Acknowledge Bit from the
Configurator
a Stop Condition
WRITE POLLING: On receipt of the Stop Condition, the Configurator enters an inter-
nally-timed write cycle. While the Configurator is busy with this write cycle, it will not
acknowledge any transfers. The programmer can start the next page write by sending
the Start Condition followed by the Device Address, in effect polling the Configurator. If
this is not acknowledged, then the programmer should abandon the transfer without
asserting a Stop Condition. The programmer can then repeatedly initiate a write instruc-
tion as above, until an acknowledge is received. When the Acknowledge Bit is received,
the write instruction should continue by sending the first EEPROM Address Byte to the
Configurator.
An alternative to write polling would be to wait a period of tWR before sending the next
page of data or exiting the programming mode. All signals must be maintained during
the entire write cycle.
9
2314D–FPSLI–2/04
Reading
Read instructions are initiated similarly to write instructions. However, with the R/W bit in
the Device Address set to one. There are three variants of the read instruction: current
address read, random read and sequential read.
For all reads, it is important to understand that the internal Data Byte address counter
maintains the last address accessed during the previous read or write operation, incre-
mented by one. This address remains valid between operations as long as the chip
power is maintained and the device remains in 2-wire access mode (i.e., SER_EN is
driven Low). If the last operation was a read at address n, then the current address
would be n + 1. If the final operation was a write at address n, then the current address
would again be n + 1 with one exception. If address n was the last byte address in the
page, the incremented address n + 1 would “roll over” to the first byte address on the
next page.
CURRENT ADDRESS READ: Once the Device Address (with the R/W select bit set to
High) is clocked in and acknowledged by the Configurator, the Data Byte at the current
address is serially clocked out by the Configurator in response to the clock from the pro-
grammer. The programmer generates a Stop Condition to accept the single byte of data
and terminate the read instruction.
A Current Address Read instruction consists of
a Start Condition
a Device Address with R/W = 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
RANDOM READ: A Random Read is a Current Address Read preceded by an aborted
write instruction. The write instruction is only initiated for the purpose of loading the
EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address
Bytes are clocked in and acknowledged by the Configurator, the programmer immedi-
ately initiates a Current Address Read.
A Random Address Read instruction consists of :
a Start Condition
a Device Address with R/W = 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge bit from the Configurator
a Start Condition
a Device Address with R/W = 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
10
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a
Random Address Read. After the programmer receives a Data Byte, it may respond
with an Acknowledge Bit. As long as the Configurator receives an Acknowledge Bit, it
will continue to increment the Data Byte address and serially clock out sequential Data
Bytes until the memory address limit is reached.(1) The Sequential Read instruction is
terminated when the programmer does not respond with an Acknowledge Bit but
instead generates a Stop Condition following the receipt of a Data Byte.
Note:
1. If an ACK is sent by the programmer after the data in the last memory address is sent
by the configurator, the internal address counter will “rollover” to the first byte address
of the memory array and continue to send data as long as an ACK is sent by the
programmer.
Programmer Functions
The following programmer functions are supported while the Configurator is in program-
ming mode (i.e., when SER_EN is driven Low):
1. Read the Manufacturer’s Code and the Device Code (optional for ISP).
2. Program the device.
3. Verify the device.
In the order given above, they are performed in the following manner.
Reading Manufacturer’s
and Device Codes
On AT17LV010 Configurator, the sequential reading of these bytes are accomplished by
performing a Random Read at EEPROM Address 040000H.
The correct codes are:
Manufacturers Code -Byte 0
Device Code - Byte 1 F7
1E
AT17LV010
Note:
The Manufacturer’s Code and Device Code are read using the byte ordering specified for
Data Bytes; i.e., LSB first, MSB last.
Programming the Device
All the bytes in a given page must be written. The page access order is not important but
it is suggested that the Configurator be written sequentially from address 0. Writing is
accomplished by using the cSDA and cSCK pins.
Important Note on AT94S Series The first byte of data will not be cached for read back during FPGA Configuration (i.e.,
Configurators Programming
when SER_EN is driven High) until the Configurator is power-cycled.
Verifying the Device
All bytes in the Configurator should be read and compared to their intended values.
Reading is done using the cSDA and cSCK pins.
In-System Programming The AT94S Series Configurators are in-system (re)programmable (ISP). The example
shown on the following page supports the following programmer functions:
Applications
1. Read the Manufacturer’s Code and the Device Code.
2. Program the device.
3. Verify the device data.
While Atmel’s Secure FPSLIC Configurators can be programmed from various sources
(e.g., on-board microcontrollers or PLDs), the applications shown here are designed to
facilitate users of our ATDH2225 Configurator Programming Cable. The typical system
setup is shown in Figure 3.
The pages within the configuration EEPROM can be selectively rewritten.
This document is limited to example implementations for Atmel’s AT94S application.
11
2314D–FPSLI–2/04
Figure 3. Typical System Setup
10-pin
Ribbon
Cable
Target System
Secure
Secure
FPSLIC
FPSLIC
ATDH2225
10
PC
In-System
Programming
Dongle
Programming
Connector
Header
The diode connection between the AT94S’ RESET pin and the SER_EN signal allows
the external programmer to force the FPGA into a reset state during ISP. This eliminates
the potential for contention on the cSCK line. The pull-up resistors required on the lines
to RESET, CON and INIT are present on the inputs (internally) to the AT94S FPSLIC,
see Figure 4.
Figure 4. ISP of the AT17LV512/010 in an AT94S FPSLIC Application
2
cSDA 1
V
CC
4
cSCK 3
6
5
7
9
8
10
GND
AT94S
SER_EN
(SER_EN)
RESET
RESET
DATA0 (cSDA)(1)
CLK (cSCK)(1)
INIT (RESET/OE)(1)
CON (CE)(1)
M2
M0
GND
Note:
1. Configurator signal names are shown in parenthesis.
12
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Figure 5. Serial Data Timing Diagram
tLOW
tHIGH
cSCK
cSDA
cSDA
tHD.STA
tSU.STA
tR
tF
tSU.STO
tSU.DAT
tHD.DAT
tBUF
tAA
tDH
13
2314D–FPSLI–2/04
DC Characteristics(1)
VCC = 3.3V ± 10%, TA = -40°C - 85°C(2)(3)(4)
Symbol
VCC
ICC
Parameter
Test Condition
Min
Typ
3.3
Max
3.6
Units
V
Supply Voltage
3.0
Supply Current
VCC = 3.6
2
3
mA
µA
µA
V
ILL
Input Leakage Current
Output Leakage Current
High-level Input Voltage
Low-level Input Voltage
Output Low-level Voltage
VIN = VCC or VSS
VOUT = VCC or VSS
0.10
0.05
10
ILO
10
VIH
VCC x 0.7
-0.5
VCC + 0.5
0.2
VIL
V
VOL
IOL = 2.1 mA
0.4
V
Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low)
2. Commercial temperature range 0°C - 70°C
3. Industrial temperature range -40°C - 85°C
4. This parameter is characterized and is not 100% tested.
AC Characteristics(1)
VCC = 3.3V ± 10%, TA = -40°C - 85°C(2)(3)(4)
Symbol Parameter
Min
Max
Units
KHz
µs
fCLOCK
tLOW
tHIGH
tAA
Clock Frequency, Clock
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Hold Time
100
4
4
µs
0.1
4.5
2
1
µs
tBUF
µs
tHD;STA
tSU;STA
tHD DAT
tSU DAT
tR
µs
Start Setup Time
2
µs
Data In Hold Time
0
µs
Data In Setup Time
0.2
µs
Inputs Rise Time
0.3
0.3
µs
tF
Inputs Fall Time
µs
tSU STO
tDH
Stop Setup Time
2
µs
Data Out Hold Time
0.1
µs
tWR
Write Cycle Time
20
ms
Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low)
2. Commercial temperature range 0°C - 70°C
3. Industrial temperature range -40°C - 85°C
4. This parameter is characterized and is not 100% tested.
14
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
.
Secure FPSLIC Configurator Pin Configurations
144-pin
LQFP
256-pin
CABGA
Name
I/O
Description
105
107
D16
C16
cSDA
I/O
Three-state DATA output for configuration.
Open-collector bi-directional pin for
programming.
cSCK
O
I
CLOCK output. Used to increment the internal
address and bit counter for reading and
programming.
RESET/O
E
RESET/OE input (when SER_EN is High). A
Low level on both the CE and RESET/OE
inputs enables the data output driver. A High
level on RESET/OE resets both the address
and bit counters. The logic polarity of this input
is programmable as either RESET/OE or
RESET/OE. This document describes the pin
as RESET/OE.
53
72
K9
N16
CE
I
Chip Enable input. Used for device selection
only when SER_EN is High. A Low level on
both CE and OE enables the data output
driver. A High level on CE disables both the
address and bit counters and forces the device
into a low-power mode. Note this pin will not
enable/disable the device in the 2-wire Serial
mode (i.e., when SER_EN is driven Low).
81
M5
SER_EN
I
Serial enable is normally High during FPGA
loading operations. Bringing SER_EN Low
enables the programming mode.
Security Bit
Once the security bit is programmed, data will no longer output from the normal data
pad. Once the fuse is set, any attempt to erase the fuse will cause the configurator to
erase all of it contents.
AT17LV512/010 Security Bit
Programming
Disabling the Security Bit
Enabling the Security Bit
Verifying the Security Bit
Write 4 bytes “00 00 00 00” to addresses 800000-800003 twice, without a power cycle in
between, using the previously defined 2-wire write algorithm.
Write 4 bytes “FF FF FF FF” to addresses 800000-800003 using the previously defined
2-wire write algorithm.
Read 4 bytes of data from addresses 800000-800003 using the previously defined 2-
wire Random Read algorithm. If the data is “FF FF FF FF”, the security bit has been
enabled. If the data is “00 00 00 00”, the security bit has been disabled.
15
2314D–FPSLI–2/04
Chip Erase Timing
The entire device can be erased at once by writing to a specific address. This operation
will erase the entire array. See Table 2 for specifics on the write algorithm.
Table 2. Chip Erase Cycle Characteristics
Symbol
Parameter
Tec
Chip Erase Cycle Time (25 ms)
Figure 6. Chip Erase Timing Diagram
tsu.dat
thigh tlow
SCL
SDA
tnd.dat
ACK
8th BIT
Tec
STOP
START
Condition
Condition
16
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Packaging and
Pin List information
Table 3. Part and Package Combinations Available
Part #
BG256
LQ144
Package
DG
AT94S05
AT94S10
137
AT94S40
162
93
–
BQ
84
84
Table 4. AT94K JTAG ICE Pin List
AT94S05
AT94S10
AT94S40
Pin
96 FPGA I/O
192 FPGA I/O
384 FPGA I/O
TDI
IO34
IO50
IO98
TDO
TMS
TCK
IO38
IO54
IO102
IO43
IO63
IO123
IO44
IO64
IO124
Table 5. AT94S Pin List
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
LQ144(1)
FPSLIC Array
I/O1, GCK1 (A16)
I/O2 (A17)
I/O3
I/O1, GCK1 (A16)
I/O2 (A17)
I/O3
I/O1, GCK1 (A16)
I/O2 (A17)
I/O3
A1
D4
D3
B1
C2
C1
2
3
4
5
6
7
I/O4
I/O4
I/O4
I/O5 (A18)
I/O6 (A19)
I/O5 (A18)
I/O6 (A19)
I/O5 (A18)
I/O6 (A19)
I/O7
I/O8
NC
NC
NC
NC
I/O9
D2
D1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O7
I/O8
NC
I/O7
I/O8
I/O9
I/O15
E3
E4
E2
I/O16
I/O17
17
2314D–FPSLI–2/04
Table 5. AT94S Pin List (Continued)
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
LQ144(1)
NC
I/O10
I/O18
I/O19
E1
I/O20
NC
NC
I/O11
I/O12
I/O21
F4
F3
I/O22
I/O23
I/O24
I/O9, FCK1
I/O10
I/O13, FCK1
I/O14
I/O25, FCK1
I/O26
F1
G7
G6
G4
G5
G2
9
10
11
12
I/O11 (A20)
I/O12 (A21)
NC
I/O15 (A20)
I/O16 (A21)
I/O17
I/O27 (A20)
I/O28 (A21)
I/O29
NC
I/O18
I/O30
I/O31
I/O32
I/O33
I/O34
NC
NC
NC
NC
I/O35
G1
H7
I/O36
I/O37
I/O38
NC
NC
NC
I/O39
H6
H5
H3
H4
H2
H1
NC
I/O40
NC
I/O19
I/O20
I/O21
I/O22
I/O41
NC
I/O42
I/O13
I/O14
I/O43
13
14
I/O44
I/O45
I/O46
I/O15 (A22)
I/O16 (A23)
I/O17 (A24)
I/O18 (A25)
I/O23 (A22)
I/O24 (A23)
I/O25 (A24)
I/O26 (A25)
I/O47 (A22)
I/O48 (A23)
I/O49 (A24)
I/O50 (A25)
I/O51
J7
J1
J4
J5
15
16
19
20
18
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Table 5. AT94S Pin List (Continued)
Package
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
Chip Array 256
CABGA
LQ144(1)
I/O52
I/O53
I/O19
I/O20
NC
I/O27
I/O28
I/O29
I/O30
J6
J8
K1
K2
21
22
I/O54
I/O55
NC
I/O56
I/O57
I/O58
I/O59
I/O60
NC
NC
NC
NC
I/O61
K4
K5
I/O62
I/O63
I/O64
NC
NC
NC
NC
I/O65
K6
L1
L2
L5
L4
M1
M2
N1
I/O66
NC
I/O31
I/O67
NC
I/O32
I/O68
I/O21 (A26)
I/O22 (A27)
I/O23
I/O33 (A26)
I/O34 (A27)
I/O35
I/O69 (A26)
I/O70 (A27)
I/O71
23
24
25
26
I/O24, FCK2
I/O36, FCK2
I/O72, FCK2
I/O73
I/O74
I/O37
I/O38
I/O75
I/O76
I/O77
I/O78
I/O79
I/O80
I/O25
I/O26
I/O39
I/O40
I/O41
I/O42
I/O81
M3
N2
I/O82
I/O83
I/O84
I/O85
19
2314D–FPSLI–2/04
Table 5. AT94S Pin List (Continued)
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
LQ144(1)
I/O86
I/O87
I/O88
I/O27 (A28)
I/O28
I/O43 (A28)
I/O44
I/O89 (A28)
I/O90
P1
P2
28
29
I/O91
I/O92
I/O29
I/O30
I/O45
I/O46
I/O93
R1
N3
T1
P3
R2
R3
30
31
32
33
34
36
I/O94
I/O31 (OTS)
I/O32, GCK2 (A29)
AVRRESET
M0
I/O47 (OTS)
I/O48, GCK2 (A29)
AVRRESET
M0
I/O95 (OTS)
I/O96, GCK2 (A29)
AVRRESET
M0
FPSLIC Array
M2
I/O33, GCK3
I/O34 (HDC/TDI)
I/O35
M2
I/O49, GCK3
I/O50 (HDC/TDI)
I/O51
M2
I/O97, GCK3
I/O98 (HDC/TDI)
I/O99
T3
R4
T4
N5
P5
38
39
40
41
42
43
81
44
I/O36
I/O52
I/O100
I/O53
I/O101
SER_EN
SER_EN
SER_EN
I/O102 (LDC/TDO)
I/O103
M5
R5
I/O38 (LDC/TDO)
I/O54 (LDC/TDO)
I/O104
I/O105
I/O106
NC
NC
NC
I/O107
T5
M6
P6
R6
L6
NC
I/O108
I/O39
I/O40
NC
I/O55
I/O56
I/O57
I/O58
I/O109
I/O110
I/O111
NC
I/O112
T6
I/O113
I/O114
20
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Table 5. AT94S Pin List (Continued)
Package
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
Chip Array 256
CABGA
LQ144(1)
I/O115
I/O116
I/O59
I/O60
I/O117
I/O118
I/O119
I/O120
I/O41
I/O42
I/O61
I/O62
I/O121
M7
N7
P7
R7
K7
K8
46
47
48
49
I/O122
I/O43 (TMS)
I/O44 (TCK)
NC
I/O63 (TMS)
I/O64 (TCK)
I/O65
I/O123 (TMS)
I/O124 (TCK)
I/O125
NC
I/O66
I/O126
I/O127
I/O128
I/O129
I/O130
I/O131
I/O132
I/O133
I/O134
NC
NC
I/O67
I/O68
I/O69
I/O70
I/O135
M8
R8
P8
N8
I/O136
I/O45
I/O46
I/O137
50
51
I/O138
I/O139
I/O140
I/O141
I/O142
I/O47 (TD7)
I/O48 (InitErr) RESET/OE
I/O49 (TD6)
I/O71 (TD7)
I/O72 (InitErr) RESET/OE
I/O73 (TD6)
I/O143 (TD7)
I/O144 (InitErr) RESET/OE
I/O145 (TD6)
I/O146 (TD5)
I/O147
L8
K9
P9
N9
52
53
56
57
I/O50 (TD5)
I/O74 (TD5)
I/O148
21
2314D–FPSLI–2/04
Table 5. AT94S Pin List (Continued)
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
LQ144(1)
I/O149
I/O150
I/O151
I/O152
I/O153
I/O154
I/O155
I/O156
I/O157
I/O158
I/O159
I/O160
I/O161
I/O162
I/O163
I/O164
I/O165 (TD4)
I/O166 (TD3)
I/O167
I/O168
I/O169
I/O170
I/O171
I/O172
I/O173
I/O174
I/O175
I/O176
I/O177
I/O178
I/O179
I/O180
I/O181
I/O182
I/O51
I/O52
NC
I/O75
I/O76
I/O77
I/O78
M9
L9
58
59
J9
NC
T10
NC
NC
I/O79
I/O80
P10
N10
L10
T11
R11
M11
N11
T12
R12
T13
I/O53 (TD4)
I/O54 (TD3)
I/O55
I/O56
NC
I/O81 (TD4)
I/O82 (TD3)
I/O83
60
61
62
63
I/O84
NC
NC
NC
NC
I/O85
NC
I/O86
NC
NC
I/O87
I/O88
I/O89
I/O90
NC
N12
P12
R13
T14
N13
P13
I/O57
I/O58
NC
NC
NC
22
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Table 5. AT94S Pin List (Continued)
Package
AT94S05
96 FPGA I/O
AT94S10
AT94S40
288 FPGA I/O
Chip Array 256
144 FPGA I/O
I/O91 (TD2)
I/O92 (TD1)
CABGA
LQ144(1)
65
I/O59 (TD2)
I/O60 (TD1)
I/O183 (TD2)
I/O184 (TD1)
I/O185
T16
P14
66
I/O186
I/O187
I/O188
I/O61
I/O62
I/O93
I/O94
I/O189
R16
P15
N14
P16
N16
67
68
69
70
72
I/O190
I/O63 (TD0)
I/O64, GCK4
CON/CE
I/O95 (TD0)
I/O96, GCK4
CON/CE
I/O191 (TD0)
I/O192, GCK4
CON/CE
FPSLIC Array
RESET
PE0
RESET
PE0
RESET
PE0
M14
M12
M15
M16
L12
L15
L11
E12
M5
74
75
76
77
78
79
80
PE1
PE1
PE1
PD0
PD0
PD0
PD1
PD1
PD1
PE2
PE2
PE2
PD2
PD2
PD2
NC
NC
NC
SER_EN
PD3
SER_EN
PD3
SER_EN
PD3
81
82
83
84
85
K11
K12
K14
K15
J10
J12
J14
J13
J16
J11
H15
H14
H13
PD4
PD4
PD4
PE3
PE3
PE3
CS0
CS0
CS0
SDA
SDA
SDA
SCL
SCL
SCL
PD5
PD5
PD5
86
87
88
89
92
93
94
PD6
PD6
PD6
PE4
PE4
PE4
PE5
PE5
PE5
PE6
PE6
PE6
PE7 (CHECK)
PD7
PE7 (CHECK)
PD7
PE7 (CHECK)
PD7
23
2314D–FPSLI–2/04
Table 5. AT94S Pin List (Continued)
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
H12
G15
G14
G12
G11
F15
LQ144(1)
INTP0
XTAL1
INTP0
INTP0
XTAL1
95
96
97
98
99
XTAL1
XTAL2
XTAL2
XTAL2
RX0
RX0
RX0
TX0
TX0
TX0
INTP1
INTP1
INTP1
INTP2
INTP2
INTP2
F14
TOSC1
TOSC1
TOSC1
E16
E15
E14
E13
D16
D15
C16
101
102
103
104
105
106
107
TOSC2
TOSC2
TOSC2
RX1
RX1
RX1
TX1
TX1
TX1
DATA0/cSDA
INTP3 (CSOUT)
CCLK/cSCK
I/O65:96 Are Unbonded
DATA0/cSDA
INTP3 (CSOUT)
CCLK/cSCK
I/O97:144 Are Unbonded
DATA0/cSDA
INTP3 (CSOUT)
CCLK/cSCK
I/O193:288 Are Unbonded
FPSLIC Array
Testclock
I/O289 (A0)
I/O290, GCK7 (A1)
I/O291
Testclock
I/O97 (A0)
I/O98, GCK7 (A1)
I/O99
Testclock
I/O145 (A0)
I/O146, GCK7 (A1)
I/O147
C15
C14
B15
A16
D13
109
111
112
113
114
I/O100
I/O148
I/O292
I/O293
I/O294
NC
NC
NC
NC
I/O295
C13
B14
A15
A14
I/O296
I/O101 (CS1, A2)
I/O102 (A3)
I/O149 (CS1, A2)
I/O150 (A3)
I/O297 (CS1, A2)
I/O298 (A3)
I/O299
115
116
I/O300
I/O104
I/O151
I/O301
Shared with Test
clock
NC
I/O103
NC
I/O152
I/O153
I/O154
NC
I/O302
I/O303
I/O304
I/O305
D12
C12
A13
B12
117
NC
24
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Table 5. AT94S Pin List (Continued)
Package
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
Chip Array 256
CABGA
LQ144(1)
I/O306
I/O307
I/O308
NC
NC
I/O155
I/O156
NC
I/O309
A12
E11
C11
D11
A11
F10
E10
D10
C10
B10
I/O310
NC
I/O311
NC
NC
I/O312
I/O105
I/O106
NC
I/O157
I/O158
I/O159
I/O160
NC
I/O313
119
120
I/O314
I/O315
NC
I/O316
NC
I/O317
NC
NC
I/O318
I/O319
I/O320
I/O321
I/O322
I/O323
I/O324
I/O107 (A4)
I/O108 (A5)
NC
I/O161 (A4)
I/O162 (A5)
I/O163
I/O325 (A4)
I/O326 (A5)
I/O327
A10
G10
G9
F9
121
122
NC
I/O164
I/O328
I/O109
I/O110
I/O165
I/O329
E9
123
124
I/O166
I/O330
C9
I/O331
I/O332
I/O333
I/O334
I/O111 (A6)
I/O112 (A7)
I/O113 (A8)
I/O114 (A9)
I/O167 (A6)
I/O168 (A7)
I/O169 (A8)
I/O170 (A9)
I/O335 (A6)
I/O336 (A7)
I/O337 (A8)
I/O338 (A9)
I/O339
B9
A9
A8
B8
125
126
129
130
25
2314D–FPSLI–2/04
Table 5. AT94S Pin List (Continued)
Package
Chip Array 256
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
CABGA
LQ144(1)
I/O340
I/O341
I/O342
I/O115
I/O116
NC
I/O171
I/O172
I/O343
C8
D8
E8
F8
H8
A7
C7
D7
131
132
I/O344
I/O173
I/O345
NC
I/O174
I/O346
I/O117 (A10)
I/O118 (A11)
NC
I/O175 (A10)
I/O176 (A11)
NC
I/O347 (A10)
I/O348 (A11)
I/O349
133
134
NC
NC
I/O350
I/O351
I/O352
I/O353
I/O354
I/O355
I/O356
NC
NC
I/O177
I/O178
I/O179
I/O180
I/O357
F7
A6
F6
B6
I/O358
I/O119
I/O120
I/O359
135
136
I/O360
I/O361
I/O362
NC
NC
I/O181
I/O182
I/O363
D6
E6
I/O364
I/O365
I/O366
I/O367
I/O368
I/O121
I/O122
I/O183
I/O184
I/O369
A5
B5
E5
C5
I/O370
I/O123 (A12)
I/O124 (A13)
I/O185 (A12)
I/O186 (A13)
I/O371 (A12)
I/O372 (A13)
I/O373
138
139
26
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Table 5. AT94S Pin List (Continued)
Package
AT94S05
96 FPGA I/O
AT94S10
144 FPGA I/O
AT94S40
288 FPGA I/O
Chip Array 256
CABGA
LQ144(1)
I/O374
I/O375
I/O376
I/O377
I/O378
NC
NC
I/O187
I/O188
I/O379
A4
B4
A3
C4
B3
A2
I/O380
I/O125
I/O189
I/O381
140
141
142
143
I/O126
I/O190
I/O382
I/O127 (A14)
I/O128, GCK8 (A15)
I/O191 (A14)
I/O192, GCK8 (A15)
I/O383 (A14)
I/O384, GCK8 (A15)
Note:
1. LQ144 is only offered in the AT94S10 and AT94S40.
Table 6. 256 CABGA and LQ144 VDD, VCC and GND Pins(1)
Package
VDD
VCC
GND
B11, B13, B16, B7, C3, C6, D5, D9, F11, F13, T15, F16,
F2, F5, G16, H11, H16, J15, J2, K16, K3, T2, L14, L16,
L7, M4, N15, N4, N6, P11, R9, R10, R15, T8
256
B2, G13, R14, G8, H10, J3,
K13, L3, M10, T7
D14, F12, P4, G3, H9, E7,
K10, L13, M13, T9
CABGA
1, 8, 17, 27, 35, 45, 55, 64, 71, 91, 100, 110, 118, 127,
137
LQ144
90
18, 37, 54, 73, 108, 128, 144
Note:
1. For power rail support for product migration to lower-power devices, refer to the “Designing in Split Power Supply Support for
AT94KAL/AX and AT94SAL/AX Devices” application note (doc2308.pdf), available on the Atmel web site, at
http://www.atmel.com/dyn/products/app_notes.asp?family_id=627.
Thermal Coefficient Table
Theta J-A [°C/W]
Theta J-A [°C/W]
Theta J-A [°C/W]
Package Style
CABGA
Lead Count
256
0 LFPM
225 LFPM
500 LPFM
27
35
23
—
20
—
LQFP
144
27
2314D–FPSLI–2/04
Ordering Information
Usable Gates
Speed Grade
Ordering Code
Package
Operation Range
Commercial
AT94S05AL-25DGC
256ZA
(0°C - 70°C)
5,000
25 MHz
25 MHz
Industrial
AT94S05AL-25DGI
256ZA
(-40°C - 85°C)
AT94S10AL-25DGC
AT94S10AL-25BQC
AT94S10AL-25DGI
AT94S10AL-25BQI
AT94S40AL-25DGC
AT94S40AL-25BQC
AT94S40AL-25DGI
AT94S40AL-25BQI
256ZA
144L1
256ZA
144L1
256ZA
144L1
256ZA
144L1
Commercial
(0°C - 70°C)
10,000
40,000
Industrial
(-40°C - 85°C)
Commercial
(0°C - 70°C)
16 MHz
Industrial
(-40°C - 85°C)
Package Type
256ZA
144L1
256-ball, Chip Array Ball Grid Array Package (CABGA)
144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP)
28
AT94S Secure Family
2314D–FPSLI–2/04
AT94S Secure Family
Packaging Information
256ZA – CABGA
D
A2
b
A1 Ball Pad Corner
E
A1
Top View
A
A3
Side View
A1 Ball Pad Corner
16 15 14 1312 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
e
COMMON DIMENSIONS
(Unit of Measure = mm)
G
H
J
K
L
M
N
P
R
T
MIN
–
MAX
–
NOM
17 BSC
17 BSC
1.40
NOTE
SYMBOL
D
E
–
–
A
1.30
0.31
0.29
0.65
1.50
0.41
0.39
0.75
A1
A2
A3
e
0.36
0.34
0.70
1.00 REF
e
1.00 BSC
0.46 REF
Bottom View
b
(256 SOLDER BALLS)
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-205 for proper dimensions, tolerances, datums, etc.
2. Array as seen from the bottom of the package.
11/07/01
DRAWING NO.
REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
256ZA, 256-ball (16 x 16 Array), 17 x 17 mm Body,
Chip Array Ball Grid Array (CABGA) Package
256ZA
A
R
29
2314D–FPSLI–2/04
144L1 – LQFP
D1
D
XX
e
E1
E
N
b
Bottom View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
1.35
MAX
0.15
1.45
NOM
NOTE
SYMBOL
A1
A2
D
6
A2
1.40
22.00 BSC
20.00 BSC
22.00 BSC
20.00 BSC
0.50 BSC
0.22
A1
D1
E
2, 3
2, 3
4, 5
L1
Side View
E1
e
b
0.17
0.27
L1
1.00 REF
1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
Notes:
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
11/30/01
TITLE
144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile
Plastic Quad Flat Pack (LQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
144L1
A
R
30
AT94S Secure Family
2314D–FPSLI–2/04
Atmel Corporation
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Tel: 1(408) 441-0311
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
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© Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof, AVR®, and Cache Logic® are the registered trademarks,
and FPSLIC™, Secure FPSLIC™, FreeRAM™, System Designer™ and megaAVR™ are the trademarks of Atmel Corporation or its subsidiaries.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2314D–FPSLI–2/04
xM
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