AT93C56A_08 [ATMEL]
Three-wire Serial EEPROM 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16); 三线制串行EEPROM 2K （ 256× 8或128 ×16 ）的4K （ 512 ×8或256 ×16 ）
| 型号： | AT93C56A_08 |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Serial EEPROM 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16) |
| 文件： | 总21页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1. Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• Sequential Read Operation
Three-wire
Serial
EEPROM
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms Max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP and 8-ball
dBGA2 Packages
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
2. Description
AT93C56A
AT93C66A
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-
lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead Ultra Lead Frame Land
Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages.
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
3378M–SEEPR–7/08
Table 2-1.
Pin Name
CS
Pin Configurations
Function
8-lead SOIC
8-ball dBGA2
8
7
6
5
1
2
3
4
CS
SK
DI
1
8
7
6
5
VCC
NC
ORG
GND
VCC
NC
ORG
GND
CS
SK
DI
2
3
4
Chip Select
DO
DO
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Bottom view
8-lead Ultra Thin mini-MAP (MLP 2x3)
DI
8-lead PDIP
DO
VCC 8
NC 7
ORG 6
GND 5
1 CS CS
2 SK
3 DI
1
8
7
6
5
VCC
NC
ORG
GND
SK
DI
2
3
4
GND
VCC
ORG
NC
4 DO DO
Power Supply
Internal Organization
No Connect
Bottom view
8-lead Ultra Lead Frame
Land Grid Array (ULA)
8-lead TSSOP
CS
SK
DI
1
8
7
6
5
VCC
NC
ORG
GND
2
3
4
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
DO
4 DO
Bottom view
3. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
2
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
Figure 3-1. Block Diagram
Note:
When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
3
3378M–SEEPR–7/08
Table 3-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Pin Capacitance(Note:)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3-2.
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
CC = +1.8V to +5.5V (unless otherwise noted)
DC Characteristics
V
Symbol
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Unit
V
VCC1
VCC2
VCC3
Supply Voltage
Supply Voltage
Supply Voltage
5.5
V
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
0.4
6.0
10.0
0.1
0.1
2.0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V
1.0
VCC = 2.7V
CS = 0V
10.0
15.0
3.0
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
IOL
Output Leakage
3.0
(Note:)
VIL1
VIH1
Input Low Voltage
Input High Voltage
−0.6
2.0
0.8
VCC + 1
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
V
V
(Note:)
(Note:)
(Note:)
VIL2
Input Low Voltage
Input High Voltage
−0.6
CC x 0.7
VCC x 0.3
VCC + 1
VIH2
V
I
I
I
OL = 2.1 mA
OH = −0.4 mA
OL = 0.15 mA
0.4
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
2.4
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
1.8V ≤ VCC ≤ 2.7V
IOH = −100 µA
VCC − 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
Table 3-3.
AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
SK Clock
Frequency
fSK
MHz
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
Minimum CS
Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
200
tCSS
CS Setup Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tPD1
tPD0
tSV
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
CS to DO in High
Impedance
AC Test
CS = VIL
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
150
400
tDF
tWP
Write Cycle Time
5.0V, 25°C
1.8V ≤ VCC ≤ 5.5V
0.1
1M
3
10
ms
(Note:)
Endurance
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5
3378M–SEEPR–7/08
Table 3-4.
Instruction Set for the AT93C56A and AT93C66A
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address.
READ
1
10
A8 – A0
A7 – A0
Write enable must precede all
programming modes.
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
WRITE
1
1
11
01
A8 – A0
A8 – A0
A7 – A0
A7 – A0
Erases memory location An – A0.
Writes memory location An – A0.
D7 – D0
D15 – D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
ERAL
1
00
10XXXXXXX
10XXXXXX
Writes all memory locations. Valid
only at VCC = 5.0V 10% and Disable
Register cleared.
WRAL
EWDS
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
D7 – D0
D15 – D0
Disables all programming instructions.
Note:
The X’s in the address field represent don’t care values and must be clocked.
6
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
4. Functional Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host processor. A
valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed
by the appropriate Op Code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory loca-
tion to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string. The AT93C56A/66A supports sequential read operations. The device
will automatically increment the internal address pointer and clock out the next memory location
as long as Chip Select (CS) is held high. In this case, the dummy bit (logic “0”) will not be
clocked out between memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-
tion is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase instruction programs all bits in the specified memory location to
the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address
are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the selected
memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle tWP starts after the last bit
of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the READ instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
7
3378M–SEEPR–7/08
5. Timing Diagrams
Figure 5-1. Synchronous Data Timing
Note:
1. This is the minimum SK period.
Table 5-1.
Organization Key for Timing Diagrams
AT93C56A (2K)
AT93C66A (4K)
I/O
AN
DN
x 8
x 16
x 8
x 16
A7
(1)
(2)
A8
D7
A7
A8
D7
D15
D15
Notes: 1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
Figure 5-2. READ Timing
tCS
CS
SK
DI
High Impedance
DO
8
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
Figure 5-3. EWEN Timing
tCS
tCS
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 5-4. EWDS Timing
CS
SK
DI
...
0
0
0
1
0
Figure 5-5. WRITE Timing
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
9
3378M–SEEPR–7/08
Figure 5-6. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 5-7. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
10
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
Figure 5-8. ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
11
3378M–SEEPR–7/08
6. AT93C56A Ordering Information(1)
Ordering Code
Package
Operation Range
AT93C56A-10PU-2.7(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8D3
8Y1
8Y6
AT93C56A-10PU-1.8(2)
AT93C56A-10SU-2.7(2)
AT93C56A-10SU-1.8(2)
AT93C56AW-10SU-2.7(2)
AT93C56AW-10SU-1.8(2)
AT93C56A-10TU-2.7(2)
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT93C56A-10TU-1.8(2)
AT93C56AU3-10UU-1.8(2)
AT93C56AD3-10DH-1.8(3)
AT93C56AY1-10YU-1.8(2) (Not recommended for new design)
AT93C56AY6-10YH-1.8(3)
Industrial Temperature
AT93C56A-W1.8-11(4)
Die Sales
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Marketing.
Package Type
8P3
8S1
8S2
8A2
8U3-1
8Y1
8Y6
8D3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, die Ball Grid Array Package (dBGA2)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA)
Options
Low-voltage (2.7V to 5.5V)
−2.7
−1.8
Low-voltage (1.8V to 5.5V)
12
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
7. AT93C66A Ordering Information(1)
Ordering Code
Package
Operation Range
AT93C66A-10PU-2.7(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8D3
8Y1
8Y6
AT93C66A-10PU-1.8(2)
AT93C66A-10SU-2.7(2)
AT93C66A-10SU-1.8(2)
AT93C66AW-10SU-2.7(2)
AT93C66AW-10SU-1.8(2)
AT93C66A-10TU-2.7(2)
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT93C66A-10TU-1.8(2)
AT93C66AU3-10UU-1.8(2)
AT93C66AD3-10DH-1.8(3)
AT93C66AY1-10YU-1.8(2) (Not recommended for new design)
AT93C66AY6-10YH-1.8(3)
Industrial Temperature
AT93C66A-W1.8-11(4)
Die Sale
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8S1
8S2
8A2
8U3-1
8Y1
8Y6
8D3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, die Ball Grid Array Package (dBGA2)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA)
Options
Low-voltage (2.7V to 5.5V)
−2.7
−1.8
Low-voltage (1.8V to 5.5V)
13
3378M–SEEPR–7/08
8. Packaging Information
8.1
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
8.2
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
8.3
8S2 – EIAJ SOIC
15
3378M–SEEPR–7/08
8.3
8Y6 - Mini-MAP (MLP 2x3)
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
C
R
16
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
8.4
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
3378M–SEEPR–7/08
8.5
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
Side View
PIN 1 BALL PAD CORNER
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
NOTE
MIN
MAX
0.85
0.19
0.50
0.30
NOM
SYMBOL
Bottom View
A
0.713
0.09
0.40
0.20
0.79
8 Solder Balls
A1
A2
b
0.14
0.45
0.25
2
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter
E
e
e1
d
d1
5/3/05
TITLE
REV.
DRAWING NO.
1150E Cheyenne Mt. Blvd
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
PO8U3-1
b
R
18
AT93C56A/66A
3378M–SEEPR–7/08
AT93C56A/66A
8.6
8D3 - ULA
D
e1
b
7
5
6
8
L
E
PIN #1 ID
0.10
0.15
PIN #1 ID
A1
2
4
1
3
b
e
A
BOTTOM VIEW
SIDE VIEW
TOP VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.40
0.05
1.90
2.30
0.25
NOM
–
NOTE
A
A1
D
E
0.00
1.70
2.10
0.15
–
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.25
0.35
11/15/05
TITLE
DRAWING NO.
8D3
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULLGA) D3
0
R
19
3378M–SEEPR–7/08
9. Revision History
Revision No.
Date
Comments
3378M
7/2008
Updated Ordering Codes
Updated to new template
3378L
11/2007
12/2006
Added ULA package offering
Removed DC/Don’t Connect and replaced with NC/No Conenct
Adjusted size of Block diagram on pg. 2
3378K
Made all diagrams on pages 6-9 consistently the same size
Corrected 8U3-1
20
AT93C56A/66A
3378M–SEEPR–7/08
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3378M–SEEPR–7/08
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