AT93C56B-XHM-T [ATMEL]
Three-wire Serial Electrically Erasable Programmable Read-only Memory; 三线串行电可擦除可编程只读存储器
| 型号： | AT93C56B-XHM-T |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Serial Electrically Erasable Programmable Read-only Memory |
| 文件： | 总21页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and standard-voltage operation
– VCC = 1.7V to 5.5V
• User-selectable internal organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire serial interface
• Sequential read operation
• 2MHz clock rate (5V)
• Self-timed write cycle (5ms max)
• High reliability
Three-wire
Serial Electrically
Erasable
– Endurance: One million write cycles
– Data retention: 100 years
Programmable
Read-only Memory
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
• 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, and 8-ball VFBGA
packages
Description
The Atmel® AT93C56B/66B provides 2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and commer-
cial applications where low-power and low-voltage operations are essential. The
AT93C56B/66B is available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
UDFN, 8-lead XDFN, and 8-ball VFBGA packages.
Atmel AT93C56B
Atmel AT93C66B
The AT93C56B/66B is enabled through the chip select pin (CS) and accessed via a
three-wire serial interface consisting of data input (DI), data output (DO), and shift clock
(SK). Upon receiving a read instruction at DI, the address is decoded and the data is clocked
out serially on the data output pin, DO. The write cycle is completely self-timed, and no sep-
arate erase cycle is required before write. The write cycle is only enabled when the part is in
the erase/write enable state. When CS is brought high following the initiation of a write
cycle, the DO pin outputs the ready/busy status of the part.
The AT93C56B/66B operates from 1.7V to 5.5V.
8-lead SOIC
8-lead TSSOP
Figure 0-1.
Pin Configurations
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
CS
SK
DI
1
8
7
6
5
VCC
NC
2
3
4
ORG
GND
ORG
GND
Pin Name
CS
Function
DO
DO
Chip Select
8-lead UDFN
8-lead XDFN
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
VCC
CS
SK
DI
VCC
CS
DI
NC
ORG
GND
NC
ORG
GND
SK
DI
DO
DO
DO
GND
VCC
ORG
NC
8-ball VFBGA
Bottom view
Bottom view
Power Supply
Internal Organization
No Connect
8
7
6
5
1
2
3
4
CS
SK
DI
VCC
NC
ORG
GND
DO
8735A–SEEPR–1/11
Bottom view
1.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Operating Temperature55C to +125C
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground 1.0V to +7.0V
Maximum Operating Voltage. . . . . . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0mA
Figure 1-1.
Block Diagram
VCC
GND
MEMORY ARRAY
ADDRESS
DECODER
256/512 x 8
or
ORG
128/256 x 16
DATA
REGISTER
OUTPUT
BUFFER
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
SK
DO
Note:
When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal
1M pull-up resistor, then the x 16 organization is selected.
Atmel AT93C56B/66B
2
8735A–SEEPR–1/11
Atmel AT93C56B/66B
Table 1-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Notes: 1. This parameter is characterized, and is not 100% tested
Table 1-2.
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
1.7
2.5
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
Supply Voltage
VCC2
5.5
V
VCC3
5.5
V
READ at 1.0MHz
WRITE at 1.0MHz
CS = 0V
0.5
0.5
0.4
6.0
10.0
0.1
0.1
2.0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.7V
1.0
VCC = 2.5V
CS = 0V
10.0
15.0
3.0
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
IOL
Output Leakage
3.0
(1)
VIL1
Input Low Voltage
Input High Voltage
0.6
2.0
0.8
CC + 1
2.5V VCC 5.5V
1.7V VCC 2.5V
V
V
(1)
V
VIH1
(1)
VIL2
Input Low Voltage
Input High Voltage
0.6
CC x 0.7
VCC x 0.3
CC + 1
(1)
V
V
VIH2
IOL = 2.1mA
0.4
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.5V VCC 5.5V
1.7V VCC 2.5V
IOH = 0.4mA
IOL = 0.15mA
IOH = 100µA
2.4
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC 0.2
Notes: 1. VIL min and VIH max are reference only, and are not tested
3
8735A–SEEPR–1/11
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = 40°C to + 85°C, VCC = as specified, CL = 1 TTL gate and 100pF
(unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V VCC 5.5V
2.5V VCC 5.5V
1.7V VCC 5.5V
0
0
0
2
1
0.25
fSK
SK Clock Frequency
MHz
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
tSKH
tSKL
tCS
SK High Time
ns
ns
ns
ns
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
SK Low Time
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
Minimum CS Low Time
CS Setup Time
2.5V VCC 5.5V
1.7V VCC 5.5V
50
200
tCSS
Relative to SK
2.5V VCC 5.5V
1.7V VCC 5.5V
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
2.5V VCC 5.5V
1.7V VCC 5.5V
100
400
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
tPD1
tPD0
tSV
Output Delay to 1
Output Delay to 0
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
2.5V VCC 5.5V
1.7V VCC 5.5V
250
1000
CS to DO in
AC Test
CS = VIL
2.5V VCC 5.5V
1.7V VCC 5.5V
150
400
tDF
ns
High Impedance
tWP
Write Cycle Time
1.7V VCC 5.5V
5
ms
Write
Cycles
Endurance(1) 5.0V, 25°C
1,000,000
Notes: 1. This parameter is characterized, and is not 100% tested
Atmel AT93C56B/66B
4
8735A–SEEPR–1/11
Atmel AT93C56B/66B
Table 1-4.
Instruction Set for the Atmel AT93C56B and Atmel AT93C66B
Address
Data
Op
Instruction
READ
SB Code
x 8
A8 – A0
x 16
x 8
x 16
Comments
1
1
1
1
10
00
11
01
A7 – A0
Reads data stored in memory at specified address
Write enable must precede all programming modes
Erases memory location An – A0
EWEN
11XXXXXXX 11XXXXXX
ERASE
WRITE
A8 – A0
A8 – A0
A7 – A0
A7 – A0
D7 – D0
D15 – D0
Writes memory location An – A0
Erases all memory locations. Valid only at
ERAL
1
00
10XXXXXXX 10XXXXXX
V
CC = 4.5V to 5.5V
Writes all memory locations. Valid only at
WRAL
EWDS
1
1
00
00
01XXXXXXX 01XXXXXX
00XXXXXXX 00XXXXXX
D7 – D0
D15 – D0
V
CC = 5.0V 10% and disable register cleared
Disables all programming instructions
Note:
The Xs in the address field represent “don’t care” values, and must be clocked
2.
Functional Description
The Atmel® AT93C56B/66B is accessed via a simple and versatile three-wire serial communication interface. Device
operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of
CS, and consists of a start bit (logic one) followed by the appropriate op code and the desired memory address location.
READ (READ): The read (READ) instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial output pin, DO.
Output data changes are synchronized with the rising edges ofthe serial clock, SK. It should be noted that a dummy bit
(logic zero) precedes the 8- or 16-bit data output string. The AT93C56B/66B supports sequential read operations. The
device will automatically increment the internal address pointer and clock out the next memory location as long as chip
select (CS) is held high. In this case, the dummy bit (logic zero) will not be clocked out between memory locations, thus
allowing for a continuous stream of data to be read.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the erase/write disable
(EWDS) state when power is first applied. An erase/write enable (EWEN) instruction must be executed first before any
programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until
an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The erase (ERASE) instruction programs all bits in the specified memory location to the logical-one
state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (tCS). A logic one at pin DO
indicates that the selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8- or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO
pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (tCS). A
logic zero at DO indicates that programming is still in progress. A logic one indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part is ready for further
instructions. A ready/busy status cannot be obtained if CS is brought high after the end of the self-timed programming
cycle, tWP
.
ERASE ALL (ERAL): The erase all (ERAL) instruction programs every bit in the memory array to the logic one state, and
is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being
kept low for a minimum of 250ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
5
8735A–SEEPR–1/11
WRITE ALL (WRAL): The write all (WRAL) instruction programs all memory locations with the data patterns specified in
the instruction. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a
minimum of 250ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the erase/write disable (EWDS)
instruction disables all programming modes, and should be executed after all programming operations. The operation of the
READ instruction is independent of both the EWEN and EWDS instructions, and can be executed at any time.
3.
Timing Diagrams
Figure 3-1.
Synchronous Data Timing
Note:
1. This is the minimum SK period
Table 3-1.
Organization Key for Timing Diagrams
Atmel AT93C56B (2K)
Atmel AT93C66B (4K)
I/O
AN
DN
x 8
x 16
x 8
A8
x 16
A7
(1)
(2)
A8
D7
A7
D15
D7
D15
Notes: 1. A8 is a don’t-care value, but the extra clock is required
2. A7 is a don’t-care value, but the extra clock is required
Atmel AT93C56B/66B
6
8735A–SEEPR–1/11
Atmel AT93C56B/66B
Figure 3-2.
READ Timing
CS
CS
S
Figure 3-3.
EWEN Timing
CS
CS
S
1
1
1
Figure 3-4.
EWDS Timing
CS
CS
S
1
7
8735A–SEEPR–1/11
Figure 3-5.
WRITE Timing
CS
CS
S
A
1
1
A
PE A CE
S
REA
P
Figure 3-6.
WRAL Timing(1)
CS
CS
S
1
1
S
PE A CE
REA
P
Note:
1. Valid only at VCC = 4.5V to 5.5V
Atmel AT93C56B/66B
8
8735A–SEEPR–1/11
Atmel AT93C56B/66B
Figure 3-7.
ERASE Timing
CS
CS
S
SA
C EC
SA S
A
1
1
1
A
A
A
1
S
PE A CE
PE A CE
S
REA
P
Figure 3-8.
ERAL Timing(1)
CS
CS
S
SA
C EC
SA S
1
1
S
S
PE A CE
PE A CE
REA
P
Note:
1. Valid only at VCC = 4.5V to 5.5V
9
8735A–SEEPR–1/11
4.
Ordering Code Detail
A T 9 3 C 5 6 B - S S H M - B
Atmel Designator
Product Family
Device Density
Shipping Carrier Option
B or blank = Bulk (tubes)
T
= Tape and reel
Operating Voltage
M = 1.7V to 5.5V
Package Device Grade or
56 = 2k
66 = 4k
Wafer/Die Thickness
H = Green, NiPdAu lead finish
Industrial Temperature range
(-40°C to +85°C)
U = Green, matte Sn lead finish
Industrial Temperature range
(-40°C to +85°C)
Device Revision
11 = 11mil wafer thickness
Package Option
SS
X
= JEDEC SOIC
= TSSOP
MA = UDFN
ME = XDFN
C
= VFBGA
WWU = Wafer unsawn
Atmel AT93C56B/66B
10
8735A–SEEPR–1/11
Atmel AT93C56B/66B
5.
Part Markings
5.1
Atmel AT93C56B
8 lead TSSOP
3 Rows
8 lead SOIC
3 Rows of 8 Characters
2 of 6 and 1 of 7 Characters
ATHYWW
56BM @
AAAAAAA
ATMLHYWW
56BM
@
AAAAAAAA
8 lead XDFN - 1.8x2.2mm
2 Rows of 3 Characters
56B
YXX
8-ball VFBGA - 2.35x3.73mm
8 lead UDFN -2.0x3.0mm
2 Rows
3 Rows of 3 Characters
1 of 4 and 1 of 5 Characters
56B
HM@
YXX
PIN 1
56BU
@YMXX
PIN 1
PIN 1
Catalog Truncation: 56B
Catalog Number: AT93C56B
Date Codes
Voltages
Y = Year
0: 2010
1: 2011
2: 2012
3: 2013
M = Month
A: January
B: February
WW = Work Week of Assembly
02: Week 2
04: Week 4
Blank: 2.7v min
D: 2.5v min
L: 1.8v min
M: 1.7v min
P: 1.5v min
4: 2014
5: 2015
6: 2016
7: 2017
“
”
“
”
“
”
L: December
52: Week 52
Trace Code
Grade/Lead Finish Material
XX = Trace Code (ATMEL Lot Numbers to Correspond to Code)
(e.g. XX:
AA, AB...YZ, ZZ)
U: Industrial/Matt Tin
H: Industrial/NiPdAu
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
ATMEL Truncation
Country of Assembly
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
@ = Country of Assembly
B = PHILIPPINES
W = THAILAND
Q = MALAYSIA
H,Y = CHINA
1/12/11
DRAWING NO. REV.
93C56BSM
TITLE
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
93C56BSM, AT93C56B Standard Marking Information
for Package Offering
A
11
8735A–SEEPR–1/11
5.2
Atmel AT93C66B
8 lead SOIC
8 lead TSSOP
3 Rows
3 Rows of 8 Characters
2 of 6 and 1 of 7 Characters
ATHYWW
66BM @
AAAAAAA
ATMLHYWW
66BM
@
AAAAAAAA
8 lead XDFN - 1.8x2.2mm
2 Rows of 3 Characters
66B
YXX
8-ball VFBGA -2.35x3.73mm 8 lead UDFN - 2.0x3.0mm
3 Rows of 3 Characters
2 Rows
1 of 4 and 1 of 5 Characters
PIN 1
66B
HM@
YXX
66BU
@YMXX
PIN 1
PIN 1
Catalog Truncation: 66B
Catalog Number: AT93C66B
Date Codes
Voltages
Y = Year
0: 2010
1: 2011
2: 2012
3: 2013
M = Month
A: January
B: February
WW = Work Week of Assembly
02: Week 2
04: Week 4
Blank: 2.7v min
D: 2.5v min
L: 1.8v min
M: 1.7v min
P: 1.5v min
4: 2014
5: 2015
6: 2016
7: 2017
“
”
“
”
“
”
L: December
52: Week 52
Trace Code
Grade/Lead Finish Material
XX = Trace Code (ATMEL Lot Numbers to Correspond to Code)
(e.g. XX:
AA, AB...YZ, ZZ)
U: Industrial/Matt Tin
H: Industrial/NiPdAu
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
ATMEL Truncation
Country of Assembly
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
@ = Country of Assembly
B = PHILIPPINES
W = THAILAND
Q = MALAYSIA
H,Y = CHINA
1/12/11
DRAWING NO. REV.
TITLE
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
93C66BSM, AT93C66B Standard Marking Information
for Package Offering
93C66BSM
A
Atmel AT93C56B/66B
12
8735A–SEEPR–1/11
Atmel AT93C56B/66B
5.3
Atmel AT93C56B Ordering Information
Atmel Ordering Code
Voltage
Package
Operation Range
AT93C56B-SSHM-B(1) (NiPdAu Lead Finish)
AT93C56B-SSHM-T(2) (NiPdAu Lead Finish)
AT93C56B-XHM-B(1) (NiPdAu Lead Finish)
AT93C56B-XHM-T(2) (NiPdAu Lead Finish)
AT93C56B-MAHM-T(2) (NiPdAu Lead Finish)
AT93C56B-MEHM-T(2) (NiPdAu Lead Finish)
AT93C56B-CUM-T(2) (NiPdAu Lead Finish)
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
8S1
8S1
8A2
Lead-free/Halogen-free/
Industrial Temperature
8A2
(40C to 85C)
8Y6
8ME1
8U3-1
Industrial Temperature
AT93C56B-WWU11M
1.7 to 5.5
Die Sale
(40C to 85C)
Notes: 1. "-B" denotes bulk delivery
2. "-T" denotes tape and reel delivery. SOIC = 4k/reel. TSSOP UDFN, XDFN, and VFBGA = 5k/reel
3. For wafer sales, please contact Atmel sales
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing, Small OutlinePackage (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8A2
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Dual No Lead Package (UDFN)
8-lead, 1.80mm x 2.20mm Body (XDFN)
8ME1
8U3-1
8-ball, 1.50mm x 2.00mm Body, 0.50mm Pitch, Small Die Ball Grid Array (VFBGA)
13
8735A–SEEPR–1/11
5.4
Atmel AT93C66B Ordering Information
Atmel Ordering Code
Voltage
Package
Operation Range
AT93C66B-SSHM-B(1) (NiPdAu Lead Finish)
AT93C66B-SSHM-T(2) (NiPdAu Lead Finish)
AT93C66B-XHM-B(1) (NiPdAu Lead Finish)
AT93C66B-XHM-T(2) (NiPdAu Lead Finish)
AT93C66B-MAHM-T(2) (NiPdAu Lead Finish)
AT93C66B-MEHM-T(2) (NiPdAu Lead Finish)
AT93C66B-CUM-T(2) (NiPdAu Lead Finish)
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
8S1
8S1
8A2
Lead-free/Halogen-free/
Industrial Temperature
8A2
(40C to 85C)
8Y6
8ME1
8U3-1
Industrial Temperature
AT93C56B-WWU11M
1.7 to 5.5
Die Sale
(40C to 85C)
Notes: 1. "-B" denotes bulk delivery
2. "-T" denotes tape and reel delivery. SOIC = 4k/reel. TSSOP UDFN, XDFN, and VFBGA = 5k/reel
3. For wafer sales, please contact Atmel sales
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing, Small Outline Package (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8A2
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Dual No Lead Package (UDFN)
8-lead, 1.80mm x 2.20mm Body (XDFN)
8ME1
8U3-1
8-ball, 1.50mm x 2.00mm Body, 0.50mm Pitch, Small Die Ball Grid Array (VFBGA)
Atmel AT93C56B/66B
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8735A–SEEPR–1/11
Atmel AT93C56B/66B
6.
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
–
D
–
–
–
SIDEE VIEW
e
1.27 BSC
Notes: This drawing is for general information only.
L
0.40
0°
–
–
1.27
8°
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
Ø
5/19/10
REV.
TITLE
GPC
SWB
DRAWING NO.
8S1
Package Drawing Contact:
packagedrawings@atmel.com
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
F
15
8735A–SEEPR–1/11
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
2.90
MAX
3.10
NOM
3.00
NOTE
2, 5
SYMBOL
D
A
E
6.40 BSC
4.30
b
E1
A
4.40
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
1.00
e
A2
0.19
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/19/10
REV.
TITLE
GPC
TNR
DRAWING NO.
8A2
Package Drawing Contact:
8A2, 8-lead 4.4mm Body, Plastic Thin
E
packagedrawings@atmel.com
Shrink Small Outline Package (TSSOP)
Atmel AT93C56B/66B
16
8735A–SEEPR–1/11
Atmel AT93C56B/66B
8Y6 – UDFN
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A1
A2
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
2.00 BSC
3.00 BSC
1.50
MAX
NOTE
D
E
1.60
1.40
0.60
0.05
0.55
D2
E2
A
1.40
–
Notes: 1. This drawing is for general information only. Refer to JEDEC
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
–
–
–
2. Dimension b applies to metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip. If the
terminal has the optional radius on the other end of the
terminal, the dimension should not be measured in that
radius area.
3. Soldering the large thermal pad is optional, but not
recommended. No electrical connection is accomplished to
the device through this pad, so if soldered it should be tied
to ground
A1
A2
A3
L
0.00
–
0.02
–
0.20 REF
0.30
0.40
0.30
0.20
0.20
e
0.50 BSC
0.25
2
b
11/21/08
REV.
TITLE
GPC
YNZ
DRAWING NO.
8Y6
Package Drawing Contact:
packagedrawings@atmel.com
8Y6, 8-lead, 2.0x3.0mm Body, 0.50mm Pitch,
UltraThin Mini-MAP, Dual No Lead Package
(Sawn)(UDFN)
E
17
8735A–SEEPR–1/11
8ME1 – XDFN
e1
D
b
8
7
6
5
L
E
PIN #1 ID
0.10
PIN #1 ID
0.15
1
2
3
4
A1
b
e
A
Top View
Side View
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
NOM
–
MAX
0.40
0.05
1.90
2.30
0.25
NOTE
A
A1
D
E
0.00
1.70
2.10
0.15
–
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.35
0.26
8/3/09
TITLE
GPC
DTP
DRAWING NO.
8ME1
REV.
A
8ME1, 8-lead (1.80 x 2.20mm Body)
Extra Thin DFN (XDFN)
Package Drawing Contact:
packagedrawings@atmel.com
Atmel AT93C56B/66B
18
8735A–SEEPR–1/11
Atmel AT93C56B/66B
8U3-1 – VFBGA
E
D
5.
b
1
A
PIN 1 BALL PAD CORNER
2
A
A
TOP VIEW
SIDE VIEW
PIN 1 BALL PAD CORNER
2
4
1
3
d
(d1)
6
5
8
7
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
A
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
BOTTOM VIEW
8 SOLDER BALLS
A1
A2
b
0.14
0.45
Notes:
0.25
2
1. This drawing is for general information only.
D
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
E
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
07/14/10
TITLE
GPC
DRAWING NO.
8U3-1
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1, 8-ball, 1.50 x 2.00 mm Body,
0.50 pitch, VFBGA Package (dBGA2)
GXU
D
19
8735A–SEEPR–1/11
7.
Revision History
Revision No.
Date
Comments
8735A
01/2011
Initial document release
Atmel AT93C56B/66B
20
8735A–SEEPR–1/11
Atmel Corporation
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© 2011 Atmel Corporation. All rights reserved. / Rev.: 8735A–SEEPR–1/11
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