概述
规格参数
数据手册
替代型号AT91R40008-66AI 概述
AT91 ARM Thumb Microcontroller AT91 ARM的Thumb微控制器 微控制器 微控制器
AT91R40008-66AI 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | QFP | 包装说明： | LFQFP, QFP100,.63SQ,20 |
| 针数： | 100 | Reach Compliance Code： | unknown |
| ECCN代码： | 3A001.A.3 | HTS代码： | 8542.31.00.01 |
| 风险等级： | 5.32 | 具有ADC： | NO |
| 地址总线宽度： | 24 | 位大小： | 32 |
| CPU系列： | ARM7 | 最大时钟频率： | 66 MHz |
| DAC 通道： | NO | DMA 通道： | NO |
| 外部数据总线宽度： | 16 | JESD-30 代码： | S-PQFP-G100 |
| JESD-609代码： | e0 | 长度： | 14 mm |
| 湿度敏感等级： | 1 | I/O 线路数量： | 32 |
| 端子数量： | 100 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | PWM 通道： | NO |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | LFQFP |
| 封装等效代码： | QFP100,.63SQ,20 | 封装形状： | SQUARE |
| 封装形式： | FLATPACK, LOW PROFILE, FINE PITCH | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 1.8,3.3 V | 认证状态： | Not Qualified |
| RAM（字节）： | 262144 | ROM（单词）： | 0 |
| ROM可编程性： | FLASH | 座面最大高度： | 1.6 mm |
| 速度： | 66 MHz | 子类别： | Microcontrollers |
| 最大供电电压： | 1.95 V | 最小供电电压： | 1.65 V |
| 标称供电电压： | 1.8 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | GULL WING |
| 端子节距： | 0.5 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 14 mm |
| uPs/uCs/外围集成电路类型： | MICROCONTROLLER, RISC | Base Number Matches： | 1 |
AT91R40008-66AI 数据手册
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PDF下载Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Little-endian
– Embedded ICE (In-circuit Emulation)
• 8-, 16- and 32-bit Read and Write Support
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
AT91 ARM®
Thumb®
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to Eight Chip Selects
– Software Programmable 8/16-bit External Data Bus
• Eight-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, including a High-priority, Low-latency Interrupt Request
• 32 Programmable I/O Lines
Microcontroller
• Three-channel 16-bit Timer/Counter
– Three External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
• Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
• Fully Static Operation:
AT91R40008
Summary
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85°C
• 2.7V to 3.6V I/O Operating Range
• 1.65V to 1.95V Core Operating Range
• -40°C to +85°C Temperature Range
• Available in 100-lead TQFP Package
Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16/32-bit microcon-
troller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set
and very low power consumption. Furthermore, it features 256K bytes of on-chip
SRAM and a large number of internally banked registers, resulting in very fast excep-
tion handling, and making the device ideal for real-time control applications.
The AT91R40008 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully programmable External Bus Interface (EBI). An 8-
level priority vectored interrupt controller, in conjunction with the Peripheral Data Con-
troller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combin-
ing the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a
wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful
microcontroller that offers a flexible and high-performance solution to many compute-
intensive embedded control applications.
1732DS–ATARM–03/04
Note: This is a summary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.
Pin Configuration
Figure 1. AT91R40008 in 100-lead TQFP Package
P22/RXD1
NWR1/NUB
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1/TIOA0
P0/TCLK0
D15
NRST
D14
NWDOVF
D13
D12
VDDIO
MCKI
VDDIO
D11
P23
P24/BMS
P25/MCKO
GND
D10
D9
D8
GND
D7
TMS
D6
TDI
D5
TDO
GND
TCK
D4
NRD/NOE
NWR0/NWE
D3
D2
D1
VDDCORE
VDDIO
D0
NWAIT
P31/A23/CS4
P30/A22/CS5
VDDIO
NCS0
NCS1
P26/NCS2
P27/NCS3
VDDCORE
P29/A21/CS6
2
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Pin Description
Table 1. AT91R40008 Pin Description
Active
Module
Name
Function
Type
Output
I/O
Level
Comments
A0 - A23
D0 - D15
NCS0 - NCS3
CS4 - CS7
NWR0
NWR1
NRD
Address Bus
–
All valid after reset
Data Bus
–
Chip Select
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
–
Chip Select
A23 - A20 after reset
Lower Byte 0 Write Signal
Upper Byte 1 Write Signal
Read Signal
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
EBI
NWE
Write Enable
NOE
Output Enable
NUB
Upper Byte Select
Lower Byte Select
Wait Input
NLB
NWAIT
BMS
Boot Mode Select
Fast Interrupt Request
External Interrupt Request
Input
Sampled during reset
FIQ
Input
–
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
AIC
TC
IRQ0 - IRQ2
Input
–
TCLK0 - TCLK2 Timer External Clock
Input
–
TIOA0 - TIOA2
TIOB0 - TIOB2
SCK0 - SCK1
TXD0 - TXD1
RXD0 - RXD1
P0 - P31
NWDOVF
MCKI
Multipurpose Timer I/O pin A
I/O
–
Multipurpose Timer I/O pin B
External Serial Clock
Transmit Data Output
Receive Data Input
Parallel IO line
I/O
–
I/O
–
USART
Output
Input
–
–
PIO
WD
I/O
–
Watchdog Overflow
Master Clock Input
Master Clock Output
Hardware Reset Input
Tri-state Mode Select
Test Mode Select
Test Data Input
Output
Input
Low
–
Open-drain
Schmidt trigger
Clock
Reset
MCKO
Output
Input
–
NRST
Low
Low
–
Schmidt trigger
NTRI
Input
Sampled during reset
TMS
Input
Schmidt trigger, internal pull-up
Schmidt trigger, internal pull-up
TDI
Input
–
ICE
TDO
Test Data Output
Test Clock
Output
Input
–
TCK
–
Schmidt trigger, internal pull-up
3V nominal supply
VDDIO
I/O Power
Power
Power
Ground
–
Power
VDDCORE
GND
Core Power
–
1.8V nominal supply
Ground
–
3
1732DS–ATARM–03/04
Block Diagram
Figure 2. AT91R40008
TMS
TDO
TDI
Reset
NRST
Embedded
ICE
TCK
D0-D15
A1-A19
ARM7TDMI Core
A0/NLB
NRD/NOE
NWR0/NWE
NWR1/NUB
NWAIT
ASB
NCS0
NCS1
MCKI
P26/NCS2
P27/NCS3
Clock
256K Bytes RAM
P25/MCKO
P28/A20/CS7
P29/A21/CS6
P30/A22/CS5
P31/A23/CS4
ASB
Controller
AMBA Bridge
P12/FIQ
P9/IRQ0
P10/IRQ1
P11/IRQ2
EBI User
Interface
AIC: Advanced
Interrupt Controller
P0/TCLK0
P3/TCLK1
P6/TCLK2
TC: Timer
Counter
P
I
O
P
I
O
P13/SCK0
P14/TXD0
P15/RXD0
2 PDC
Channels
USART0
USART1
P1/TIOA0
P2/TIOB0
TC0
TC1
TC2
APB
P20/SCK1
P21/TXD1/NTRI
P22/RXD1
2 PDC
Channels
P4/TIOA1
P5/TIOB1
P7/TIOA2
P8/TIOB2
PS: Power Saving
P16
P17
WD: Watchdog
Timer
NWDOVF
P18
Chip ID
P19
P23
P24/BMS
PIO: Parallel I/O Controller
4
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Architectural
Overview
The AT91R40008 microcontroller integrates an ARM7TDMI with embedded ICE inter-
face, memories and peripherals. The architecture consists of two main buses: the
Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for
maximum performance and controlled by the memory controller, the ASB interfaces the
ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface
(EBI) and the AMBA™ Bridge. The AMBA Bridge drives the APB, which is designed for
accesses to on-chip peripherals and optimized for low power consumption.
The AT91R40008 microcontroller implements the ICE port of the ARM7TDMI processor
on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for tar-
get debugging.
Memories
The AT91R40008 microcontroller embeds 256K bytes of internal SRAM. The internal
memory is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91R40008 microcontroller features an External Bus Interface (EBI), which
enables connection of external memories and application-specific peripherals. The EBI
supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit
device. The EBI implements the early read protocol, enabling faster memory accesses
than standard memory interfaces.
Peripherals
The AT91R40008 microcontrollers integrate several peripherals, that are classified as
system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA
Bridge, and can be programmed with a minimum number of instructions. The peripheral
register set consists of control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs and on- and off-chip memories address space without processor intervention.
Most importantly, the PDC removes the processor interrupt handling overhead, making
it possible to transfer up to 64K contiguous bytes without reprogramming the start
address, thus increasing the performance of the microcontroller and reducing the power
consumption.
System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via
an 8- or 16-bit data bus and is programmed through the Advanced Peripheral Bus
(APB). Each chip select line has its own programming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock
stopped until the next interrupt) and enables the user to adapt the power consumption of
the microcontroller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the
internal peripherals and the four external interrupt lines (including the FIQ) to provide an
interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority
controller and, using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user
to select specific pins for on-chip peripheral input/output functions and general-purpose
input/output signal pins. The PIO controller can be programmed to detect an interrupt on
a signal change from each line.
The Watchdog (WD) can be used to prevent system lock-up if the software becomes
trapped in a deadlock.
The Special Function (SF) module integrates the Chip ID, the Reset Status and the Pro-
tect registers.
5
1732DS–ATARM–03/04
User Peripherals
Two independently configurable USARTs enable communication at a high baud rate in
synchronous or asynchronous mode. The format includes start, stop and parity bits and
up to 8 data bits. Each USART also features a Time-out and a Time-guard register,
facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels.
The 3-channel, 16-bit Timer/Counter (TC) is highly programmable and supports capture
or waveform modes. Each TC channel can be programmed to measure or generate dif-
ferent kinds of waves, and can detect and control two input/output signals. The TC also
has three external clock signals.
6
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Associated Documentation
The AT91R40008 is part of the AT91X40 series of microcontrollers, a member of the Atmel AT91 16/32-bit microcontroller
family, which is based on the ARM7TDMI processor core. The table below contains details of associated documentation for
further reference.
Table 2. Associated Documentation
Product
Information
Document Title
Internal architecture of processor
ARM/Thumb instruction sets
Embedded in-circuit-emulator
ARM7TDMI (Thumb) Datasheet
External memory interface mapping
Peripheral operations
AT91x40 Series Datasheet
Peripheral user interfaces
DC characteristics
AT91R40008
Power consumption
AT91R40008 Electrical Characteristics
Thermal and reliability considerations
AC characteristics
Product overview
Ordering information
Packaging information
Soldering profile
AT91R40008 Summary Datasheet (this document)
7
1732DS–ATARM–03/04
Product Overview
Power Supply
The AT91R40008 microcontroller has two types of power supply pins:
•
VDDCORE pins, which power the chip core (i.e., the ARM7TDMI, embedded
memory and the peripherals).
•
VDDIO pins, which power the I/O lines.
An independent I/O supply allows a flexible adaptation to external component signal
levels.
Input/Output
Considerations
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-
mum flexibility. It is recommended that in any application phase, the inputs to the
AT91R40008 microcontroller be held at valid logic levels to minimize the power
consumption.
Master Clock
The AT91R40008 microcontroller has a fully static design and works on the Master
Clock (MCK) provided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is
multiplexed through a general-purpose I/O line. While NRST is active, MCKO remains
low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The
PIO controller must be programmed to use this pin as standard I/O line.
Reset
Reset restores the default states of the user interface registers (defined in the user inter-
face of each peripheral) and forces the ARM7TDMI to perform the next instruction fetch
from address zero. Except for the program counter, the ARM7TDMI registers do not
have defined reset states.
NRST Pin
NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the MCK. The signal presented on MCKI must be active within
the specification for a minimum of 10 clock cycles up to the rising edge of NRST to
ensure correct operation.
The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
Watchdog Reset
The Watchdog can be programmed to generate an internal reset. In this case, the reset
has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not
sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted
and the Watchdog triggers the internal reset, the NRST pin has priority.
Emulation Functions
Tri-state Mode
The AT91R40008 microcontroller provides a tri-state mode, which is used for debug
purposes. This enables the connection of an emulator probe to an application board
without having to desolder the device from the target board. In tri-state mode, all the out-
put pin drivers of the AT91R40008 microcontroller are disabled.
To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles
before the rising edge of NRST. For normal operation, the NTRI pin must be held high
during reset by a resistor of up to 400 kΩ.
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
Standard RS-232 drivers generally contain internal 400 kΩ pull-up resistors. If TXD1 is
connected to a device not including this pull-up, the user must make sure that a high
level is tied on NTRI while NRST is asserted.
8
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
JTAG/ICE Debug
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-
fies the microcontroller. This is not fully IEEE1149.1 compliant.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
•
•
Internal memories in the four lowest megabytes
Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
•
Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-endian mode only.
Internal Memories
The AT91R40008 microcontroller integrates 256K bytes of internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-
bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching
Thumb or ARM instructions is supported and internal memory can store twice as many
Thumb instructions as ARM ones.
The SRAM is mapped at address 0x0 (after the Remap command), allowing
ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the
microcontroller performance and minimizes the system power consumption. The 32-bit
bus increases the effectiveness of the use of the ARM instruction set and the ability of
processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI
advanced performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an
extra dimension to the AT91R40008.
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory (see Table 3).
The BMS pin is multiplexed with the I/O line P24, which can be programmed after reset
like any standard PIO line.
Table 3. Boot Mode Select
BMS
Boot Memory
1
0
External 8-bit memory on NCS0
External 16-bit memory on NCS0
9
1732DS–ATARM–03/04
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Pre-fetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91R40008
microcontroller uses a Remap command that enables switching between the boot mem-
ory and the internal primary SRAM bank addresses. The Remap command is
accessible through the EBI User Interface by writing one in RCB of EBI_RCR (Remap
Control Register). Performing a Remap command is mandatory if access to the other
external devices (connected to chip-selects 1 to 7) is required. The Remap operation
can only be changed back by an internal reset or an NRST assertion.
Abort Control
The abort signal providing a Data Abort or a Pre-fetch Abort exception to the
ARM7TDMI is asserted when accessing an undefined address in the EBI address
space.
No abort is generated when reading the internal memory or by accessing the internal
peripherals, whether or not the address is defined.
External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and
can be configured from eight 1M byte banks up to four 16M bytes banks. It supports
byte-, half-word- and word-aligned accesses.
For each of these banks, the user can program:
•
•
Number of wait states
Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
•
Data bus width (8-bit or 16-bit)
The user can program the EBI to control one 16-bit device (Byte Select Access mode)
with a 16-bit wide data bus or two 8-bit devices in parallel that emulate a 16-bit memory
(Byte Write Access mode).
The External Bus Interface also features the Early Read Protocol, configurable for all the
devices, which significantly reduces access time requirements on an external device in
the case of single-clock cycle access.
10
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Peripherals
The AT91R40008 microcontroller peripherals are connected to the 32-bit wide
Advanced Peripheral Bus. Peripheral registers are only word accessible – byte and half-
word accesses are not supported. If a byte or a half-word access is attempted, the mem-
ory controller automatically masks the lowest address bits and generates a word
access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte
address space).
Peripheral Registers
The following registers are common to all peripherals:
•
Control Register – write-only register that triggers a command when a one is written
to the corresponding position at the appropriate address. Writing a zero has no
effect.
•
•
Mode Register – read/write register that defines the configuration of the peripheral.
Usually has a value of 0x0 after a reset.
Data Registers – read and/or write registers that enable the exchange of data
between the processor and the peripheral.
•
•
Status Register – read-only register that returns the status of the peripheral.
Enable/Disable/Status Registers are shadow command registers. Writing a one in
the Enable Register sets the corresponding bit in the Status Register. Writing a one
in the Disable Register resets the corresponding bit and the result can be read in the
Status Register. Writing a bit to zero has no effect. This register access method
maximizes the efficiency of bit manipulation and enables modification of a register
with a single non-interruptible instruction, replacing the costly read-modify-write
operation.
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for
upward compatibility. These bits read 0.
Peripheral Interrupt Control
The Interrupt Control of each peripheral is controlled from the Status Register using the
interrupt mask. The Status Register bits are ANDed to their corresponding interrupt
mask bits and the result is then ORed to generate the Interrupt Source signal to the
Advanced Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-
rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or
mask) makes it possible to enable or disable peripheral interrupt sources with a non-
interruptible single instruction. This eliminates the need for interrupt masking at the AIC
or Core level in real-time and multi-tasking systems.
Peripheral Data Controller
The AT91R40008 microcontroller has a 4-channel PDC dedicated to the two on-chip
USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of
each USART.
The user interface of a PDC channel is integrated in the memory space of each USART.
It contains a 32-bit Address Pointer Register (RPR or TPR) in addition to a 16-bit Trans-
fer Counter Register (RCR or TCR). When the programmed number of transfers are
performed, a status bit indicating the end of transfer is set in the USART Status Register
and an interrupt can be generated.
11
1732DS–ATARM–03/04
System Peripherals
PS: Power-saving
The Power-saving feature optimizes power consumption, enabling the software to stop
the ARM7TDMI clock (Idle mode), restarting it when the module receives an interrupt (or
reset). It also enables on-chip peripheral clocks to be enabled and disabled individually,
matching power consumption and application need.
AIC: Advanced Interrupt
Controller
The Advanced Interrupt Controller has an 8-level priority, individually maskable, vec-
tored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from:
•
•
•
The external fast interrupt line (FIQ)
The three external interrupt request lines (IRQ0 - IRQ2)
The interrupt signals from the on-chip peripherals
The AIC is extensively programmable offering maximum flexibility, and its vectoring fea-
tures reduce the real-time overhead in handling interrupts.
The AIC also features a spurious vector, which reduces spurious interrupt handling to a
minimum, and a protect mode that facilitates the debug capabilities.
PIO: Parallel I/O Controller
WD: Watchdog
The AT91R40008 microcontroller has 32 programmable I/O lines. Six pins are dedi-
cated as general-purpose I/O pins. Other I/O lines are multiplexed with an external
signal of a peripheral to optimize the use of available package pins. The PIO controller
enables generation of an interrupt on input change on any of the PIO pins.
The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if
the software becomes trapped in a deadlock. It can generate an internal reset or inter-
rupt, or assert an active level on the dedicated pin NWDOVF. All programming registers
are password-protected to prevent unintentional programming.
SF: Special Function
The AT91R40008 microcontroller provides registers that implement the following special
functions:
•
•
•
Chip identification
RESET status
Protect mode
12
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
User Peripherals
USART: Universal
Synchronous/
The AT91R40008 microcontroller provides two identical, full-duplex, universal synchro-
nous/asynchronous receiver/transmitters.
Asynchronous Receiver
Transmitter
Each USART has its own baud rate generator and two dedicated Peripheral Data Con-
troller channels. The data format includes a start bit, up to 8 data bits, an optional
programmable parity bit and up to 2 stop bits.
The USART also features a Receiver Time-out Register, facilitating variable length
frame support when it is working with the PDC, and a Time-guard Register, used when
interfacing with slow remote equipment.
TC: Timer/Counter
The AT91R40008 microcontroller features a Timer/Counter block that includes three
identical 16-bit Timer/Counter channels. It is possible to independently program each
channel to perform a wide range of functions, including frequency measurement, event
counting, interval measurement, pulse generation, delay timing and pulse width
modulation.
The Timer/Counter can be used in Capture or Waveform mode, and all three counter
channels can be started simultaneously and chained together.
13
1732DS–ATARM–03/04
Ordering Information
Table 4. Ordering Information
Ordering Code
Package
Operation Range
Industrial
AT91R40008-66AI
TQFP 100
(-40°C to 85°C)
14
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Packaging Information
Figure 3. 100-lead Thin Quad Flat Pack Package Outline
a a a
b b b
PIN 1
θ2
S
c c c
θ3
d d d
R2
R1
1
θ
0.25
θ
c
c 1
L1
15
1732DS–ATARM–03/04
Table 5. Common Dimensions (mm)
Symbol
c
Min
0.09
0.09
0.45
Nom
Max
0.2
c1
L
0.16
0.75
0.6
L1
R2
R1
S
1.00 REF
0.08
0.08
0.2
0°
0.2
7°
q
3.5°
θ1
θ2
θ3
A
0°
11°
11°
12°
12°
13°
13°
1.6
A1
A2
0.05
1.35
0.15
1.45
1.4
Tolerances of Form and Position
aaa
bbb
0.2
0.2
Table 6. Lead Count Dimensions (mm)
b
b1
e
Pin
Count
D/E
BSC
D1/E1
BSC
Min
Nom
Max
Min
Nom
Max
BSC
ccc
0.10
ddd
100
16.0
14.0
0.17
0.22
0.27
0.17
0.2
0.23
0.50
0.06
Table 7. Device and 100-lead TQFP Package Maximum Weight
710
mg
Table 8. 100-lead TQFP Package Characteristics
Moisture Sensitivity Level
3
16
AT91R40008 - Summary
1732DS–ATARM–03/04
AT91R40008 - Summary
Soldering Profile
Table 9 gives the recommended soldering profile from J-STD-20.
Table 9. Soldering Profile
Convection or
IR/Convection
VPR
Average Ramp-up Rate (183°C to Peak)
Preheat Temperature 125°C ±25°C
Temperature Maintained Above 183°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
3°C/sec. max.
10°C/sec.
120 sec. max
60 sec. to 150 sec.
10 sec. to 20 sec.
60 sec.
220 +5/-0°C or
235 +5/-0°C
215 to 219°C or
235 +5/-0°C
Ramp-down Rate
6°C/sec.
10°C/sec.
Time 25°C to Peak Temperature
6 min. max
Small packages may be subject to higher temperatures if they are reflowed in boards
with larger components. In this case, small packages may have to withstand tempera-
tures of up to 235°C, not 220°C (IR reflow).
Recommended package reflow conditions depend on package thickness and volume.
See Table 10.
Table 10. Recommended Package Reflow Conditions (1, 2, 3)
Parameter
Convection
VPR
Temperature
235 +5/-0°C
235 +5/-0°C
235 +5/-0°C
IR/Convection
When certain small thin packages are used on boards without larger packages, these
small packages may be classified at 220°C instead of 235°C.
Notes: 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or
VPR.
2. By default, the package level 1 is qualified at 220°C (unless 235°C is stipulated).
3. The body temperature is the most important parameter but other profile parameters
such as total exposure time to hot temperature or heating rate may also influence
component reliability.
A maximum of three reflow passes is allowed per component.
17
1732DS–ATARM–03/04
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Printed on recycled paper.
1732DS–ATARM–03/04
0M
AT91R40008-66AI 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| AT91R40008-66AU-999 | MICROCHIP | IC MCU 32BIT ROMLESS 100LQFP | 类似代替 |
|
| AT91R40008-66AU | ATMEL | AT91 ARM Thumb-based Microcontroller | 功能相似 |
|
AT91R40008-66AI 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AT91R40008-66AU | ATMEL | AT91 ARM Thumb-based Microcontroller | 获取价格 |
|
| AT91R40008-66AU | MICROCHIP | IC MCU 32BIT ROMLESS 100LQFP | 获取价格 |
|
| AT91R40008-66AU-999 | MICROCHIP | IC MCU 32BIT ROMLESS 100LQFP | 获取价格 |
|
| AT91R40008-66QI | ATMEL | RISC Microcontroller, 32-Bit, 66MHz, CMOS, PQFP100, TQFP-100 | 获取价格 |
|
| AT91R40008-70AI | ATMEL | RISC Microcontroller, 32-Bit, 70MHz, CMOS, PQFP100, TQFP-100 | 获取价格 |
|
| AT91R40008_02 | ATMEL | ARM? Thumb? Microcontrollers | 获取价格 |
|
| AT91R40008_05 | ATMEL | AT91 ARM Thumb Microcontrollers | 获取价格 |
|
| AT91R40008_06 | ATMEL | AT91 ARM Thumb-based Microcontroller | 获取价格 |
|
| AT91R40807 | ATMEL | AT91 ARM Thumb Microcontrollers | 获取价格 |
|
| AT91R40807-33AC | ATMEL | RISC Microcontroller, 32-Bit, 33MHz, CMOS, PQFP100, TQFP-100 | 获取价格 |
|
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