AT91R40008-70AI [ATMEL]
RISC Microcontroller, 32-Bit, 70MHz, CMOS, PQFP100, TQFP-100;
| 型号： | AT91R40008-70AI |
| 厂家： | 
ATMEL |
| 描述： | RISC Microcontroller, 32-Bit, 70MHz, CMOS, PQFP100, TQFP-100 微控制器 外围集成电路 |
| 文件： | 总19页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Little-endian
– Embedded ICE (In-circuit Emulation)
• 8-, 16- and 32-bit Read and Write Support
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
AT91
• Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to Eight Chip Selects
– Software Programmable 8/16-bit External Data Bus
• Eight-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 32 Programmable I/O Lines
ARM® Thumb®
Microcontrollers
• Three-channel 16-bit Timer/Counter
– Three External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
• Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
AT91R40008
Electrical
Characteristics
– CPU and Peripheral Can be Deactivated Individually
• Fully Static Operation
– 0 Hz to 70 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C
• 2.7V to 3.6V I/O Operating Range
• 1.65V to 1.95V Core Operating Range
• Available in 100-lead TQFP Package
• -40°C to +85°C Temperature Range
Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16-/32-bit microcon-
troller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set
and very low power consumption. Furthermore, it features 256K bytes of on-chip
SRAM and a large number of internally banked registers, resulting in very fast excep-
tion handling, and making the device ideal for real-time control applications.
The AT91R40008 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An 8-
level priority vectored interrupt controller, in conjunction with the Peripheral Data Con-
troller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combin-
ing the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a
wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful
microcontroller that offers a flexible and high-performance solution to many compute-
intensive embedded control applications.
Rev. 1795A–01/02
Absolute Maximum Ratings*
Operating Temperature (Industrial) ....-40°C to + 85°C
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature........................-60°C to + 150°C
Voltage on Any Input Pin with Respect to Ground
..................................................-0.3V to max of VDDIO
..........................................................+ 0.3V and 3.6V
Maximum Operating Voltage (VDDIO)....................3.6V
Maximum Operating Voltage (VDDCORE) .............1.95V
DC Output Current ...............................................TBD
The following characteristics are applicable to the Operating Temperature range: TA = -40°C to +85°C, unless otherwise
specified and are certified for a Junction Temperature up to 100°C.
Table 1. DC Characteristics
Symbol
Parameter
Conditions
Min
2.7
Typ
Max
3.6
Units
VDDIO
DC Supply I/Os
V
V
V
VDDCORE DC Supply Core
1.65
-0.3
1.95
0.8
VIL
VIH
Input Low Voltage
Input High Voltage
VDDIO
0.3
+
2.0
V
NRD, NRW0, NWR1: IOL = 16 mA(1)
Other EBI Output Pins: IOL = 8 mA(1)
Other Output Pins: IOL = 2 mA(1)
All Output Pins: IOL = 0 mA(1)
0.4
0.4
0.4
0.2
V
V
V
V
VOL
Output Low Voltage
VDDIO
0.4
-
-
-
-
NRD, NWR0, NWR1: IOH = 16 mA(1)
Other EBI Output Pins: IOH = 8 mA(1)
Other Output Pins: IOH = 2 mA(1)
All Output Pins: IOH = 0 mA(1)
V
VDDIO
0.4
VOH
Output High Voltage
VDDIO
0.4
VDDIO
0.2
ILEAK
IPULL
CIN
Input Leakage Current
Input Pull-up Current
Input Capacitance
10
µA
µA
pF
µA
µA
VDDIO = 3.6V, VIN = 0V
TQFP100 Package
280
5.3
TA = 25°C
TA = 85°C
TBD
TBD
ISC
Static Current
TBD
Note:
1. IO = Output Current.
2
AT91R40008
1795A–01/02
AT91R40008
Power Consumption The values in the following tables are measured values in the operating conditions indi-
cated (i.e., VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25°C) on the AT91EB40A Evaluation
Board.
Table 2. Power Consumption
Mode
Conditions
Consumption
Unit
Reset
TBD
Fetch in ARM mode out of internal SRAM
All peripheral clocks activated
0.32
0.23
Normal
Idle
Fetch in ARM mode out of internal SRAM
All peripheral clocks deactivated
mW/MHz
All peripheral clocks activated
All peripheral clocks deactivated
0.14
0.05
Table 3. Power Consumption per Peripheral
Peripheral
Consumption
Unit
PIO Controller
13.7
12.9
TBD
13.7
Timer/Counter Channel
Timer/Counter Block (3 Channels)
USART
µW/MHz
3
1795A–01/02
Thermal and Reliability
Considerations
Thermal Data
In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately
controlled” environmental model (this model is described as corresponding to an instal-
lation in a permanent rack with adequate cooling air), depending on the device Junction
Temperature. (For details see the section “Junction Temperature” on page 5.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL-
217 model is pessimistic with respect to observed values due to the way the data/mod-
els are obtained (test under severe conditions). The life test results that have been
measured are always better than the predicted ones.
Table 4. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C)
Estimated Lifetime (MTBF) (Year)
100
125
150
175
10
5
3
2
Table 5 summarizes the thermal resistance data related to the package of interest.
Table 5. Thermal Resistance Data
Symbol
θJA
θJC
Parameter
Condition
Package
TQFP100
TQFP100
Typ
40
Unit
=
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Still Air
°C/W
6.4
Reliability Data
The number of gates and the device die size are provided for the user to calculate reli-
ability data with another standard and/or in another environmental model.
Table 6. Reliability Data
Parameter
Data
280
Unit
K gates
K gates
mm2
Number of Logic Gates
Number of Memory Gates
Device Die Size
12,897
21.2
4
AT91R40008
1795A–01/02
AT91R40008
Junction Temperature
The average chip-junction temperature TJ in °C can be obtained from the following:
1. TJ = TA + (PD × θJA
)
2. TJ = TA + (PD × (θHEATSINK + θJC ))
Where:
•
•
•
•
•
θ
JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5
on page 4.
JC = package thermal resistance, Junction-to-case thermal resistance (°C/W),
provided in Table 5 on page 4.
HEAT SINK = cooling device thermal resistance (°C/W), provided in the device
θ
θ
datasheet.
PD = device power consumption (W) estimated from data provided in the section
“Power Consumption” on page 3.
TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and
thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted
on the chip, the second equation should be used to compute the resulting average chip-
junction temperature TJ in °C
5
1795A–01/02
Conditions
Timing Results
The delays are given as typical values in the following conditions:
•
•
•
•
•
•
VDDIO = 3.0V
VDDCORE = 1.8V
Ambient Temperature = 25°C
Load Capacitance = 0 pF
The output level change detection is 0.5 x VDDIO
The input level is 0.3 x VDDIO for a low-level detection and is 0.7 x VDDIO for a high
level detection.
The minimum and maximum values given in the AC characteristic tables of this
datasheet take into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
t = δT° × ((δVDDCORE × tDATASHEET) + (δVDDIO
Where:
×
(CSIGNAL × δCSIGNAL)))
•
•
δT is the derating factor in temperature given in Figure 1.
°
δVDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page
7.
•
tDATASHEET is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
•
•
•
δ
VDDIO is the derating factor for the I/O Power Supply given in Figure 3 on page 7.
CSIGNAL is the capacitance load on the considered output pin.(1)
CSIGNAL is the load derating factor depending on the capacitance load on the related
output pins given in Min and Max values in this datasheet.
The input delays are given as typical values.
δ
Note:
1. The user must take into account the package capacitance load contribution (CIN)
described in Table 1 on page 2.
Temperature
Figure 1. Derating Curve for Different Operating Temperatures
Derating Factor
1.2
1.1
1
Derating Factor for
Typ Case is 1
0.9
0.8
-60
-40
-20
0
20
40
60
80
100
120
140
160
Operating Temperature °C
6
AT91R40008
1795A–01/02
AT91R40008
Core Voltage
Figure 2. Core Voltage Derating Factor
Derating Factor
3
2.5
2
Derating Factor
for Typ Case is 1
1.5
1
0.5
1
1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Core Supply Voltage (V)
IO Voltage
Derating Factor
Figure 3. Derating Factor for Different VDDIO Power Supply Levels
1.6
Derating Factor for
Typ Case is 1
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
DDIO Voltage Level
7
1795A–01/02
Clock Waveforms
Table 7. Master Clock Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
MHz
ns
1/(tCP
tCP
tCH
tCL
tr
)
Oscillator Frequency
Oscillator Period
High Half-period
Low Half-period
MCKI Rising Edge
MCKI Falling Edge
82.1
12.2
0.45 x tCP
0.45 x tCP
0.55 x tCP
0.55 x tCP
TBD
ns
ns
ns
tf
TBD
ns
Note:
1. Applicable only for Chip Select programmed with zero wait states.
Table 8. Clock Propagation Times
Symbol
Parameter
Conditions
MCKO = 0 pF
CMCKO derating
Min
Max
6.6
Units
ns
C
4.4
0.199
4.5
tCDLH
Rising Edge Propagation Time
0.295
6.7
ns/pF
ns
CMCKO = 0 pF
tCDHL
Falling Edge Propagation Time
CMCKO derating
0.153
0.228
ns/pF
Figure 4. Clock Waveform
tCH
tr
tf
0.7 VDDIO
MCKI
0.3 VDDIO
tCL
tCP
0.5 VDDIO
0.5 VDDIO
MCKO
tCDLH
tCDHL
8
AT91R40008
1795A–01/02
AT91R40008
Table 9. NRST to MCKO
Symbol
Parameter
Min
Max
Units
tD
NRST Rising Edge to MCKO Valid Time
3(tCP/2)
7(tCP/2)
ns
Figure 5. MCKO Relative to NRST
NRST
tD
MCKO
9
1795A–01/02
AC Characteristics
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 6.
See Figure 6 on page 14.
Table 10. General-purpose EBI Signals
Symbol
Parameter
Conditions
Min
4.4
Max
8.9
Units
ns
C
C
C
C
NUB = 0 pF
NUB derating
NLB = 0 pF
EBI1
MCKI Falling to NUB Valid
0.030
3.7
0.043
6.7
ns/pF
ns
EBI2
EBI3
EBI4
MCKI Falling to NLB/A0 Valid
MCKI Falling to A1 - A23 Valid
NLB derating
0.045
3.4
0.069
7.8
ns/pF
ns
CADD = 0 pF
CADD derating
CNCS = 0 pF
0.045
3.7
0.076
8.6
ns/pF
ns
MCKI Falling to Chip Select
Change
CNCS derating
0.045
1.7
0.078
ns/pF
ns
EBI5
EBI6
NWAIT Setup before MCKI Rising
NWAIT Hold after MCKI Rising
1.7
ns
10
AT91R40008
1795A–01/02
AT91R40008
Table 11. EBI Write Signals
Symbol
Parameter
Conditions
Min
3.9
Max
6.3
Units
ns
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
EBI7
MCKI Rising to NWR Active (No Wait States)
0.029
4.4
0.043
7.0
ns/pF
ns
EBI8
MCKI Rising to NWR Active (Wait States)
MCKI Falling to NWR Inactive (No Wait States)
MCKI Rising to NWR Inactive (Wait States)
MCKI Rising to D0 - D15 Out Valid
NWR High to NUB Change
0.029
3.8
0.043
6.3
ns/pF
ns
CNWR = 0 pF
EBI9
CNWR derating
CNWR = 0 pF
CNWR derating
CDATA = 0 pF
CDATA derating
0.029
4.2
0.044
6.7
ns/pF
ns
EBI10
EBI11
EBI12
EBI13
EBI14
EBI15
0.029
4.2
0.044
7.5
ns/pF
ns
0.045
3.1
0.080
7.0
ns/pF
ns
CNUB = 0 pF
CNUB derating
0.030
3.1
0.043
5.4
ns/pF
ns
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
CNCS = 0 pF
NWR High to NLB/A0 Change
0.043
2.9
0.073
7.0
ns/pF
ns
NWR High to A1 - A23 Change
0.043
2.9
0.076
6.8
ns/pF
ns
NWR High to Chip Select Inactive
CNCS derating
C = 0 pF
0.052
tCH - 1.8
-0.080
0.044
n x tCP - 1.3(2)
-0.080
0.044
2.2
0.067
ns/pF
ns
EBI16
EBI17
Data Out Valid before NWR High (No Wait States)(1)
Data Out Valid before NWR High (Wait States)(1)
CDATA derating
ns/pF
ns/pF
ns
CNWR derating
C = 0 pF
C
DATA derating
NWR derating
ns/pF
ns/pF
ns
C
EBI18
EBI19
Data Out Valid after NWR High
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
tCH - 0.6
0
ns
NWR Minimum Pulse Width (No Wait States)(1)
ns/pF
ns
n x tCP - 0.9(2)
EBI20
NWR Minimum Pulse Width (Wait States)(1)
CNWR derating
0
ns/pF
Notes: 1. The derating factor should not be applied to tCH or tCP.
2. n = number of standard wait states inserted.
11
1795A–01/02
Table 12. EBI Read Signals
Symbol
Parameter
Conditions
Min
Max
7.9
Units
ns
CNRD = 0 pF
4.5
EBI21
MCKI Falling to NRD Active(1)
C
NRD derating
CNRD = 0 pF
NRD derating
CNRD = 0 pF
NRD derating
CNRD = 0 pF
NRD derating
0.029
0.043
7.3
ns/pF
ns
3.8
EBI22
EBI23
EBI24
MCKI Rising to NRD Active(2)
MCKI Falling to NRD Inactive(1)
MCKI Falling to NRD Inactive(2)
C
0.029
0.043
6.5
ns/pF
ns
4.1
C
0.030
0.044
5.8
ns/pF
ns
3.9
C
0.030
0.044
ns/pF
ns
EBI25
EBI26
D0 - D15 In Setup before MCKI Falling Edge(5)
D0 - D15 In Hold after MCKI Falling Edge(5)
1.5
1.2
ns
CNUB = 0 pF
3.2
7.1
0.043
4.6
ns
EBI27
EBI28
EBI29
EBI30
EBI31
EBI32
EBI33
EBI34
NRD High to NUB Change
CNUB derating
0.030
ns/pF
ns
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
CNCS = 0 pF
3.2
NRD High to NLB/A0 Change
NRD High to A1 - A23 Change
NRD High to Chip Select Inactive
Data Setup before NRD High(5)
Data Hold after NRD High(5)
NRD Minimum Pulse Width(1)(3)
NRD Minimum Pulse Width(2)(3)
0.043
0.073
6.1
ns/pF
ns
2.8
0.043
0.076
6.2
ns/pF
ns
2.9
CNCS derating
CNRD = 0 pF
0.052
0.067
ns/pF
ns
8.0
0.044
C
NRD derating
CNRD = 0 pF
NRD derating
CNRD = 0 pF
NRD derating
CNRD = 0 pF
NRD derating
ns/pF
ns
-3.1
C
-0.030
ns/pF
ns
(n +1) tCP - 1.9(4)
C
0.001
ns/pF
ns
n x tCP + (tCH - 1.5)(4)
0.001
C
ns/pF
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. The derating factor should not be applied to tCH or tCP.
4. n = number of standard wait states inserted.
5. Only one of these two timings needs to be met.
12
AT91R40008
1795A–01/02
AT91R40008
Table 13. EBI Read and Write Control Signals. Capacitance Limitation
Symbol
Parameter
Conditions
Min
7.3
Max
Units
ns
CNRD = 0 pF
(1)
TCPLNRD
Master Clock Low Due to NRD Capacitance
CNRD derating
CNWR = 0 pF
CNWR derating
0.044
7.6
ns/pF
ns
(2)
TCPLNWR
Master CLock Low Due to NWR Capacitance
0.044
ns/pF
Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
13
1795A–01/02
Figure 6. EBI Signals Relative to MCKI
MCKI
EBI4
EBI4
NCS
CS
EBI3
A1 - A23
NWAIT
EBI5
EBI6
EBI1/EBI2
NUB/NLB/A0
EBI21
EBI27-30
EBI23
EBI33
NRD(1)
NRD(2)
EBI22 EBI24
EBI34
EBI31
EBI32
EBI25
EBI26
D0 - D15 Read
EBI9
EBI19
EBI12-15
EBI7
NWR (No Wait States)
NWR (Wait States)
D0 - D15 to Write
EBI8
EBI10
EBI20
EBI11
EBI17
EBI18
EBI16
EBI18
No Wait
Wait
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
14
AT91R40008
1795A–01/02
AT91R40008
Peripheral Signals
USART Signals
The inputs have to meet the minimum pulse width and period constraints shown in
Table 14 and Table 15, and represented in Figure 7.
Table 14. USART Input Minimum Pulse Width
Symbol
Parameter
Min Pulse Width
Units
US1
SCK/RXD Minimum Pulse Width
5(tCP/2)
ns
Table 15. USART Minimum Input Period
Symbol
Parameter
Min Input Period
Units
US2
SCK Minimum Input Period
9(tCP/2)
ns
Figure 7. USART Signals
US1
RXD
SCK
US2
US1
15
1795A–01/02
Timer/Counter Signals
Due to internal synchronization of input signals, there is a delay between an input event
and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection
mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the
minimum pulse width and minimum input period shown in Table 16 and Table 17, and
as represented in Figure 8.
Table 16. Timer Input Minimum Pulse Width
Symbol
Parameter
Min Pulse Width
Units
TC1
TCLK/TIOA/TIOB Minimum Pulse Width
3(tCP/2)
ns
Table 17. Timer Input Minimum Period
Symbol
Parameter
Min Input Period
Units
TC2
TCLK/TIOA/TIOB Minimum Input Period
5(tCP/2)
ns
Figure 8. Timer Input
TC2
3(tCP/2)
3(tCP/2)
MCKI
TC1
TIOA/
TIOB/
TCLK
Reset Signals
A minimum pulse width is necessary, as shown in Table 18 and as represented in Figure 9.
Table 18. Reset Minimum Pulse Width
Symbol
Parameter
Min Pulse-width
10(tCP
Units
RST1
NRST Minimum Pulse Width
)
ns
Figure 9. Reset Signal
RST1
NRST
Only the NRST rising edge is synchronized with MCKI. The falling edge is
asynchronous.
16
AT91R40008
1795A–01/02
AT91R40008
Advanced Interrupt Controller Inputs have to meet the minimum pulse width and minimum input period shown in Table
Signals
19 and Table 20 and represented in Figure 10.
Table 19. AIC Input Minimum Pulse Width
Symbol
Parameter
Min Pulse Width
Units
AIC1
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum
Pulse Width
3(tCP/2)
ns
Table 20. AIC Input Minimum Period
Symbol
Parameter
Min Input Period
Units
AIC2
AIC Minimum Input Period
5(tCP/2)
ns
Figure 10. AIC Signals
AIC2
MCKI
AIC1
FIQ/IRQ0/
IRQ1/IRQ2/
IRQ3 Input
Parallel I/O Signals
The inputs have to meet the minimum pulse width shown in Table 21 and represented in
Figure 11.
Table 21. PIO Input Minimum Pulse Width
Symbol
Parameter
Min Pulse Width
Units
PIO1
PIO Input Minimum Pulse Width
3(tCP/2)
ns
Figure 11. PIO Signal
PIO1
PIO
Inputs
17
1795A–01/02
ICE Interface Signals
Table 22. ICE Interface Timing Specifications
Symbol
Parameter
Conditions
Min
10.9
0.9
Max
Units
ns
NTRST Minimum Pulse
Width
ICE0
NTRST High Recovery
to TCK High
ICE1
ICE2
ns
NTRST High Removal
from TCK High
-0.3
23.5
22.7
46.1
ns
ns
ns
ns
ICE3
ICE4
ICE5
TCK Low Half-period
TCK High Half-period
TCK Period
TDI, TMS Setup before
TCK High
ICE6
ICE7
0.4
ns
TDI, TMS Hold after
TCK High
0.4
3.3
ns
ns
CTDO = 0 pF
ICE8
ICE9
TDO Hold Time
CTDO derating
0.001
ns/pF
ns
C
C
TDO = 0 pF
7.4
TCK Low to TDO Valid
TDO derating
0.28
ns/pF
Figure 12. ICE Interface Signal
ICE0
NTRST
ICE2
ICE1
ICE5
TCK
ICE3
ICE4
TMS/TDI
ICE6
ICE7
TDO
ICE8
ICE9
18
AT91R40008
1795A–01/02
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