AT91M63200-12AJ-1.8 [ATMEL]
RISC Microcontroller, 32-Bit, 12MHz, CMOS, PQFP176, TQFP-176;
| 型号： | AT91M63200-12AJ-1.8 |
| 厂家： | 
ATMEL |
| 描述： | RISC Microcontroller, 32-Bit, 12MHz, CMOS, PQFP176, TQFP-176 时钟 微控制器 外围集成电路 |
| 文件： | 总21页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Utilizes the ARM7TDMI™ ARM Thumb Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 2K Bytes (M63200) or 3K Bytes (M43300) Internal RAM
• Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
• Multi-processor Interface (M63200 Only)
– High-performance External Processor Interface
– 512 x 16-bit Dual-port RAM
AT91
ARM® Thumb®
Microcontrollers
• 8-channel Peripheral Data Controller
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 58 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
AT91M63200
AT91M43300
– 6 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 3 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for up to 9-bit Data Transfers
• Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Electrical
Characteristics
• Programmable Watchdog Timer
• Power Management Controller (PMC)
– CPU and Peripherals Can be Deactivated Individually
• IEEE 1149.1 JTAG Boundary-scan on All Active Pins
• Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V Core, 25 MHz at 2.7V Core)
• 1.8V to 3.6V Core Operating Voltage Range
• 2.7V to 5.5V I/O Operating Voltage Range
• -40°C to +85°C Operating Temperature Range
• AT91M63200 in a 176-lead TQFP Package; AT91M43300 in a 144-ball BGA Package
Description
The AT91M63200 and AT91M43300 are members of the Atmel AT91 16/32-bit micro-
controller family which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and very low power consumption. In addition, a large number of
internally banked registers result in very fast exception handling, making the device
ideal for real-time control applications. The AT91 ARM-based MCU family also fea-
tures Atmel’s high-density, in-system programmable, nonvolatile memory technology.
Both products have a direct connection to off-chip memory, including Flash, through
the External Bus Interface.
For the AT91M63200, the Multi-processor Interface (MPI) provides a high-perfor-
mance interface with an external coprocessor or a high bandwidth peripheral.
Both products are manufactured using Atmel’s high-density CMOS technology. By
combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-processor
interface and a wide range of peripheral functions on a monolithic chip, the
AT91M63200 and AT91M43300 provide a highly-flexible and cost-effective solution to
many compute-intensive real-time applications.
Rev. 1090B–06/00
Absolute Maximum Ratings*
Operating Temperature (Industrial) .....-40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these or other con-
ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect device reliability.
Voltage on Any Input Pin
with Respect to Ground.......................-0.5V to +5.5V
Maximum Operating Voltage (Core).....................3.6V
Maximum Operating Voltage (I/Os) ......................5.5V
DC Output Current ..............................................4 mA
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
3.6
Units
(1)
VDDCORE
DC Supply Voltage Core
1.8
V
VDDCORE
2.0 or 5.5
+
2.7V ≤ VDDCORE ≤ 3.6V
1.8V ≤ VDDCORE ≤ 2.7V
VDDCORE
VDDIO
DC Supply I/Os
V
2.7
-40
-0.3
3.3
TA
Ambient Temperature
Low-level Input Voltage
85
°C
VIL
0.8
V
VDDIO
0.3
+
VIH
High-level Input Voltage
2
V
V
V
V
V
2.7 ≤ V
≤ 3.6; IO(2) = 2 mA
0.4
0.4
DDIO
VOL
Low-level Output Voltage
VDDCORE ≤ V
IO(2) = 4 mA
≤ 5.5V;
DDIO
2.7 ≤ V
≤ 3.6; IO(2) = 2 mA
VDDIO - 0.4
VDDIO - 0.4
DDIO
VOH
High-level Output Voltage
VDDCORE ≤ V
IO(2) = 4 mA
≤ 5.5V;
DDIO
ILEAK
IPULL
ICAP
Input-leakage Current
Input Pull-up Current
Input Capacitance
100
100
12
nA
µA
pF
V
= VDDCORE = 3.6V
DDIO
MCKI = 0 Hz, NRST = 1
ISC
Static Current
60
µA
Notes: 1. See Table 4.
2. IO = Output current.
AT91M63200/M43300
2
AT91M63200/M43300
Power Consumption
The values in the following tables are measured values in the operating conditions indicated (i.e. VDDIO = 3.3V, VDDCORE
=
3.3V or 1.8V; T = 25°). They represent the power consumption on the VDDCORE power supply.
Table 1. Core Power Consumption
VDDCORE
Mode
Conditions
1.8V
3.3V
Unit
Reset
0.05
0.41
Fetch in ARM mode out of Internal SRAM
All peripheral clocks activated
3.1
1.8
13.3
7.4
Normal
Idle
Fetch in ARM mode out of Internal SRAM
All peripheral clocks deactivated
mW/MHz
All peripheral clocks activated
All peripheral clocks deactivated
2.0
8.7
2.4
0.54
Table 2. Core Power Consumption per Peripheral
VDDCORE
Peripheral
1.8V
0.07
0.07
0.18
0.22
0.22
3.3V
0.32
0.28
0.75
0.99
1.02
Unit
PIO Controller
Timer Counter channel
Timer Counter Block (3 channels)
USART
mW/MHz
SPI
3
Conditions
Environment Constraints
The output delays are valid for a capacitive load of 50 pF as shown in Figure 1.
Figure 1. Output/Bidir Pad Capacitive Load
C
= 50 pF
L
PAD
Timing Results
The output delays are for a capacitive load of 50 pF as shown in Figure 1.
In order to obtain the timing for other capacitance values, the following equation should be used.
t = tdatasheet + factor × (Cload – 50pF)
Table 3. Derating Factor Due to Capacitive Load Variation
Parameter
Industrial
Units
Factor
0.058
ns/pF
In the tables that follow, the output delays are for industrial conditions only.
Voltage Ranges
Although the core may be supplied between 1.8V and 3.6V, there are two voltage ranges that have been characterized for
timing purposes.
These are from 1.8V to 2.2V (core at 2V), and 2.7V to 3.6V (core at 3.3V). Timing values are given for both sets of condi-
tions, as in Table 4.
Table 4. Voltage Ranges for Timing Characterization
VDDCORE
VDDIO
Condition
Core at 2V
Core at 3.3V
Minimum
1.8
Maximum
2.2
Minimum
2.7
Maximum
3.3
Unit
V
2.7
3.6
2.7
5.5
AT91M63200/M43300
4
AT91M63200/M43300
Clock Waveforms
Table 5. Clock Waveform Parameters
Minimum
Maximum
Core at
2V
Core at
3.3V
Core at
2V
Core at
3.3V
Symbol
Parameter
Units
1/(tCP
tCP
tCH
tCL
tr
)
Oscillator Frequency
Main Clock Period
High Time
12
25
MHz
83
40
18
18
TBD
TBD
Low Time
ns
Rising Edge
TBD
TBD
7
7
tf
Falling Edge
Table 6. Clock Propagation Times
Minimum
Maximum
Core at
2V
Core at
3.3V
Core at
2V
Core at
3.3V
Symbol
tCDLH
Parameter
Units
Rising Edge Propagation Time
Falling Edge Propagation Time
TBD
TBD
20
18
TBD
TBD
TBD
TBD
ns
tCDHL
Figure 2. Clock Waveform
tCH
tr
tf
MCKI
0.7 VDDIO
0.3 VDDIO
tCL
tCP
MCKO
tCDLH
tCDHL
5
AC Characteristics
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in Table 4. See Figure 3.
Table 7. General Purpose EBI Signals
Minimum
Maximum
Symbol
EBI1
Parameter
Core at 2V
Core at 3.3V
Core at 2V
Core at 3.3V
Units
ns
MCKI Falling to NUB Valid
MCKI Falling to NLB/A0 Valid
MCKI Falling to A7 - A1 Valid
MCKI Falling to A23 - A8 Valid
MCKI Falling to Chip Select
NWAIT Setup before MCKI Rising
NWAIT Hold after MCKI Rising
TBD
TBD
TBD
TBD
TBD
20
20
20
20
20
EBI2
ns
EBI3
ns
EBI4
ns
EBI5
TBD
TBD
TBD
5
5
4
ns
EBI6
ns
EBI7
ns
Table 8. EBI Write Signals
Minimum
Maximum
Symbol
Parameter
Core at 2V
Core at 3.3V
Core at 2V
Core at 3.3V
Units
EBI8
MCKI Rising to NWR Active (No Wait
States)
TBD
20
ns
EBI9
MCKI Rising to NWR Active (Wait
States)
TBD
TBD
TBD
TBD
20
20
20
20
ns
ns
ns
EBI10
EBI11
MCKI Falling to NWR Inactive (No
Wait States)
MCKI Rising to NWR Inactive (Wait
States)
EBI12
EBI19
MCKI Rising to D0 - D15 Out Valid
ns
ns
NWR High to A23 - A1, NUB/NLB/A0,
NCS, CS Changes (No Wait States)
TBD
2
EBI20
NWR High to A23 - A1, NCS, CS
Changes (Wait States)
tCP/2
ns
EBI21
EBI22
Data Out Valid before NWR High
Data Out Valid after NWR High
tCH - 5
tCP/2
ns
ns
AT91M63200/M43300
6
AT91M63200/M43300
Table 9. EBI Read Signals
Minimum
Maximum
Symbol
EBI13
EBI14
EBI15
EBI16
EBI17
Parameter
Core at 2V
Core at 3.3V
Core at 2V
TBD
Core at 3.3V
Units
MCKI Falling to NRD Valid(1)
MCKI Rising to NRD Valid(2)
D0 - D15 in Setup before MCKI Falling
D0 - D15 in Hold after MCKI Falling
TBD
5
18
20
TBD
TBD
TBD
TBD
0
3
0
ns
NRD High to A23 - A1, NCS, CS
Changes
EBI18
Data Hold after NRD High
TBD
0
Notes: 1. Early Read Protocol
2. Standard Read Protocol
7
Figure 3. EBI Signals Relative to MCKI
MCKI
EBI5
EBI5
NCS
CS
A1 - A23
NWAIT
EBI3/EBI4
No Wait
EBI7
Wait
EBI6
EBI1/EBI2
NUB/NLB/A0
EBI13
EBI13
EBI17
NRD(1)
NRD(2)
EBI14
EBI18
EBI15
EBI16
D0 - D15 read
EBI10
EBI8
EBI19
NWR (No Wait States)
NWR (Wait States)
D0 - D15 to Write
EBI20
EBI9
EBI11
EBI12
EBI21
EBI22
EBI22
No Wait
Wait
Notes: 1. Early Read Protocol
2. Standard Read Protocol
AT91M63200/M43300
8
AT91M63200/M43300
Peripheral Signals Relative to MCKI
USART Signals
Table 10. USART Outputs
Minimum
Maximum
Symbol
Parameter
Core at 2V
Core at 3.3V
Core at 2V
Core at 3.3V
Units
US1
MCKI Rising to SCK Output
Rising/Falling
TBD
TBD
TBD
25
ns
US2
US3
US4
MCKI Rising to TXD Toggling
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
35
10
ns
ns
ns
SCK Output Falling to TXD Toggling
SCK Input Falling to TXD Toggling
2(tCP) + 35
The inputs can be used synchronously or asynchronously (in relation to MCKI).
For synchronous and asynchronous USART inputs, certain setup/hold constraints must be met. These constraints are
shown in Tables 11 and 12 and are represented in Figure 4.
For asynchronous inputs, a minimum pulse-width is necessary as shown in Table 13 and as represented in Figure 4.
Table 11. USART Synchronous Input Setup/Hold Constraints
Symbol
US5
Type of Input
Synchronous
Synchronous
Synchronous
Parameter
Setup
Hold
Units
ns
RXD Toggling Relative to MCKI Falling
SCK Input Rising Relative to MCKI Rising
SCK Input Falling Relative to MCKI Rising
0
0
0
5
5
5
US6
ns
US7
ns
Table 12. USART Asynchronous Input Setup/Hold Constraints
Symbol
Type of Input
Parameter
Setup
Hold
Units
US8
Asynchronous RXD Toggling Relative to SCK Input Rising
tCP/2 - 2
tCP/2 + 2
ns
Table 13. USART Asynchronous Input Minimum Pulse-width
Symbol
Type of Input
Parameter
Pulse-width
3(tCP/2)
Units
US9
Asynchronous RXD/SCK Minimum Pulse-width
ns
9
Figure 4. USART Signals Relative to MCKI
MCKI
US1
US1
SCK Output
US3
US7H
US7S
US6H
US6S
SCK Input
US2
US4
US8S
US8H
TXD
RXD
US5S
US5H
US9
RXD/SCK
(Asynchronous)
AT91M63200/M43300
10
AT91M63200/M43300
SPI Signals
Table 14. SPI Signals in Master Mode
Minimum
Core at 2V Core at 3.3V
Maximum
Symbol
tSPCK
fSPCK
SP1
Parameter
Core at 2V
16320(tCP
1/4(tCP
261120(tCP)
Core at 3.3V
Units
ns
SPI Operating Period
SPI Operating Frequency
Delay before NPCS[3:0]
Delay between Chip Selects
Delay before SPCK
4(tCP
)
)
1/16320(tCP
)
)
GHz
ns
4(tCP
6(tCP
2(tCP
)
)
)
SP2
8160(tCP
)
)
ns
SP3
8160(tCP
ns
SP4
MISO/SPCK Setup Time
MISO/SPCK Hold Time
MOSI Valid after SPCK Edge
TBD
TBD
18
7
ns
SP5
TBD
0
ns
SP6
ns
Figure 5. SPI Signals
SP1
SP3
NPCS[3:0]
output
SP2
tSPCK
SPCK
Output
CPOL = 0
SPCK
Output
CPOL = 1
SP4
SP5
MISO
Input
MSB In
LSB In
Data
SP6
MSB Out
MOSI
Output
LSB Out
Data
11
Timer Counter Signals
Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event.
This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. In addition
there are the following delays relative to MCKI waveforms.
Table 15. Timer Outputs
Maximum
Symbol
TC1
Parameter
Core at 2V
TBD
Core at 3.3V
Units
MCKI Rising to TIOA Rising
MCKI Rising to TIOA Falling
MCKI Rising to TIOB Rising
MCKI Rising to TIOB Falling
22
22
22
22
TC2
TBD
ns
TC3
TBD
TC4
TBD
The inputs can be used synchronously or asynchronously (in relation to MCKI).
For synchronous Timer inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 16
and are represented in Figure 6.
For asynchronous inputs, a minimum pulse-width and a minimum input period are necessary as shown in Tables 17 and 18
and as represented in Figure 6.
Table 16. Synchronous Timer Inputs
Setup
Hold
Core at
2V
Core at
3.3V
Core at
2V
Core at
3.3V
Symbol
TC5
Type of Input
Synchronous
Synchronous
Parameter
Units
TIOA/TIOB Rising Relative to MCKI Rising
TBD
TBD
2
2
TBD
TBD
5
5
TC6
TIOA/TIOB Falling Relative to MCKI
Rising
ns
TC7
TC8
Synchronous
Synchronous
TCLK Rising Relative to MCKI Rising
TCLK Falling Relative to MCKI Rising
TBD
TBD
2
2
TBD
TBD
5
5
Table 17. Asynchronous Timer Input Minimum Pulse-width
Symbol
Type of Inputs
Parameter
TCLK/TIOA/TIOB Minimum Pulse-width
Pulse-width
Units
TC9
Asynchronous
3(tCP/2)
ns
Table 18. Asynchronous Timer Input Minimum Input Period
Symbol
Type of Inputs
Parameter
Input Period
Units
TC10
Asynchronous
TCLK/TIOA/TIOB Minimum Input Period
5(tCP/2)
ns
AT91M63200/M43300
12
AT91M63200/M43300
Figure 6. Timer Relative to MCKI
TC10
3(tCP/2)
1(tCP)
MCKI
Detect
TC9
Detect
TIOA/TIOB/TCLK
Asynchronous In
TC7H
TC7S
TC8H
TC8S
TCLK
Synchronous Input
TC5H
TC5S
TC6H
TC6S
TIOA/TIOB
Synchronous Inputs
TC1
TC2
TIOA
Output
TC3
TC4
TIOB
Output
13
Watchdog Timer Signals
Table 19. Watchdog Timer Outputs
Maximum
Symbol
WD1
Parameter
Core at 2V
TBD
Core at 3.3V
Units
MCKI Rising to NWDOVF Rising
MCKI Rising to NWDOVF Falling
20
20
ns
WD2
TBD
Figure 7. Watchdog Signals Relative to MCKI
MCKI
WD1
WD2
Z
Z
NWDOVF Output
Reset Signals
Certain setup constraints must be met. These constraints are shown in Table 20 and are represented in Figure 8.
Table 20. Reset Setup Constraints
Setup
Symbol
Parameter
Core at 2V
Core at 3.3V
Units
RST1
NRST Rising Related to MCKI Rising
TBD
5
ns
A minimum pulse width is necessary as shown in Table 21 and as represented in Figure 8.
Table 21. Reset Minimum Pulse-width
Symbol
Parameter
Pulse-width
10(tCP
Units
RST3
NRST Minimum Pulse-width
)
ns
Figure 8. Reset Signals Relative to MCKI
MCKI
RST1H
RST1S
RST3
NRST
Only the NRST rising edge is synchronized. The falling edge is asynchronous.
AT91M63200/M43300
14
AT91M63200/M43300
Advanced Interrupt Controller Signals
The inputs can be used synchronously or asynchronously (in relation to MCKI).
For synchronous AIC inputs, certain setup/hold constraints must be met. These constraints are shown in Table 22 and are
represented in Figure 9.
For asynchronous inputs, a minimum pulse width is necessary as shown in Table 23 and as represented in Figure 9.
Table 22. AIC Synchronous Input Setup/Hold Constraints
Setup
Hold
Core
Core
Core
Core
Symbol
Type
Parameter
at 2V
at 3.3V
at 2V
at 3.3V
Units
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Rising.
Relative to MCKI Rising
AIC1
Synchronous
TBD
0
0
TBD
4
4
ns
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Falling.
Related to MCKI Rising
AIC2
Synchronous
TBD
TBD
ns
Table 23. AIC Asynchronous Input Minimum Pulse-width
Symbol
Type
Parameter
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse-width
Pulse-width
Units
AIC5
Asynchronous
3(tCP/2)
ns
Table 24. AIC Asynchronous Input Minimum Input Period
Symbol
Type
Parameter
Input Period
Units
AIC6
Asynchronous
AIC Minimum Input Period
5(tCP/2)
ns
Figure 9. AIC Signals Relative to MCKI
AIC6
MCKI
AIC5
FIQ/IRQ0/IRQ1/IRQ2/IRQ3
Asynchronous Input
AIC1H
AIC1S
AIC2H
AIC1S
FIQ/IRQ0/IRQ1/IRQ2/IRQ3
Synchronous Input
15
Parallel I/O Signals
Table 25. PIO Outputs
Maximum
Symbol
PIO1
Parameter
Core at 2V
Core at 3.3V
Units
ns
MCKI Falling to PIO Output Rising
MCKI Falling to PIO Output Falling
TBD
TBD
22
22
PIO2
ns
The inputs can be used synchronously or asynchronously (in relation to MCKI).
For synchronous PIO inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 26 and
are represented in Figure 10.
For asynchronous inputs, a minimum pulse width is necessary as shown in Table 27 and as represented in Figure 10.
Table 26. PIO Synchronous Input Setup/Hold Constraints
Setup
Hold
Core
Core
Core
Core
Symbol
PIO3
Type
Parameter
at 2V
at 3.3V
at 2V
at 3.3V
Units
ns
Synchronous
Synchronous
PIO Input Rising Related to MCKI Rising
PIO Input Falling Related to MCKI Rising
TBD
2
2
TBD
5
5
PIO4
TBD
TBD
ns
Table 27. PIO Asynchronous Input Minimum Pulse-width
Symbol
Type
Parameter
Pulse-width
Units
PIO5
Asynchronous
PIO Input Minimum Pulse-width
3(tCP/2)
ns
Figure 10. PIO Signals Relative to MCKI
MCKI
PIO3H
PIO3S
PIO4H
PIO4S
PIO
Synchronous Inputs
PIO5
PIO
Asynchronous Inputs
PIO1
PIO2
PIO
Outputs
AT91M63200/M43300
16
AT91M63200/M43300
Multi-processor Interface Signals (AT91M63200 Only)
Figure 11. External Arbitration
MPI_BR
t1
t2
MPI_BG
MPI_D[15:0]
Data Transfer
Table 28. External Arbitration
Minimum
Core at 2V Core at 3.3V
Maximum
Symbol
Parameter
Core at 2V
Core at 3.3V
Units
MPI_BR High to MPI_BG High Delay
(30 pf)
t1
t2
tCP
2 x tCP + 12
ns
MPI_BR Low to MPI_BG Low
TBD
12
17
Table 29. MPI Read Access
Minimum
Maximum
Symbol
tRC
Parameter
Core at 2V
Core at 3.3V
Core at 2V
Core at 3.3V
Units
ns
Read Cycle Time
TBD
22
tAA
Address Access Time
TBD
TBD
TBD
TBD
22
22
10
10
ns
tACS
tOE
LB, tUB
Chip Select Access Time
Output Enable to Output Valid
Byte Select to Output Valid
Output Hold from Address Change
Chip Select to Output in Low-Z
Output Enable to Output in Low-Z
ns
ns
t
ns
tOH
TBD
TBD
TBD
0
0
0
ns
tCLZ
tOLZ
tLBLZ,
ns
ns
Byte Select to Output in Low-Z
TBD
0
ns
tUBLZ
tCHZ
tOHZ
tLBHZ,
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
TBD
TBD
7
7
ns
ns
Byte Deselect to Output in High-Z
TBD
7
ns
tUBHZ
Figure 12. MPI Read Access
tRC
MPI_A[9:1]
Valid Address
tAA
tOH
tCHZ
tACS
MPI_NCS
MPI_NOE
tOE
tOHZ
tLB
tUB
tLBHZ tUBHZ
MPI_NLB, MPI_NUB
tOLZ tLBLZ tUBLZ
tCLZ
High Impedance
MPI_D[15:0]
Valid Data
AT91M63200/M43300
18
AT91M63200/M43300
Table 30. MPI Write Access
Minimum
Maximum
Symbol
tWC
Parameter
Core at 2V
Core at 3.3V
Core at 2V
Core at 3.3V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
10
10
10
10
10
0
tAW
Address Valid to End of Write
Chip Select to End of Write
Write pulse-width
tCW
tWP
t
LBW, tUBW
Byte Select to End of Write
Address Setup Time
tAS
tWR
tDW
tDH
Write Recovery Time
0
Data Valid to End of Write
Data Hold Time from End of Write
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
10
0
tOW
tWHZ
10
TBD
7
Figure 13. MPI Write Access (MPI_RNW Controlled)
tWC
MPI_A[9:1]
Valid Address
tAW
tWR
tAS
tWP
MPI_RNW
tCW
MPI_NCS
tLBW tUBW
MPI_NLB, MPI_NUB
MPI_Dout[15:0]
tWHZ
tOW
high-Z
tDW
tDH
High-Z
High-Z
MPI_Din[15:0]
Valid Data
19
Figure 14. MPI Write Access (MPI_NCS Controlled)
tWC
MPI_A[9:1]
Valid Address
tAW
tWR
tAS
tWP
MPI_RNW
tCW
MPI_NCS
tLBW tUBW
MPI_NLB, MPI_NUB
tDW
tDH
High-Z
High-Z
MPI_Din[15:0]
Valid Data
Figure 15. MPI Write Access (MPI_NLB, MPI_NUB Controlled)
tWC
MPI_A[9:1]
MPI_RNW
Valid Address
tWP
tAW
tWR
tAS
tCW
MPI_NCS
tLBW tUBW
MPI_NLB, MPI_NUB
MPI_Din[15:0]
tDW
tDH
High-Z
High-Z
Valid Data
AT91M63200/M43300
20
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