AT90LS4434-4JI_技术文档

Features

• Utilizes the AVR ^®Enhanced RISC Architecture

• AVR - High Performance and Low Power RISC Architecture

• 118 Powerful Instructions - Most Single Clock Cycle Execution

• 8K bytes of In-System Programmable Flash AT90S/LS8535

4K bytes of In-System Programmable Flash AT90S/LS4434

– SPI Serial Interface for In-System Programming

– Endurance: 1,000 Write/Erase Cycles

• 512 bytes EEPROM AT90S/LS8535

256 bytes EEPROM AT90S/LS4434

– Endurance: 100,000 Write/Erase Cycles

• 512 bytes Internal SRAM AT90S/LS8535

256 bytes Internal SRAM AT90S/LS4434

• 8-Channel, 10-Bit ADC

• 32 x 8 General Purpose Working Registers

• 32 Programmable I/O Lines

• Programmable Serial UART

• V_CC: 4.0 - 6.0V AT90S4434/AT90S8535

• V_CC: 2.7 - 6.0V AT90LS4434/AT90LS8535

• Speed Grades:

0 - 8 MHz AT90S4434/AT90S8535,

8-Bit

Microcontroller

with 4K/8K

BytesIn-System

Programmable

Flash

0 - 4 MHz (AT90LS4434/AT90LS8535

• Power-On Reset Circuit

• Up to 8 MIPS Throughput at 8 MHz

• RTC with Separate Oscillator and Counter Mode

• Two 8-Bit Timer/Counters with Separate Prescaler and Compare Mode

• One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes

• 3 PWM channels

• External and Internal Interrupt Sources

• Programmable Watchdog Timer with On-Chip Oscillator

• On-Chip Analog Comparator

AT90S4434

AT90LS4434

AT90S8535

AT90LS8535

Advance

• Three Sleep Modes: Idle, Power Save, and Power Down

• Programming Lock for Software Security

Description

The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR^®

enhanced RISC architecture. By executing powerful instructions in a single clock

cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing

Information

speed.

(continued)

Pin Configurations

Rev. 1041AS–05/98

Note: This is a summary document. For the complete 80 page

document, please visit our website at www.atmel.com or e-mail at

1

literature@atmel.com and request literature #1041A.

Block Diagram

PA0 - PA7

PC0 - PC7

VCC

GND

PORTA DRIVERS

PORTC DRIVERS

DATA REGISTER

DATA DIR.

REG. PORTA

DATA REGISTER

DATA DIR.

REG. PORTC

PORTA

PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX

ADC

OSCILLATOR

AGND

AREF

XTAL1

XTAL2

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

UART

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD7

The AVR core combines a rich instruction set with 32 gen-

eral purpose working registers. All the 32 registers are

directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving through-

puts up to ten times faster than conventional CISC micro-

controllers.

external interrupts, a programmable serial UART, 8-chan-

nel, 10-bit ADC, programmable Watchdog Timer with inter-

nal oscillator, an SPI serial port and three software

selectable power saving modes. The Idle mode stops the

CPU while allowing the SRAM, timer/counters, SPI port

and interrupt system to continue functioning. The Power

Down mode saves the register contents but freezes the

oscillator, disabling all other chip functions until the next

interrupt or hardware reset. In Power Save mode, the timer

oscillator continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping.

The AT90S4434/8535 provides the following features:

4K/8K bytes of In-System Programmable Flash, 256/512

bytes EEPROM, 256/512 bytes SRAM, 32 general purpose

I/O lines, 32 general purpose working registers, RTC, three

flexible timer/counters with compare modes, internal and

The device is manufactured using Atmel’s high density

non-volatile memory technology. The on-chip ISP Flash

AT90S/LS4434 and AT90S/LS8535

2

AT90S/LS4434 and AT90S/LS8535

allows the program memory to be reprogrammed in-system

through an SPI serial interface or by a conventional nonvol-

atile memory programmer. By combining an 8-bit RISC

CPU with In-System Programmable Flash on a monolithic

chip, the Atmel AT90S4434/8535 is a powerful microcon-

troller that provides a highly flexible and cost effective solu-

tion to many embedded control applications.

Port C is an 8-bit bi-directional I/O port with internal pullup

resistors. The Port C output buffers can sink 20 mA. As

inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. Two Port C

pins can alternatively be used as oscillator for

Timer/Counter2.

Port D (PD7..PD0)

The AT90S4434/8535 AVR is supported with a full suite of

program and system development tools including: C com-

pilers, macro assemblers, program debugger/simulators,

in-circuit emulators, and evaluation kits.

Port D is an 8-bit bidirectional I/O port with internal pull-up

resistors. The Port D output buffers can sink 20 mA. As

inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Comparison between AT90S4434 and AT90S8535

Port D also serves the functions of various special features

of the AT90S4434/8535 as listed on page 59.

The AT90S4434 has 4K bytes of In-System Programmable

Flash, 256 bytes of EEPROM, and 256 bytes of internal

SRAM.

RESET

Reset input. A low on this pin for two machine cycles while

the oscillator is running resets the device.

The AT90S8535 has 8K bytes of In-System Programmable

Flash, 512 bytes of EEPROM, and 512 bytes of internal

SRAM.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

Table 1 summarizes the different memory sizes for the two

devices.

XTAL2

Output from the inverting oscillator amplifier

Table 1. Memory Size Summary

AVCC

Part

Flash

EEPROM

256 bytes

512 bytes

SRAM

This is the supply voltage pin for the A/D Converter. It

should be externally connected to VCC via a low-pass filter.

See page 47 for details on operation of the ADC.

AT90S4434

AT90S8535

4K bytes

8K bytes

256 bytes

512 bytes

AREF

This is the analog reference input for the A/D Converter.

For ADC operations, a voltage in the range AGND to AV_CC

must be applied to this pin.

Pin Descriptions

VCC

Digital supply voltage

GND

AGND

Analog ground. If the board has a separate analog ground

plane, this pin should be connected to this ground plane.

Otherwise, connect to GND.

Digital ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can pro-

vide internal pull-up resistors (selected for each bit). The

Port A output buffers can sink 20mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs

and are externally pulled low, they will source current if the

internal pull-up resistors are activated.

Crystal Oscillators

XTAL1 and XTAL2 are input and output, respectively, of an

inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or a ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.

For the Timer Oscillator pins, PC6(OSC1) and PC7(OSC2),

the crystal is connected directly between the pins. No

external capacitors are needed. The oscillator is optimized

for use with a 32,768 Hz watch crystal. An external clock

signal applied to this pin goes through the same amplifier

having a bandwidth of 256 kHz. The external clock signal

should therefore be in the interval 0 Hz - 256 kHz.

Port A also serves as the analog inputs to the A/D Con-

verter.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O pins with internal pull-up

resistors. The Port B output buffers can sink 20 mA. As

inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features

of the AT90S4434/8535 as listed on page 52.

Port C (PC7..PC0)

3

Figure 1. Oscillator Connections

Figure 2. External Clock Drive Configuration

Architectural Overview

The fast-access register file concept contains 32 x 8-bit

general purpose working registers with a single clock cycle

access time. This means that during one single clock cycle,

one Arithmetic Logic Unit (ALU) operation is executed. Two

operands are output from the register file, the operation is

executed, and the result is stored back in the register file -

in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect

address register pointers for Data Space addressing -

enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the

constant table look up function. These added function reg-

isters are the 16-bits X-register, Y-register and Z-register.

Figure 3. The AT90S4434/8535 AVR Enhanced RISC Architecture

AVR AT90S4434/8535 Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Interrupt

Unit

2K/4K X 16

Program

Memory

SPI

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

Serial

UART

Instruction

Decoder

8-bit

Timer/Counter

ALU

Control Lines

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

256/512 x 8

Data

SRAM

Watchdog

Timer

256/512 x 8

EEPROM

Analog to Digital

Converter

32

I/O Lines

Analog

Comparator

AT90S/LS4434 and AT90S/LS8535

4

AT90S/LS4434 and AT90S/LS8535

The ALU supports arithmetic and logic functions between

registers or between a constant and a register. Single reg-

ister operations are also executed in the ALU. Figure 3

shows the AT90S4434/8535 AVR Enhanced RISC micro-

controller architecture.

enables instructions to be executed in every clock cycle.

The program memory is in-system downloadable Flash

memory.

With the relative jump and call instructions, the whole

2K/4K address space is directly accessed. Most AVR

instructions have a single 16-bit word format. Every pro-

gram memory address contains a 16- or 32-bit instruction.

In addition to the register operation, the conventional mem-

ory addressing modes can be used on the register file as

well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 -

$1F), allowing them to be accessed as though they were

ordinary memory locations.

During interrupts and subroutine calls, the return address

program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and conse-

quently the stack size is only limited by the total SRAM size

and the usage of the SRAM. All user programs must initial-

ize the SP in the reset routine (before subroutines or inter-

rupts are executed). The 9-bit stack pointer SP is read/write

accessible in the I/O space.

The I/O memory space contains 64 addresses for CPU

peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O Memory

can be accessed directly, or as the Data Space locations

following those of the register file, $20 - $5F.

The 256/512 bytes data SRAM can be easily accessed

through the five different addressing modes supported in

the AVR architecture.

The AVR uses a Harvard architecture concept - with sepa-

rate memories and buses for program and data. The pro-

gram memory is executed with a single level pipelining.

While one instruction is being executed, the next instruction

is pre-fetched from the program memory. This concept

The memory spaces in the AVR architecture are all linear

and regular memory maps.

Figure 4. Memory Maps

Program Memory

Data Memory

$0000

$000

32 Gen. Purpose

Working Registers

$001F

$0020

64 I/O Registers

EEPROM

Program Flash

(2K/4K x 16)

(256/512 x 8)

$005F

$0060

$1F/$FF

Internal SRAM

(256/512 x 8)

$015F/$025F

$7FF/$FFF

5

AT90S4434/8535 Register Summary

Address

Name

SREG

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($20)

$02 ($22)

$01 ($21)

$00 ($20)

I

-

T

-

SP6

H

-

SP5

S

-

SP4

V

-

SP3

N

-

SP2

Z

C

21

22

SPH

SPL

SP9

SP1

SP8

SP0

SP7

Reserved

GIMSK

GIFR

TIMSK

TIFR

INT1

INTF1

OCIE2

OCF2

INT0

INTF0

TOIE2

TOV2

-

28

29

30

TICIE1

ICF1

OCIE1A

OCF1A

OCIE1B

OCF1B

TOIE1

TOV1

-

TOIE0

TOV0

Reserved

MCUCR

MCUSR

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

-

SE

-

SM1

-

SM0

-

ISC11

-

ISC10

-

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

31

27

35

36

Timer/Counter0 (8 Bits)

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

-

COM1B0

-

PWM11

CS11

PWM10

CS10

38

39

40

41

45

46

48

50

CTC1

CS12

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

TCCR2

TCNT2

OCR2

-

PWM2

Timer/Counter2 (8 Bits)

Timer/Counter2 Output Compare Register

COM21

COM20

CTC2

CS22

CS21

CS20

ASSR

-

AS2

WDE

TCN2UB

WDP2

OCR2UB

WDP1

TCR2UB

WDP0

WDTCR

Reserved

EEARH

EEARL

EEDR

EECR

PORTA

DDRA

PINA

PORTB

DDRB

PINB

PORTC

DDRC

WDTOE

EEAR9

EEAR0

EEAR7

EEPROM Data Register

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

51

52

70

72

78

81

57

56

60

61

-

EERIE

PORTA3

DDA3

PINA3

PORTB3

DDB3

PINB3

PORTC3

DDC3

PINC3

PORTD3

DDD3

EEMWE

PORTA2

DDA2

PINA2

PORTB2

DDB2

PINB2

PORTC2

DDC2

PINC2

PORTD2

DDD2

EEWE

PORTA1

DDA1

PINA1

PORTB1

DDB1

PINB1

PORTC1

DDC1

PINC1

PORTD1

DDD1

EERE

PORTA0

DDA0

PINA0

PORTB0

DDB0

PINB0

PORTC0

DDC0

PINC0

PORTD0

DDD0

PORTA7

DDA7

PINA7

PORTB7

DDB7

PINB7

PORTC7

DDC7

PINC7

PORTD7

DDD7

PORTA6

DDA6

PINA6

PORTB6

DDB6

PINB6

PORTC6

DDC6

PINC6

PORTD6

DDD6

PORTA5

DDA5

PINA5

PORTB5

DDB5

PINB5

PORTC5

DDC5

PINC5

PORTD5

DDD5

PORTA4

DDA4

PINA4

PORTB4

DDB4

PINB4

PORTC4

DDC4

PINC4

PORTD4

DDD4

PINC

PORTD

DDRD

PIND

SPDR

PIND7

SPI Data Register

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

SPSR

SPCR

UDR

USR

UCR

UBRR

SPIF

SPIE

WCOL

SPE

-

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

UART I/O Data Register

RXC

RXCIE

UART Baud Rate Register

TXC

TXCIE

UDRE

UDRIE

FE

RXEN

OR

TXEN

-

CHR9

RXB8

TXB8

ACSR

ACD

-

ADEN

-

ADC7

-

ACO

-

ADFR

-

ADC5

ACI

-

ADIF

-

ADC4

ACIE

-

ADIE

-

ADC3

ACIC

MUX2

ADPS2

-

ACIS1

MUX1

ADPS1

ADC9

ADC1

ACIS0

MUX0

ADPS0

ADC8

ADC0

67

68

ADMUX

ADCSR

ADCH

ADSC

-

ADC6

ADCL

ADC2

Reserved

AT90S/LS4434

6

AT90S/LS4434 and AT90S/LS8535

AT90S4434/8535 Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Z,N,V

ORI

Rd ← Rd v K

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Rd,K

Rd

Clear Bit(s) in Register

Increment

DEC

TST

CLR

SER

Rd

Decrement

Test for Zero or Minus

Clear Register

Rd ← Rd − 1

Z,N,V

None

Rd ← Rd • Rd

Rd ← Rd Rd

Rd ← $FF

Set Register

BRANCH INSTRUCTIONS

RJMP

IJMP

RCALL

ICALL

RET

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Subroutine Return

Interrupt Return

PC ← Z

PC ← PC + k + 1

PC ← Z

PC ← STACK

2

3

4

RETI

PC ← STACK

4

CPSE

CP

CPC

Rd,Rr

Compare, Skip if Equal

Compare

Compare with Carry

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

Rd − Rr − C

None

Z, N,V,C,H

None

1 / 2

1

Rd,Rr

Rd,K

Rr, b

CPI

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N V= 0) then PC ← PC + k + 1

if (N V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1 / 2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

7

Mnemonics

Operands

Description

Operation

Flags

#Clocks

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Move Between Registers

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← Rr

Rd ← K

Rd ← (X)

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

None

1

2

3

1

2

LD

LDD

LD

LDD

LDS

ST

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

STD

STS

LPM

IN

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

OUT

PUSH

POP

Out Port

Push Register on Stack

Pop Register from Stack

P ← Rr

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

I/O(P,b) ← 1

I/O(P,b) ← 0

None

2

1

3

1

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

Z,C,N,V

None

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

T

None

C

s

Rr, b

Rd, b

Clear Carry

C ← 0

Set Negative Flag

Clear Negative Flag

Set Zero Flag

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

N

Z

I

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

T ← 0

S

V

T

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

Watchdog Reset

H ← 1

H ← 0

H

None

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

AT90S/LS4434 and AT90S/LS8535

8

AT90S/LS4434 and AT90S/LS8535

Ordering Information

Power Supply

Speed (MHz)

Ordering Code

Package

Operation Range

2.7 - 6.0V

4

8

4

8

AT90LS4434-4AC

AT90LS4434-4JC

AT90LS4434-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90LS4434-4AI

AT90LS4434-4JI

AT90LS4434-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

4.0 - 6.0V

2.7 - 6.0V

4.0 - 6.0V

AT90S4434-8AC

AT90S4434-8JC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S4434-8AI

AT90S4434-8JI

AT90S4434-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

AT90LS8535-4AC

AT90LS8535-4JC

AT90LS8535-4PC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90LS8535-4AI

AT90LS8535-4JI

AT90LS8535-4PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

AT90S8535-8AC

AT90S8535-8JC

44A

44J

Commercial

(0°C to 70°C)

40P6

AT90S8535-8AI

AT90S8535-8JI

AT90S8535-8PI

44A

44J

Industrial

(-40°C to 85°C)

40P6

Package Type

44A

44 Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)

44 Lead, Plastic J-Leaded Chip Carrier (PLCC)

44J

40P6

40 Lead, 0.600" Wide, Plastic Dual in Line Package (PDIP)

9

Packaging Information

44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

Dimensions in Millimeters and (Inches)

.045(1.14) X 30° - 45°

.045(1.14) X 45°

PIN NO. 1

IDENTIFY

.012(.305)

.008(.203)

.630(16.0)

.590(15.0)

.656(16.7)

.650(16.5)

SQ

.032(.813)

.026(.660)

.021(.533)

.013(.330)

.695(17.7)

.685(17.4)

SQ

.043(1.09)

.020(.508)

.120(3.05)

.050(1.27) TYP

.500(12.7) REF SQ

.090(2.29)

.180(4.57)

.165(4.19)

.022(.559) X 45° MAX (3X)

*Controlling dimension: millimeters

40P6, 40-Lead, 0.600" Wide,

Plastic Dual Inline Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-011 AC

2.07(52.6)

2.04(51.8)

1

.566(14.4)

.530(13.5)

.090(2.29)

MAX

1.900(48.26) REF

.220(5.59)

MAX

.005(.127)

MIN

SEATING

PLANE

.065(1.65)

.015(.381)

.161(4.09)

.125(3.18)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

.110(2.79)

.090(2.29)

.630(16.0)

.590(15.0)

0

15

REF

.012(.305)

.008(.203)

.690(17.5)

.610(15.5)

AT90S/LS4434 and AT90S/LS8535

10


型号：	AT90LS4434-4JI
厂家：	ATMEL
描述：	8-Bit Microcontroller with 4K/8K Bytes In-System Programmable Flash 8 -bit微控制器4K / 8K字节的系统内可编程闪存闪存微控制器
文件：	总10页 (文件大小：485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90LS4434-4JI [ATMEL]

相关型号：

AT90LS4434-4PC

AT90LS4434-4PI

AT90LS8535

AT90LS8535-4AC

AT90LS8535-4AI

AT90LS8535-4JC

AT90LS8535-4JI

AT90LS8535-4MC

AT90LS8535-4MI

AT90LS8535-4PC

AT90LS8535-4PI

AT90LS8535-8MC