AT90LS8535-4JC_技术文档

Features

• AVR^®– High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

• Data and Nonvolatile Program Memories

– 8K Bytes of In-System Programmable Flash

SPI Serial Interface for In-System Programming

Endurance: 1,000 Write/Erase Cycles

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM

– Programming Lock for Software Security

• Peripheral Features

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– 8-channel, 10-bit ADC

– Programmable UART

– Master/Slave SPI Serial Interface

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and

Capture Modes and Dual 8-, 9-, or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset Circuit

– Real-time Clock (RTC) with Separate Oscillator and Counter Mode

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power Save and Power-down

• Power Consumption at 4 MHz, 3V, 20°C

– Active: 6.4 mA

AT90S8535

AT90LS8535

– Idle Mode: 1.9 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 32 Programmable I/O Lines

– 40-lead PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF

• Operating Voltages

– V_CC: 4.0 - 6.0V AT90S8535

– V_CC: 2.7 - 6.0V AT90LS8535

• Speed Grades:

– 0 - 8 MHz for the AT90S8535

– 0 - 4 MHz for the AT90LS8535

Rev. 1041H–11/01

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Pin Configurations

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AT90S/LS8535

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AT90S/LS8535

Description

The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S8535

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

Block Diagram

Figure 1. The AT90S8535 Block Diagram

PA0 - PA7

PC0 - PC7

VCC

GND

PORTA DRIVERS

PORTC DRIVERS

DATA REGISTER

DATA DIR.

REG. PORTA

DATA REGISTER

DATA DIR.

REG. PORTC

PORTA

PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX

ADC

OSCILLATOR

AGND

AREF

XTAL1

XTAL2

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

X

Y

Z

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

UART

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD7

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The AVR core combines a rich instruction set with 32 general-purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90S8535 provides the following features: 8K bytes of In-System Programmable

Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 general-

purpose working registers, Real-time Clock (RTC), three flexible timer/counters with

compare modes, internal and external interrupts, a programmable serial UART, 8-chan-

nel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial

port and three software-selectable power-saving modes. The Idle Mode stops the CPU

while allowing the SRAM, timer/counters, SPI port and interrupt system to continue

functioning. The Power-down mode saves the register contents but freezes the oscilla-

tor, disabling all other chip functions until the next interrupt or hardware reset. In Power

Save Mode, the timer oscillator continues to run, allowing the user to maintain a timer

base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed in-system

through an SPI serial interface or by a conventional nonvolatile memory programmer.

By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic

chip, the Atmel AT90S8535 is a powerful microcontroller that provides a highly flexible

and cost effective solution to many embedded control applications.

The AT90S8535 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators and evaluation kits.

Pin Descriptions

VCC

Digital supply voltage.

Digital ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated.

Port A also serves as the analog inputs to the A/D Converter.

The Port A pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. Port B also serves the functions of various

special features of the AT90S8535 as listed on page 78.

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source

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AT90S/LS8535

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AT90S/LS8535

current if the pull-up resistors are activated. Two Port C pins can alternatively be used

as oscillator for Timer/Counter2.

The Port C pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S8535 as listed

on page 86.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

AVCC

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used,

this pin must be connected to VCC. If the ADC is used, this pin must be connected to

VCC via a low-pass filter. See page 68 for details on operation of the ADC.

AREF

AGND

AREF is the analog reference input for the A/D Converter. For ADC operations, a volt-

age in the range 2V to AV_CCmust be applied to this pin.

Analog ground. If the board has a separate analog ground plane, this pin should be con-

nected to this ground plane. Otherwise, connect to GND.

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Clock Options

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can

be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used.

Figure 2. Oscillator Connections

MAX 1 HC BUFFER

HC

C2

XTAL2

C1

XTAL1

GND

Note:

When using the MCU Oscillator as a clock for an external device, an HC buffer should be

connected as indicated in the figure.

External Clock

To drive the device from an external clock source, XTAL2 should be left unconnected

while XTAL1 is driven as shown in Figure 3.

Figure 3. External Clock Drive Configuration

Timer Oscillator

For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly

between the pins. No external capacitors are needed. The oscillator is optimized for use

with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not

recommended.

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AT90S/LS8535

Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from

the register file, the operation is executed and the result is stored back in the register file

– in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing, enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-register, Y-register, and Z-register.

Figure 4. The AT90S8535 AVR RISC Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Interrupt

Unit

4K X 16

Program

Memory

SPI

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

Serial

UART

Instruction

Decoder

8-bit

Timer/Counter

ALU

Control Lines

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

512 x 8

Data

SRAM

Watchdog

Timer

512 x 8

EEPROM

Analog to Digital

Converter

32

I/O Lines

Analog

Comparator

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the AT90S8535 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be

used on the register file as well. This is enabled by the fact that the register file is

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assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be

accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can

be accessed directly or as the Data Space locations following those of the register file,

$20 - $5F.

The AVR uses a Harvard architecture concept – with separate memories and buses for

program and data. The program memory is executed with a two-stage pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the program

memory. This concept enables instructions to be executed in every clock cycle. The pro-

gram memory is in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 4K address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM and

consequently, the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 10-bit stack pointer (SP) is read/write-accessible in the

I/O space.

The 512 bytes data SRAM can be easily accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 5. Memory Maps

Program Memory

Data Memory

$0000

$000

32 Gen. Purpose

Working Registers

$001F

$0020

64 I/O Registers

EEPROM

(512 x 8)

Program Flash

(4K x 16)

$005F

$0060

$1FF

Internal SRAM

(512 x 8)

$025F

$FFF

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the status register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the beginning of the program

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AT90S/LS8535

memory. The different interrupts have priority in accordance with their interrupt vector

position. The lower the interrupt vector address, the higher the priority.

General-purpose

Register File

Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.

Figure 6. AVR CPU General-purpose Working Registers

7

0

Addr.

R0

R1

$00

$01

$02

R2

…

R13

R14

R15

R16

R17

…

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register low byte

X-register high byte

Y-register low byte

Y-register high byte

Z-register low byte

Z-register high byte

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception is the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the

LDI instruction for load immediate constant data. These instructions apply to the second

half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND,

and OR and all other operations between two registers or on a single register apply to

the entire register file.

As shown in Figure 6, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any

register in the file.

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X-register, Y-register and Z-

register

The registers R26..R31 have some added functions to their general-purpose usage.

These registers are address pointers for indirect addressing of the Data Space. The

three indirect address registers, X, Y, and Z, are defined in Figure 7.

Figure 7. X-, Y-, and Z-register

15

7

0

X-register

0

7

0

R27 ($1B)

R26 ($1A)

15

0

Y-register

Z-register

7

0

7

0

R29 ($1D)

R31 ($1F)

R28 ($1C)

R30 ($1E)

15

0

7

0

In the different addressing modes, these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories: arithmetic, logical and bit functions.

In-SystemProgrammable The AT90S8535 contains 8K bytes On-chip, In-System Programmable Flash memory

for program storage. Since all instructions are 16- or 32-bit words, the Flash is orga-

Flash Program Memory

nized as 4K x 16. The Flash memory has an endurance of at least 1000 write/erase

cycles. The AT90S8535 Program Counter (PC) is 12 bits wide, thus addressing the

4096 program memory addresses.

See page 99 for a detailed description on Flash data downloading.

See page 12 for the different program memory addressing modes.

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AT90S/LS8535

SRAM Data Memory

Figure 8 shows how the AT90S8535 SRAM memory is organized.

Figure 8. SRAM Organization

Register File

Data Address Space

R0

R1

$0000

$0001

R2

...

$0002

...

R29

R30

R31

$001D

$001E

$001F

I/O Registers

$00

$01

$0020

$0021

$02

...

$0022

...

$3D

$3E

$3F

$005D

$005E

$005F

Internal SRAM

$0060

$0061

...

$025E

$025F

The lower 608 data memory locations address the Register file, the I/O memory and the

internal data SRAM. The first 96 locations address the Register file + I/O memory, and

the next 512 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the

register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode features 63 address locations reached from the

base address given by the Y- or Z-registers.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented and incremented.

The 32 general-purpose working registers, 64 I/O registers and the 512 bytes of internal

data SRAM in the AT90S8535 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

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Program and Data

Addressing Modes

The AT90S8535 AVR RISC microcontroller supports powerful and efficient addressing

modes for access to the program memory (Flash) and data memory (SRAM, register file

and I/O memory). This section describes the different addressing modes supported by

the AVR architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single

Register Rd

Figure 9. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Figure 10. Direct Register Addressing, Two Registers

Rd And Rr

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d

(Rd).

I/O Direct

Figure 11. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or

source register address.

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AT90S/LS8535

Data Direct

Figure 12. Direct Data Addressing

Data Space

$0000

20 19

Rr/Rd

31

16

OP

16 LSBs

15

0

$025F

A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify

the destination or source register.

Data Indirect with

Displacement

Figure 13. Data Indirect with Displacement

Data Space

$0000

15

0

Y OR Z - REGISTER

15

10

6 5

0

OP

n

a

025F

Operand address is the result of the Y- or Z-register contents added to the address con-

tained in six bits of the instruction word.

Data Indirect

Figure 14. Data Indirect Addressing

Data Space

$0000

15

0

X, Y OR Z - REGISTER

$025F

Operand address is the contents of the X-, Y-, or the Z-register.

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Data Indirect with Pre-

decrement

Figure 15. Data Indirect Addressing with Pre-decrement

Data Space

$0000

15

0

X, Y OR Z - REGISTER

-1

$025F

The X-, Y-, or the Z-register is decremented before the operation. Operand address is

the decremented contents of the X-, Y-, or the Z-register.

Data Indirect with Post-

increment

Figure 16. Data Indirect Addressing with Post-increment

Data Space

$0000

15

0

X, Y OR Z - REGISTER

1

$025F

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the

content of the X-, Y-, or the Z-register prior to incrementing.

Constant Addressing Using

the LPM Instruction

Figure 17. Code Memory Constant Addressing

$FFF

Constant byte address is specified by the Z-register contents. The 15 MSBs select word

address (0 - 4K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

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AT90S/LS8535

Indirect Program Addressing, Figure 18. Indirect Program Memory Addressing

IJMP and ICALL

$FFF

Program execution continues at address contained by the Z-register (i.e., the PC is

loaded with the contents of the Z-register).

Relative Program Addressing, Figure 19. Relative Program Memory Addressing

RJMP and RCALL

+1

$FFF

Program execution continues at address PC + k + 1. The relative address k is from -

2048 to 2047.

EEPROM Data Memory

The AT90S8535 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described on page 51 specifying the EEPROM address registers, the

EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 99 for a detailed description.

Memory Access Times

and Instruction

This section describes the general access timing concepts for instruction execution and

internal memory access.

Execution Timing

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock crystal for the chip. No internal clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power-unit.

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Figure 20. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 21 shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed and the result is stored back

to the destination register.

Figure 21. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described

in Figure 22.

Figure 22. On-chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Prev. Address

Address

Data

WR

Data

RD

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AT90S/LS8535

I/O Memory

The I/O space definition of the AT90S8535 is shown in Table 1.

Table 1. AT90S8535 I/O Space

I/O Address

(SRAM Address)

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$35 ($55)

$34 ($45)

$33 ($53)

$32 ($52)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$1F ($3E)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

Name

SREG

Function

Status REGister

SPH

Stack Pointer High

SPL

Stack Pointer Low

GIMSK

GIFR

General Interrupt MaSK register

General Interrupt Flag Register

Timer/Counter Interrupt MaSK register

Timer/Counter Interrupt Flag register

MCU general Control Register

MCU general Status Register

Timer/Counter0 Control Register

Timer/Counter0 (8-bit)

TIMSK

TIFR

MCUCR

MCUSR

TCCR0

TCNT0

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

Timer/Counter1 Control Register A

Timer/Counter1 Control Register B

Timer/Counter1 High Byte

Timer/Counter1 Low Byte

Timer/Counter1 Output Compare Register A High Byte

Timer/Counter1 Output Compare Register A Low Byte

Timer/Counter1 Output Compare Register B High Byte

Timer/Counter1 Output Compare Register B Low Byte

T/C 1 Input Capture Register High Byte

T/C 1 Input Capture Register Low Byte

Timer/Counter2 Control Register

Timer/Counter2 (8-bit)

TCCR2

TCNT2

OCR2

Timer/Counter2 Output Compare Register

Asynchronous Mode Status Register

Watchdog Timer Control Register

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

ASSR

WDTCR

EEARH

EEARL

EEDR

EECR

EEPROM Control Register

PORTA

DDRA

Data Register, Port A

Data Direction Register, Port A

Input Pins, Port A

PINA

PORTB

Data Register, Port B

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Table 1. AT90S8535 I/O Space (Continued)

I/O Address

(SRAM Address)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

Name

DDRB

PINB

Function

Data Direction Register, Port B

Input Pins, Port B

PORTC

DDRC

PINC

Data Register, Port C

Data Direction Register, Port C

Input Pins, Port C

PORTD

DDRD

PIND

Data Register, Port D

Data Direction Register, Port D

Input Pins, Port D

SPDR

SPSR

SPCR

UDR

SPI I/O Data Register

SPI Status Register

SPI Control Register

UART I/O Data Register

UART Status Register

USR

UCR

UART Control Register

UART Baud Rate Register

Analog Comparator Control and Status Register

ADC Multiplexer Select Register

ADC Control and Status Register

ADC Data Register High

ADC Data Register Low

UBRR

ACSR

ADMUX

ADCSR

ADCH

ADCL

Note:

Reserved and unused locations are not shown in the table.

All AT90S8535 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions transferring data between the 32 general-pur-

pose working registers and the I/O space. I/O registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers,

the value of single bits can be checked by using the SBIS and SBIC instructions. Refer

to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as

SRAM, $20 must be added to these addresses. All I/O register addresses throughout

this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any

flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers

$00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

18

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Status Register – SREG

The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

$3F ($5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-

pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after

an interrupt has occurred and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the register file can be copied

into T by the BST instruction and a bit in T can be copied into a bit in a register in the

register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the

Instruction Set description for detailed information.

^{• Bit 4 – S: Sign Bit, S = N}⊄⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-

ment overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the

Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation.

See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logic operation. See the

Instruction Set description for detailed information.

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-

tion Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

19

1041H–11/01

Stack Pointer – SP

The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O space

locations $3E ($5E) and $3D ($5D). As the AT90S8535 data memory has $25F loca-

tions, 10 bits are used.

Bit

15

–

14

–

13

–

12

–

11

–

10

–

9

SP9

SP1

1

8

SP8

SP0

0

$3E ($5E)

$3D ($5D)

SPH

SPL

SP7

7

SP6

6

SP5

5

SP4

4

SP3

3

SP2

2

Read/Write

Initial Value

R

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-

rupt stacks are located. This stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when

data is pushed onto the stack with the PUSH instruction and it is decremented by 2

when an address is pushed onto the stack with subroutine calls and interrupts. The

Stack Pointer is incremented by 1 when data is popped from the stack with the POP

instruction and it is incremented by 2 when an address is popped from the stack with

return from subroutine RET or return from interrupt RETI.

Reset and Interrupt

Handling

The AT90S8535 provides 16 different interrupt sources. These interrupts and the sepa-

rate reset vector each have a separate program vector in the program memory space.

All interrupts are assigned individual enable bits that must be set (one) together with the

I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the

Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list

also determines the priority levels of the different interrupts. The lower the address, the

higher the priority level. RESET has the highest priority, and next is INT0 (the External

Interrupt Request 0), etc.

Table 2. Reset and Interrupt Vectors

Vector No. Program Address Source

Interrupt Definition

Hardware Pin, Power-on Reset and

Watchdog Reset

1

2

$000

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

RESET

INT0

External Interrupt Request 0

External Interrupt Request 1

Timer/Counter2 Compare Match

Timer/Counter2 Overflow

3

INT1

4

TIMER2 COMP

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

5

6

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

7

8

TIMER1 COMPB Timer/Counter1 Compare Match B

9

TIMER1 OVF

TIMER0 OVF

SPI, STC

Timer/Counter1 Overflow

Timer/Counter0 Overflow

SPI Serial Transfer Complete

UART, Rx Complete

10

11

12

UART, RX

20

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Table 2. Reset and Interrupt Vectors (Continued)

Vector No. Program Address Source

Interrupt Definition

13

14

15

16

17

$00C

$00D

$00E

$00F

$010

UART, UDRE

UART, TX

ADC

UART Data Register Empty

UART, Tx Complete

ADC Conversion Complete

EEPROM Ready

EE_RDY

ANA_COMP

Analog Comparator

The most typical and general program setup for the Reset and Interrupt vector

addresses are:

Address Labels

Code

rjmp

Comments

$000

RESET

; Reset Handler

$001

EXT_INT0

EXT_INT1

TIM2_COMP

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_OVF

SPI_STC;

UART_RXC

UART_DRE

UART_TXC

ADC

; IRQ0 Handler

$002

; IRQ1 Handler

$003

; Timer2 Compare Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 CompareA Handler

; Timer1 CompareB Handler

; Timer1 Overflow Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; UART RX Complete Handler

; UDR Empty Handler

$004

$005

$006

$007

$008

$009

$00a

$00b

$00c

$00d

; UART TX Complete Handler

; ADC Conversion Complete Interrupt

$00e

Handler

$00f

$010

rjmp

EE_RDY

; EEPROM Ready Handler

rjmp

ANA_COMP

; Analog Comparator Handler

$011

$012

$013

$014

$015

…

MAIN:

ldi

r16, high(RAMEND); Main program start

out

SPH,r16

ldi

r16, low(RAMEND) ;

SPL,r16

out

<instr> xxx

…

Reset Sources

The AT90S8535 has three sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

more than 50 ns.

Watchdog Reset. The MCU is reset when the Watchdog timer period expires and

the Watchdog is enabled.

During reset, all I/O registers are set to their initial values and the program starts execu-

tion from address $000. The instruction placed in address $000 must be an RJMP

(relative jump) instruction to the reset handling routine. If the program never enables an

interrupt source, the interrupt vectors are not used and regular program code can be

21

1041H–11/01

placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3

defines the timing and electrical parameters of the reset circuitry.

Figure 23. Reset Logic

Table 3. Reset Characteristics (V_CC= 5.0V)

Symbol

Parameter

Min

1.0

0.4

Typ

1.4

Max

1.8

Units

Power-on Reset Threshold (rising)

Power-on Reset Threshold (falling)

RESET Pin Threshold Voltage

V

(1)

V_POT

0.6

0.8

V_RST

t_TOUT

0.6 V_CC

Reset Delay Time-out Period

FSTRT Unprogrammed

11.0

1.0

16.0

1.1

21.0

1.2

ms

Reset Delay Time-out Period

FSTRT Programmed

t_TOUT

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

Table 4. Number of Watchdog Oscillator Cycles

FSTRT

Time-out at V_CC= 5V

1.1 ms

Number of WDT Cycles

Programmed

Unprogrammed

1K

16.0 ms

16K

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As

shown in Figure 23, an internal timer clocked from the Watchdog Timer oscillator pre-

vents the MCU from starting until after a certain period after V_CChas reached the Power-

on Threshold voltage (V_POT), regardless of the V_CCrise time (see Figure 24).

The user can select the start-up time according to typical oscillator start-up time. The

number of WDT oscillator cycles is shown in Table 4. The frequency of the Watchdog

oscillator is voltage-dependent as shown in “Typical Characteristics” on page 107.

If the built-in start-up delay is sufficient, RESET can be connected to V_CCdirectly or via

an external pull-up resistor. By holding the pin low for a period after V_CChas been

applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing

example of this.

22

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 24. MCU Start-up, RESET Tied to V_CC

.

V_POT

VCC

RESET

V_RST

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 25. MCU Start-up, RESET Controlled Externally

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer

than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset. When the applied signal reaches the Reset Threshold

Voltage (V_RST) on its positive edge, the delay timer starts the MCU after the Time-out

period t_TOUThas expired.

Figure 26. External Reset during Operation

23

1041H–11/01

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

t_TOUT. Refer to page 49 for details on operation of the Watchdog.

Figure 27. Watchdog Reset during Operation

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

0

$34 ($54)

Read/Write

Initial Value

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R

0

R

0

R

0

See Bit Description

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

• Bit 1 – EXTRF: External Reset Flag

After a power-on reset, this bit is undefined (X). It can only be set by an External Reset.

A Watchdog Reset will leave this bit unchanged. The bit is cleared by writing a logical

zero to the bit.

• Bit 0 – PORF: Power-on Reset Flag

This bit is only set by a Power-on Reset. A Watchdog Reset or an External Reset will

leave this bit unchanged. The bit is cleared by writing a logical zero to the bit.

To summarize, Table 5 shows the value of these two bits after the three modes of reset.

Table 5. PORF and EXTRF Values after Reset

Reset Source

Power-on Reset

External Reset

Watchdog Reset

EXTRF

Undefined

1

PORF

1

Unchanged

To make use of these bits to identify a reset condition, the user software should clear

both the PORF and EXTRF bits as early as possible in the program. Checking the

PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before

an External or Watchdog Reset occurs, the source of reset can be found by using Table

6.

24

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Table 6. Reset Source Identification

EXTRF

PORF

Reset Source

Watchdog Reset

Power-on Reset

External Reset

Power-on Reset

0

1

0

1

0

1

Interrupt Handling

The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Inter-

rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.

The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding

interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until

the interrupt is enabled or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared

(zero), the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set (one) and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for

as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

General Interrupt Mask

Register – GIMSK

Bit

7

6

5

–

4

–

3

–

2

–

1

–

0

–

$3B ($5B)

Read/Write

Initial Value

INT1

R/W

0

INT0

R/W

0

GIMSK

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and

ISC10) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT1 is configured as an output. The corre-

sponding interrupt of External Interrupt Request 1 is executed from program memory

address $002. See also “External Interrupts.”

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on

the pin will cause an interrupt request even if INT0 is configured as an output. The corre-

25

1041H–11/01

sponding interrupt of External Interrupt Request 0 is executed from program memory

address $001. See also “External Interrupts.”

• Bits 5.0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

General Interrupt Flag

Register – GIFR

Bit

7

INTF1

R/W

0

6

INTF0

R/W

0

5

–

4

–

3

–

2

–

1

–

0

–

$3A ($5A)

Read/Write

Initial Value

GIFR

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – INTF1: External Interrupt Flag1

When an edge or logical change on the INT1 pin triggers an interrupt request, INTF1

becomes set (one). This flag is always cleared (0) when the pin is configured for low-

level interrupts, as the state of a low-level interrupt can be determined by reading the

PIN register.

If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the

interrupt address $002. For edge and logic change interrupts, this flag is cleared when

the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-

cal “1” to it.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge or logical change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). This flag is always cleared (0) when the pin is configured for low-

level interrupts, as the state of a low-level interrupt can be determined by reading the

PIN register.

If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the

interrupt address $001. For edge and logic change interrupts, this flag is cleared when

the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-

cal “1” to it.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

1

–

0

TOIE0

R/W

0

$39 ($59)

Read/Write

Initial Value

TIMSK

R

0

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at

vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the

OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

26

AT90S/LS8535

1041H–11/01

AT90S/LS8535

• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt

(at vector $005) is executed if a capture-triggering event occurs on pin 20, PD6 (ICP)

(i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at

vector $006) is executed if a CompareA match in Timer/Counter1 occurs (i.e., when the

OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at

vector $007) is executed if a CompareB match in Timer/Counter1 occurs (i.e., when the

OCF1B bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector

$008) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8535 and always reads zero.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector

$009) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set

in the Timer/Counter Interrupt Flag Register [TIFR]).

Timer/Counter Interrupt Flag

Register – TIFR

Bit

7

OCF2

R/W

0

6

TOV2

R/W

0

5

4

OCF1A

R/W

0

3

OCF1B

R/W

0

2

TOV1

R/W

0

1

–

0

TOV0

R/W

0

$38 ($58)

Read/Write

Initial Value

ICF1

R/W

0

TIFR

R

0

• Bit 7 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2

and the data in OCR2 (Output Compare Register2). OCF2 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by

writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2

Compare Match Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2

Compare Match Interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2

(Timer/Counter2 Overflow Interrupt Enable) and TOV2 are set (one), the

Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set

when Timer/Counter1 advances from $0000.

27

1041H–11/01

• Bit 5 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the

Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1

is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit

and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the

Timer/Counter1 Capture Interrupt is executed.

• Bit 4 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1A is

cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A

(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the

Timer/Counter1 Compare A Match Interrupt is executed.

• Bit 3 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1B is

cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B

(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the

Timer/Counter1 Compare Match B Interrupt is executed.

• Bit 2 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1

(Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the

Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set

when Timer/Counter1 advances from $0000.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8535 and always reads zero.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0

(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the

Timer/Counter0 Overflow Interrupt is executed. In up/down PWM mode, this bit is set

when Timer/Counter1 advances from $0000.

External Interrupts

The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if

enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.

This feature provides a way of generating a software interrupt. The external interrupts

can be triggered by a falling or rising edge or a low level. This is set up as indicated in

the specification for the MCU Control Register (MCUCR). When the external interrupt is

enabled and is configured as level-triggered, the interrupt will trigger as long as the pin

is held low.

The external interrupts are set up as described in the specification for the MCU Control

Register (MCUCR).

28

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. Four clock cycles after the interrupt flag has been set, the program vector

address for the actual interrupt handling routine is executed. During this 4-clock-cycle

period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is

decremented by 2. The vector is normally a relative jump to the interrupt routine and this

jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes

four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is

popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in

SREG is set. When the AVR exits from an interrupt, it will always return to the main pro-

gram and execute one more instruction before any pending interrupt is served.

MCU Control Register –

The MCU Control Register contains control bits for general MCU functions.

MCUCR

Bit

7

–

6

SE

R/W

0

5

4

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

$35 ($55)

Read/Write

Initial Value

SM1

R/W

0

SM0

R/W

0

MCUCR

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8535 and always reads zero.

• Bit 6 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP

instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the

execution of the SLEEP instruction.

• Bits 5, 4 – SM1/SM0: Sleep Mode Select Bits 1 and 0

These bits select between the three available sleep modes as shown in Table 7.

Table 7. Sleep Mode Select

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

Reserved

Power-down

Power Save

• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bits 1 and 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt mask in the GIMSK is set. The level and edges on the external

INT1 pin that activate the interrupt are defined in Table 8.

29

1041H–11/01

Table 8. Interrupt 1 Sense Control

ISC11

ISC10

Description

0

1

0

1

0

1

The low level of INT1 generates an interrupt request.

Reserved

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

The value on the INT pin is sampled before detecting edges. If edge interrupt is

selected, pulses that last longer than one CPU clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate

an interrupt request as long as the pin is held low.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bits 1 and 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask is set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 9.

Table 9. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Reserved

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

The value on the INT pin is sampled before detecting edges. If edge interrupt is

selected, pulses that last longer than one CPU clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate

an interrupt request as long as the pin is held low.

Sleep Modes

To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a

SLEEP instruction must be executed. The SM0 and SM1 bits in the MCUCR register

select which sleep mode (Idle, Power-down or Power Save) will be activated by the

SLEEP instruction. See Table 7.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up,

executes the interrupt routine and resumes execution from the instruction following

SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset

occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.

Idle Mode

When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the

Idle Mode, stopping the CPU but allowing SPI, UARTs, Analog Comparator, ADC,

Timer/Counters, Watchdog and the interrupt system to continue operating. This enables

the MCU to wake up from external triggered interrupts as well as internal ones like the

Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog

30

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Comparator Interrupt is not required, the Analog Comparator can be powered down by

setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This

will reduce power consumption in Idle Mode. When the MCU wakes up from Idle Mode,

the CPU starts program execution immediately.

Power-down Mode

When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the

Power-down mode. In this mode, the external oscillator is stopped while the external

interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a

Watchdog reset (if enabled) or an external level interrupt can wake up the MCU.

Note that when a level-triggered interrupt is used for wake-up from power-down, the low

level must be held for a time longer than the reset delay Time-out period t_TOUT

.

When waking up from Power-down mode, a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable

after having been stopped. The wake-up period is equal to the reset period, as shown in

Table 3 on page 22.

If the wake-up condition disappears before the MCU wakes up and starts to execute,

e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be

executed.

Power Save Mode

When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power

Save Mode. This mode is identical to Power-down, with one exception: If

Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,

Timer/Counter2 will run during sleep. In addition to the power-down wake-up sources,

the device can also wake up from either a Timer Overflow or Output Compare event

from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in

TIMSK and the global interrupt enable bit in SREG is set.

When waking up from Power Save Mode by an external interrupt, two instruction cycles

are executed before the interrupt flags are updated. When waking up by the asynchro-

nous timer, three instruction cycles are executed before the flags are updated. During

these cycles, the processor executes instructions, but the interrupt condition is not read-

able and the interrupt routine has not started yet.

When waking up from Power Save Mode by an asynchronous timer interrupt, the part

will wake up even if global interrupts are disabled. To ensure that the part executes the

interrupt routine when waking up, also set the global interrupt enable bit in SREG.

If the asynchronous timer is not clocked asynchronously, Power-down mode is recom-

mended instead of Power Save Mode because the contents of the registers in the

asynchronous timer should be considered undefined after wake-up in Power Save

Mode, even if AS2 is 0.

31

1041H–11/01

Timer/Counters

The AT90S8535 provides three general-purpose Timer/Counters – two 8-bit T/Cs and

one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter-

nal oscillator. This oscillator is optimized for use with a 32.768 kHz watch crystal,

enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1

have individual prescaling selection from the same 10-bit prescaling timer.

Timer/Counter2 has its own prescaler. These Timer/Counters can either be used as a

timer with an internal clock time base or as a counter with an external pin connection

that triggers the counting.

Timer/Counter

Prescalers

Figure 28. Prescaler for Timer/Counter0 and 1

TCK0

TCK1

For Timer/Counters 0 and 1, the four different prescaled selections are: CK/8, CK/64,

CK/256 and CK/1024, where CK is the oscillator clock. For the two Timer/Counters 0

and 1, CK, external source and stop can also be selected as clock sources.

Figure 29. Timer/Counter2 Prescaler

CK

PCK2

10-BIT T/C PRESCALER

TOSC1

AS2

0

CS20

CS21

CS22

TIMER/COUNTER2 CLOCK SOURCE

TCK2

32

AT90S/LS8535

1041H–11/01

AT90S/LS8535

The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default con-

nected to the main system clock (CK). By setting the AS2 bit in ASSR, Timer/Counter2

prescaler is asynchronously clocked from the PC6(TOSC1) pin. This enables use of

Timer/Counter2 as a Real-time Clock (RTC). When AS2 is set, pins PC6(TOSC1) and

PC7(TOSC2) are disconnected from Port C. A crystal can then be connected between

the PC6(TOSC1) and PC7(TOSC2) pins to serve as an independent clock source for

Timer/Counter2. The oscillator is optimized for use with a 32.768 kHz crystal. Applying

an external clock source to TOSC1 is not recommended.

8-bit Timer/Counter0

Figure 30 shows the block diagram for Timer/Counter0.

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external

pin. In addition, it can be stopped as described in the specification for the

Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the

Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for

Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter0 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-

quent actions.

Figure 30. Timer/Counter0 Block Diagram

T/C0 OVER-

FLOW IRQ

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C0 CONTROL

REGISTER (TCCR0)

7

0

CK

T0

T/C CLK SOURCE

TIMER/COUNTER0

(TCNT0)

CONTROL

LOGIC

33

1041H–11/01

Timer/Counter0 Control

Register – TCCR0

Bit

7

–

6

–

5

–

4

–

3

–

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

$33 ($53)

Read/Write

Initial Value

TCCR0

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read zero.

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0

The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer/Counter0.

Table 10. Clock 0 Prescale Select

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, Timer/Counter0 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T0, falling edge

External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes

are scaled directly from the CK oscillator clock. If the external pin modes are used, the

corresponding setup must be performed in the actual Data Direction Control Register

(cleared to zero gives an input pin).

Timer Counter 0 – TCNT0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$32 ($52)

Read/Write

Initial Value

LSB

R/W

0

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 is realized as an up-counter with read and write access. If the

Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues

counting in the clock cycle following the write operation.

34

AT90S/LS8535

1041H–11/01

AT90S/LS8535

16-bit Timer/Counter1

Figure 31 shows the block diagram for Timer/Counter1.

Figure 31. Timer/Counter1 Block Diagram

T/C1 OVER-

FLOW IRQ

T/C1 COMPARE T/C1 COMPARE T/C1 INPUT

MATCHA IRQ MATCHB IRQ CAPTURE IRQ

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C1 CONTROL

REGISTER A (TCCR1A)

T/C1 CONTROL

REGISTER B (TCCR1B)

15

8

7

0

T/C1 INPUT CAPTURE REGISTER (ICR1)

CK

T1

CONTROL

LOGIC

CAPTURE

TRIGGER

15

8

7

0

T/C CLEAR

T/C CLOCK SOURCE

UP/DOWN

TIMER/COUNTER1 (TCNT1)

8

7

15

8

7

0

16 BIT COMPARATOR

8

7

15

8

7

TIMER/COUNTER1 OUTPUT COMPARE REGISTER A

TIMER/COUNTER1 OUTPUT COMPARE REGISTER B

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an exter-

nal pin. In addition, it can be stopped as described in the specification for the

Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The different status flags

(Overflow, Compare Match and Capture Event) and control signals are found in the

Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The interrupt enable/dis-

able settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register

(TIMSK).

When Timer/Counter1 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To assure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities

makes the Timer/Counter1 useful for lower speed functions or exact timing functions

with infrequent actions.

The Timer/Counter1 supports two Output Compare functions using the Output Compare

Register 1A and B (OCR1A and OCR1B) as the data sources to be compared to the

Timer/Counter1 contents. The Output Compare functions include optional clearing of

35

1041H–11/01

the counter on compareA match and actions on the Output Compare pins on both com-

pare matches.

Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this

mode the counter and the OCR1A/OCR1B registers serve as a dual glitch-free stand-

alone PWM with centered pulses. Refer to page 40 for a detailed description of this

function.

The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1

contents to the Input Capture Register (ICR1), triggered by an external event on the

Input Capture Pin (ICP). The actual capture event settings are defined by the

Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be

set to trigger the input capture. Refer to “Analog Comparator” on page 66 for details on

this. The ICP pin logic is shown in Figure 32.

Figure 32. ICP Pin Schematic Diagram

If the Noise Canceler function is enabled, the actual trigger condition for the capture

event is monitored over four samples and all four must be equal to activate the capture

flag. The input pin signal is sampled at XTAL clock frequency.

Timer/Counter1 Control

Register A – TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

–

2

–

1

PWM11

R/W

0

PWM10

R/W

0

$2F ($4F)

Read/Write

Initial Value

TCCR1A

R

0

R

0

• Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a

compare match in Timer/Counter1. Any output pin actions affect pin OC1A (Output

CompareA pin 1). This is an alternative function to an I/O port and the corresponding

direction control bit must be set (one) to control an output pin. The control configuration

is shown in Table 11.

• Bits 5, 4 – COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0

The COM1B1 and COM1B0 control bits determine any output pin action following a

compare match in Timer/Counter1. Any output pin actions affect pin OC1B (Output

CompareB). This is an alternative function to an I/O port and the corresponding direction

control bit must be set (one) to control an output pin. The control configuration is given in

Table 11.

36

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Table 11. Compare 1 Mode Select

COM1X1

COM1X0

Description

0

1

0

1

0

1

Timer/Counter1 disconnected from output pin OC1X

Toggle the OC1X output line.

Clear the OC1X output line (to zero).

Set the OC1X output line (to one).

Note:

X = A or B.

In PWM mode, these bits have a different function. Refer to Table 15 for a detailed

description. When changing the COM1X1/COM1X0 bits, Output Compare Interrupt 1

must be disabled by clearing their Interrupt Enable bits in the TIMSK Register. Other-

wise an interrupt can occur when the bits are changed.

• Bits 3..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read zero.

• Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits

These bits select PWM operation of Timer/Counter1 as specified in Table 12. This mode

is described on page 40.

Table 12. PWM Mode Select

PWM11

PWM10

Description

0

1

0

1

0

1

PWM operation of Timer/Counter1 is disabled

Timer/Counter1 is an 8-bit PWM

Timer/Counter1 is a 9-bit PWM

Timer/Counter1 is a 10-bit PWM

Timer/Counter1 Control

Register B – TCCR1B

Bit

7

6

5

–

4

–

3

CTC1

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

$2E ($4E)

Read/Write

Initial Value

ICNC1

R/W

0

ICES1

R/W

0

TCCR1B

R

0

R

0

• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)

When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function

is disabled. The input capture is triggered at the first rising/falling edge sampled on the

ICP (input capture pin) as specified. When the ICNC1 bit is set (one), four successive

samples are measured on the ICP (input capture pin), and all samples must be high/low

according to the input capture trigger specification in the ICES1 bit. The actual sampling

frequency is XTAL clock frequency.

• Bit 6 – ICES1: Input Capture1 Edge Select

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the

Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While

the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Cap-

ture Register (ICR1) on the rising edge of the input capture pin (ICP).

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read zero.

37

1041H–11/01

• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match

When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock

cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-

ues counting and is unaffected by a compare match. Since the compare match is

detected in the CPU clock cycle following the match, this function will behave differently

when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used

and the compareA register is set to C, the timer will count as follows if CTC1 is set:

... | C-2 | C-1 | C | 0 | 1 |...

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|...

In PWM mode, this bit has no effect.

• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0

The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.

Table 13. Clock 1 Prescale Select

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter1 is stopped.

CK

CK/8

CK/64

CK/256

CK/1024

External Pin T1, falling edge

External Pin T1, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used, the corresponding setup must be performed in the actual Direction Control Regis-

ter (cleared to zero gives an input pin).

Timer/Counter1 – TCNT1H

AND TCNT1L

Bit

15

14

13

12

11

10

9

8

$2D ($4D)

$2C ($4C)

MSB

TCNT1H

TCNT1L

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To

ensure that both the high and low bytes are read and written simultaneously when the

CPU accesses these registers, the access is performed using an 8-bit temporary regis-

ter (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and

ICR1. If the main program and also interrupt routines perform access to registers using

38

AT90S/LS8535

1041H–11/01

AT90S/LS8535

TEMP, interrupts must be disabled during access from the main program (and from

interrupt routines if interrupts are allowed from within interrupt routines).

•

TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the written data is placed in the

TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is

combined with the byte data in the TEMP register, and all 16 bits are written to the

TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte

TCNT1H must be accessed first for a full 16-bit register write operation.

•

TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent

to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.

When the CPU reads the data in the high byte TCNT1H, the CPU receives the data

in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for

a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read

and write access. If Timer/Counter1 is written to and a clock source is selected, the

Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-

ten value.

Timer/Counter1 Output

Compare Register – OCR1AH

AND OCR1AL

Bit

15

14

13

12

11

10

9

8

$2B ($4B)

$2A ($4A)

MSB

OCR1AH

OCR1AL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

Timer/Counter1 Output

Compare Register – OCR1BH

AND OCR1BL

Bit

15

14

13

12

11

10

9

8

$29 ($49)

$28 ($48)

MSB

OCR1BH

OCR1BL

LSB

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

Read/Write

Initial Value

R/W

0

The output compare registers are 16-bit read/write registers.

The Timer/Counter1 Output Compare registers contain the data to be continuously com-

pared with Timer/Counter1. Actions on compare matches are specified in the

Timer/Counter1 Control and Status registers. A compare match only occurs if

Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A

or OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the

compare event.

Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a tem-

porary register (TEMP) is used when OCR1A/B are written to ensure that both bytes are

updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the

data is temporarily stored in the TEMP register. When the CPU writes the low byte,

39

1041H–11/01

OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or

OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a

full 16-bit register write operation.

The TEMP register is also used when accessing TCNT1 and ICR1. If the main program

and interrupt routines perform access to registers using TEMP, interrupts must be dis-

abled during access from the main program.

Timer/Counter1 Input Capture

Register – ICR1H AND ICR1L

Bit

15

14

13

12

11

10

9

8

$27 ($47)

$26 ($46)

MSB

ICR1H

ICR1L

LSB

0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

Read/Write

Initial Value

R

0

The Input Capture Register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting [ICES1]) of

the signal at the input capture pin (ICP) is detected, the current value of the

Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,

the input capture flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register

(TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously.

When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of

the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in

the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently,

the low-byte ICR1L must be accessed first for a full 16-bit register read operation.

The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the

main program and interrupt routines perform access to registers using TEMP, interrupts

must be disabled during access from the main program.

Timer/Counter1 In PWM Mode When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A

(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,

free-running, glitch-free and phase-correct PWM with outputs on the PD5(OC1A) and

PD4(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000

to TOP (see Table 14), where it turns and counts down again to zero before the cycle is

repeated. When the counter value matches the contents of the 10 least significant bits of

OCR1A or OCR1B, the PD5(OC1A)/PD4(OC1B) pins are set or cleared according to

the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1

Control Register (TCCR1A). Refer to Table 15 for details.

Table 14. Timer TOP Values and PWM Frequency

PWM Resolution

Timer TOP value

$00FF (255)

Frequency

_TCK1/510

_TCK1/1022

f_TCK1/2046

8-bit

9-bit

f

$01FF (511)

f

10-bit

$03FF(1023)

Note that if the Compare Register contains the TOP value and the prescaler is not in

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the

40

AT90S/LS8535

1041H–11/01

AT90S/LS8535

up-counting and down-counting values are reached simultaneously. When the prescaler

is in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter

reaches TOP value, but the down-counting compare match is not interpreted to be

reached before the next time the counter reaches the TOP value, making a one-period

PWM pulse.

Table 15. Compare1 Mode Select in PWM Mode

COM1X1 COM1X0 Effect on OCX1

0

1

Not connected

Cleared on compare match, up-counting. Set on compare match,

down-counting (non-inverted PWM).

1

0

Cleared on compare match, down-counting. Set on compare match,

up-counting (inverted PWM).

1

Note:

X = A or B

Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,

are transferred to a temporary location. They are latched when Timer/Counter1 reaches

the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the

event of an unsynchronized OCR1A/OCR1B write. See Figure 33 for an example.

Figure 33. Effects of Unsynchronized OCR1 Latching

Compare Value changes

Counter alue

V

Compare V

alue

Output OC1X

PWM

Synchronized

OCR1X Latch

Compare Value changes

Counter

Value

Compare Value

PWM Output OC1X

Glitch

Unsynchronized

OCR1X Latch

Note: X = A or B

During the time between the write and the latch operations, a read from OCR1A or

OCR1B will read the contents of the temporary location. This means that the most

recently written value always will read out of OCR1A/B.

When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated

to low or high on the next compare match according to the settings of

COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 16.

Table 16. PWM Outputs OCR1X = $0000 or TOP

COM1X1

COM1X0

OCR1X

Output OC1X

1

0

$0000

L

41

1041H–11/01

Table 16. PWM Outputs OCR1X = $0000 or TOP

COM1X1

COM1X0

OCR1X

TOP

Output OC1X

1

0

1

H

L

$0000

TOP

1

Note:

X = A

In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from

$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,

i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global

interrupts are enabled. This also applies to the Timer Output Compare1 flags and

interrupts.

8-bit Timer/Counter2

Figure 34 shows the block diagram for Timer/Counter2.

Figure 34. Timer/Counter2 Block Diagram

T/C2 OVER- T/C2 COMPARE

FLOW IRQ

MATCH IRQ

8-BIT DATA BUS

8-BIT ASYNCH T/C2 DATA BUS

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C2 CONTROL

REGISTER (TCCR2)

7

0

T/C CLEAR

CK

TIMER/COUNTER2

(TCNT2)

T/C CLK SOURCE

UP/DOWN

CONTROL

LOGIC

TOSC1

0

8-BIT COMPARATOR

0

OUTPUT COMPARE

REGISTER2 (OCR2)

ASYNCH. STATUS

REGISTER (ASSR)

CK

PCK2

SYNCH UNIT

The 8-bit Timer/Counter2 can select clock source from PCK2 or prescaled PCK2. It can

also be stopped as described in the specification for the Timer/Counter Control Register

(TCCR2).

The different status flags (Overflow and Compare Match) are found in the

Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the

42

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Timer/Counter Control Register (TCCR2). The interrupt enable/disable settings are

found in the Timer/Counter Interrupt Mask Register (TIMSK).

This module features a high-resolution and a high-accuracy usage with the lower pres-

caling opportunities. Similarly, the high prescaling opportunities make this unit useful for

lower speed functions or exact timing functions with infrequent actions.

The Timer/Counter supports an Output Compare function using the Output Compare

Register (OCR2) as the data source to be compared to the Timer/Counter contents.The

Output Compare function includes optional clearing of the counter on compare match

and action on the Output Compare Pin, PD7(OC2), on compare match. Writing to

PORTD7 does not set the OC2 value to a predetermined value.

Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode,

Timer/Counter2 and the Output Compare Register serve as a glitch-free, stand-alone

PWM with centered pulses. Refer to page 45 for a detailed description of this function.

Timer/Counter2 Control

Register – TCCR2

Bit

7

–

6

PWM2

R/W

0

5

COM21

R/W

0

4

COM20

R/W

0

3

CTC2

R/W

0

2

CS22

R/W

0

1

CS21

R/W

0

CS20

R/W

0

$25 ($45)

Read/Write

Initial Value

TCCR2

R

0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8535 and always reads as zero.

• Bit 6 – PWM2: Pulse Width Modulator Enable

When set (one), this bit enables PWM mode for Timer/Counter2. This mode is described

on page 45.

• Bits 5, 4 – COM21, COM20: Compare Output Mode, Bits 1 and 0

The COM21 and COM20 control bits determine any output pin action following a com-

pare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an

alternative function to an I/O port and the corresponding direction control bit must be set

(one) to control an output pin. The control configuration is shown in Table 17.

Table 17. Compare Mode Select

COM21

COM20

Description

0

1

0

1

0

1

Timer/Counter disconnected from output pin OC2

Toggle the OC2 output line.

Clear the OC2 output line (to zero).

Set the OC2 output line (to one).

Note:

In PWM mode, these bits have a different function. Refer to Table 19 for a detailed

description.

• Bit 3 – CTC2: Clear Timer/Counter on Compare Match

When the CTC2 control bit is set (one), Timer/Counter2 is reset to $00 in the CPU clock

cycle after a compare match. If the control bit is cleared, Timer/Counter2 continues

counting and is unaffected by a compare match. Since the compare match is detected in

the CPU clock cycle following the match, this function will behave differently when a

prescaling higher than 1 is used for the timer. When a prescaling of 1 is used and the

compare2 register is set to C, the timer will count as follows if CTC2 is set:

... | C-2 | C-1 | C | 0 | 1 |...

43

1041H–11/01

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 | 1, 1, 1,...

In PWM mode, this bit has no effect.

• Bits 2, 1, 0 – CS22, CS21, CS20: Clock Select Bits 2, 1 and 0

The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter2.

Table 18. Timer/Counter2 Prescale Select

CS22

CS21

CS20

Description

Timer/Counter2 is stopped.

PCK2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PCK2/ 8

PCK2/ 32

PCK2/ 64

PCK2/128

PCK2/256

PCK2/1024

The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes

are scaled directly from the CK oscillator clock.

Timer/Counter2 – TCNT2

Bit

7

6

5

4

3

2

1

0

$24 ($44)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

TCNT2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This 8-bit register contains the value of Timer/Counter2.

Timer/Counter2 is realized as an up or up/down (in PWM mode) counter with read and

write access. If the Timer/Counter2 is written to and a clock source is selected, it contin-

ues counting in the timer clock cycle following the write operation.

Timer/Counter2 Output

Compare Register – OCR2

Bit

7

6

5

4

3

2

1

0

$23 ($43)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

OCR2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register is an 8-bit read/write register.

The Timer/Counter Output Compare Register contains the data to be continuously com-

pared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A

compare match only occurs if Timer/Counter2 counts to the OCR2 value. A software

write that sets TCNT2 and OCR2 to the same value does not generate a compare

match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the

compare event.

44

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Timer/Counter2 in PWM Mode When the PWM mode is selected, Timer/Counter2 and the Output Compare Register

(OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on

the PD7(OC2) pin. Timer/Counter2 acts as an up/down counter, counting up from $00 to

$FF, where it turns and counts down again to zero before the cycle is repeated. When

the counter value matches the contents of the Output Compare Register, the PD7(OC2)

pin is set or cleared according to the settings of the COM21/COM20 bits in the

Timer/Counter2 Control Register (TCCR2). Refer to Table 19 for details.

Table 19. Compare Mode Select in PWM Mode

COM21 COM20 Effect on Compare Pin

0

1

0

1

0

Not connected

Cleared on compare match, up-counting. Set on compare match, down-

counting (non-inverted PWM).

1

Cleared on compare match, down-counting time-out. Set on compare

match, up-counting (inverted PWM).

Note that in PWM mode, the Output Compare Register is transferred to a temporary

location when written. The value is latched when the Timer/Counter reaches $FF. This

prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-

chronized OCR2 write. See Figure 35 for an example.

Figure 35. Effects of Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

PWM Output

Synchronized OCR Latch

Compare Value changes

Counter Value

Compare Value

PWM Output

Glitch

Unsynchronized OCR Latch

During the time between the write and the latch operation, a read from OCR2 will read

the contents of the temporary location. This means that the most recently written value

always will read out of OCR2.

When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM

output changes to low or high immediately according to the settings of COM21/COM20.

This is shown in Table 20.

Table 20. PWM Outputs OCR2 = $00 or $FF

COM21

COM20

OCR2

Output PWM2

1

0

$00

L

45

1041H–11/01

Table 20. PWM Outputs OCR2 = $00 or $FF

COM21

COM20

OCR2

$FF

Output PWM2

1

0

1

H

L

$00

$FF

In PWM mode, the Timer Overflow Flag (TOV2) is set when the counter advances from

$00. Timer Overflow Interrupt2 operates exactly as in normal Timer/Counter mode, i.e.,

it is executed when TOV2 is set, provided that Timer Overflow Interrupt and global inter-

rupts are enabled. This also applies to the Timer Output Compare flag and interrupt.

The frequency of the PWM will be Timer Clock Frequency divided by 510.

Asynchronous Status

Register – ASSR

Bit

7

–

6

–

5

–

4

–

3

2

1

0

$22 ($22)

Read/Write

Initial Value

AS2

R/W

0

TCN2UB

OCR2UB

TCR2UB

ASSR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..4 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and

PC7 become connected to a crystal oscillator and cannot be used as general I/O pins.

When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK.

When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might

get corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes

set (one). When TCNT2 has been updated from the temporary storage register, this bit

is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT2 is ready to be

updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes

set (one). When OCR2 has been updated from the temporary storage register, this bit is

cleared (zero) by hardware. A logical “0” in this bit indicates that OCR2 is ready to be

updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes

set (one). When TCCR2 has been updated from the temporary storage register, this bit

is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR2 is ready to be

updated with a new value.

If a write is performed to any of the three Timer/Counter2 registers while its Update Busy

flag is set (one), the updated value might get corrupted and cause an unintentional inter-

rupt to occur.

The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading

TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the

temporary storage register is read.

46

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Asynchronous Operation of

Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

•

Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the timer registers TCNT2, OCR2 and TCCR2 might get corrupted.

A safe procedure for switching clock source is:

1. Disable the Timer/Counter2 interrupts OCIE2 and TOIE2.

2. Select clock source by setting AS2 as appropriate.

3. Write new values to TCNT2, OCR2 and TCCR2.

4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB and

TCR2UB.

5. Clear the Timer/Counter2 interrupt flags.

6. Clear the TOV2 and OCF2 flags in TIFR.

7. Enable interrupts, if needed.

•

When writing to one of the registers TCNT2, OCR2 or TCCR2, the value is

transferred to a temporary register and latched after two positive edges on TOSC1.

The user should not write a new value before the contents of the temporary register

have been transferred to their destination. Each of the three mentioned registers

have their individual temporary register. For example, writing to TCNT2 does not

disturb an OCR2 write in progress. To detect that a transfer to the destination

register has taken place, an Asynchronous Status Register (ASSR) has been

implemented.

When entering a Power Save Mode after having written to TCNT2, OCR2 or

TCCR2, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will go to sleep

before the changes have had any effect. This is extremely important if the Output

Compare2 interrupt is used to wake up the device; Output Compare is disabled

during write to OCR2 or TCNT2. If the write cycle is not finished (i.e., the user goes

to sleep before the OCR2UB bit returns to zero), the device will never get a compare

match and the MCU will not wake up.

If Timer/Counter2 is used to wake up the device from Power Save Mode,

precautions must be taken if the user wants to re-enter Power Save Mode: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake up and

re-entering Power Save Mode is less than one TOSC1 cycle, the interrupt will not

occur and the device will fail to wake up. If the user is in doubt whether the time

before re-entering Power Save is sufficient, the following algorithm can be used to

ensure that one TOSC1 cycle has elapsed:

1. Write a value to TCCR2, TCNT2 or OCR2.

2. Wait until the corresponding Update Busy flag in ASSR returns to zero.

3. Enter Power Save Mode.

•

When the asynchronous operation is selected, the 32 kHz oscillator for

Timer/Counter2 is always running, except in Power-down mode. After a power-up

reset or wake-up from power-down, the user should be aware of the fact that this

oscillator might take as long as one second to stabilize. The user is advised to wait

for at least one second before using Timer/Counter2 after power-up or wake-up from

power-down. The content of all Timer/Counter2 registers must be considered lost

after a wake-up from power-down due to the unstable clock signal upon start-up,

regardless of whether the oscillator is in use or a clock signal is applied to the TOSC

pin.

•

Description of wake-up from Power Save Mode when the timer is clocked

asynchronously: When the interrupt condition is met, the wake-up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at

47

1041H–11/01

least one before the processor can read the counter value. After wake-up, the MCU

is halted for four cycles, it executes the interrupt routine, and resumes execution

from the instruction following SLEEP.

•

During asynchronous operation, the synchronization of the interrupt flags for the

asynchronous timer takes three processor cycles plus one timer cycle. The timer is

therefore advanced by at least 1 before the processor can read the timer value

causing the setting of the interrupt flag. The output compare pin is changed on the

timer clock and is not synchronized to the processor clock.

48

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in

Table 21. See characterization data for typical values at other V_CClevels. The WDR

(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle

periods can be selected to determine the reset period. If the reset period expires without

another Watchdog reset, the AT90S8535 resets and executes from the reset vector. For

timing details on the Watchdog reset, refer to page 22.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 36. Watchdog Timer

Oscillator

1 MHz at V_CC= 5V

350 kHz at V_CC= 3V

Watchdog Timer Control

Register – WDTCR

Bit

7

–

6

–

5

–

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

$21 ($41)

Read/Write

Initial Value

WDTCR

R

0

R

0

R

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared

(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE

bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be

followed:

49

1041H–11/01

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to “1” before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown in Table 21.

Table 21. Watchdog Timer Prescale Select

Number of WDT

Oscillator Cycles

Typical Time-out

at V_CC= 3.0V

Typical Time-out

at V_CC= 5.0V

WDP2

WDP1

WDP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

15 ms

30 ms

60 ms

0.12 s

0.24 s

0.49 s

0.97 s

1.9 s

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

3.0 s

6.0 s

Note:

The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical

Characteristics section.

The WDR (Watchdog Reset) instruction should always be executed before the Watchdog

Timer is enabled. This ensures that the reset period will be in accordance with the

Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the

Watchdog Timer may not start to count from zero.

To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.

50

AT90S/LS8535

1041H–11/01

AT90S/LS8535

EEPROM Read/Write The EEPROM access registers are accessible in the I/O space.

Access

The write access time is in the range of 2.5 - 4 ms, depending on the V_CCvoltages. A

self-timing function lets the user software detect when the next byte can be written. A

special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to

accept new data.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

EEPROM Address Register –

EEARH and EEARL

Bit

15

14

13

12

11

10

9

8

EEAR8

EEAR0

0

$1F ($3F)

$1E ($3E)

–

EEARH

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

7

R

6

R

5

R

4

R

3

R

2

R

1

R

Read/Write

Initial Value

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

The EEPROM address registers (EEARH and EEARL) specify the EEPROM address in

the 512-byte EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 511.

EEPROM Data Register –

EEDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$1D ($3D)

Read/Write

Initial Value

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to

the EEPROM in the address given by the EEAR register. For the EEPROM read opera-

tion, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

EEPROM Control Register –

EECR

Bit

7

–

6

–

5

–

4

–

3

EERIE

R/W

0

2

EEMWE

R/W

0

1

EEWE

R/W

0

EERE

R/W

0

$1C ($3C)

Read/Write

Initial Value

EECR

R

0

R

0

R

0

R

0

• Bit 7..4 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is

enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt

generates a constant interrupt when EEWE is cleared (zero).

51

1041H–11/01

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be

written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the

selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE

has been set (one) by software, hardware clears the bit to zero after four clock cycles.

See the description of the EEWE bit for a EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be set to write the value into

the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed

when writing the EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEARL and EEARH (optional).

3. Write new EEPROM data to EEDR (optional).

4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to

the EEMWE bit, the EEWE bit must be written to “0” in the same cycle).

5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR and EEDR registers will

be modified, causing the interrupted EEPROM access to fail. It is recommended to have

the global interrupt flag cleared during the four last steps to avoid these problems.

When the write access time (typically 2.5 ms at V_CC= 5V or 4 ms at V_CC= 2.7V) has

elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit

and wait for a zero before writing the next byte. When EEWE has been set, the CPU is

halted for two clock cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When

the correct address is set up in the EEAR register, the EERE bit must be set. When the

EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.

The EEPROM read access takes one instruction and there is no need to poll the EERE

bit. When EERE has been set, the CPU is halted for four clock cycles before the next

instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress when new data or address is written to the EEPROM I/O registers, the

write operation will be interrupted and the result is undefined.

52

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Prevent EEPROM

Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using the EEPROM and the same design solutions

should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommen-

dations (one is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This is best done by an external low V_CCReset Protection circuit, often

referred to as a Brown-out Detector (BOD). Please refer to application note AVR

180 for design considerations regarding power-on reset and low-voltage

detection.

2. Keep the AVR core in Power-down Sleep Mode during periods of low V_CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the EEPROM registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from

software is not required. Flash memory cannot be updated by the CPU and will

not be subject to corruption.

53

1041H–11/01

Serial Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the AT90S8535 and peripheral devices or between several AVR devices. The

AT90S8535 SPI features include the following:

• Full-duplex, 3-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• End-of-transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

Figure 37. SPI Block Diagram

The interconnection between master and slave CPUs with SPI is shown in Figure 38.

The PB7(SCK) pin is the clock output in the Master Mode and is the clock input in the

Slave Mode. Writing to the SPI Data Register of the master CPU starts the SPI clock

generator and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)

pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the

end-of-transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR regis-

ter is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to select

an individual slave SPI device. The two shift registers in the master and the slave can be

considered as one distributed 16-bit circular shift register. This is shown in Figure 38.

When data is shifted from the master to the slave, data is also shifted in the opposite

direction, simultaneously. During one shift cycle, data in the master and the slave is

interchanged.

54

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 38. SPI Master-slave Interconnection

MSB

MASTER

LSB

MSB

MASTER

LSB

MISO

MOSI

MISO

MOSI

8 BIT SHIFT REGISTER

SPI

SCK

SS

SCK

CLOCK GENERATOR

SS

V_CC

The system is single-buffered in the transmit direction and double-buffered in the

receive direction. This means that bytes to be transmitted cannot be written to the SPI

Data Register before the entire shift cycle is completed. When receiving data, however,

a received byte must be read from the SPI Data Register before the next byte has been

completely shifted in. Otherwise, the first byte is lost.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is

overridden according to Table 22.

Table 22. SPI Pin Overrides

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

See “Alternate Functions of Port B” on page 79 for a detailed description of how to

define the direction of the user-defined SPI pins.

55

1041H–11/01

SS Pin Functionality

When the SPI is configured as a master (MSTR in SPCR is set), the user can determine

the direction of the SS pin. If SS is configured as an output, the pin is a general output

pin, which does not affect the SPI system. If SS is configured as an input, it must be held

high to ensure master SPI operation. If the SS pin is driven low by peripheral circuitry

when the SPI is configured as master with the SS pin defined as an input, the SPI sys-

tem interprets this as another master selecting the SPI as a slave and starting to send

data to it. To avoid bus contention, the SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a

result of the SPI becoming a slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set and if the SPI interrupt is enabled and the I-bit in

SREG are set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master Mode and there exists a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. Once the MSTR bit has been cleared by a slave select, it must be set by the

user to re-enable the SPI Master Mode.

When the SPI is configured as a slave, the SS pin is always input. When SS is held low,

the SPI is activated and MISO becomes an output if configured so by the user. All other

pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once

the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI

will stop sending and receiving immediately and both data received and data sent must

be considered as lost.

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 39 and Figure 40.

Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0

SCK CYCLE#

(FOR REFERENCE)

1

2

3

4

5

6

7

8

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MSB

6

5

4

3

2

1

LSB

MISO

(FROM SLAVE)

MSB

6

5

4

3

2

1

*

SS (TO SLAVE)

SAMPLE

*Not defined but normally MSB of character just received.

56

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0

SPI Control Register – SPCR

Bit

7

SPIE

R/W

0

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

SPR1

R/W

0

SPR0

R/W

0

$0D ($2D)

Read/Write

Initial Value

SPE

R/W

0

SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set

and the global interrupts are enabled.

• Bit 6 – SPE: SPI Enable

When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is set (one), the LSB of the data word is transmitted first.

When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI Mode when set (one) and Slave SPI Mode when cleared

(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be

cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-

enable SPI Master Mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is

low when idle. Refer to Figure 39. and Figure 40. for additional information.

• Bit 2 – CPHA: Clock Phase

Refer to Figure 40 or Figure 41 for the functionality of this bit.

57

1041H–11/01

• Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a master. SPR1 and

SPR0 have no effect on the slave. The relationship between SCK and the oscillator

clock frequency f_clis shown in Table 23.

Table 23. Relationship between SCK and the Oscillator Frequency

SPR1

SPR0

SCK Frequency

0

1

0

1

0

1

f_cl/4

f_cl/16

f_cl/64

f_cl/128

SPI Status Register – SPSR

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

–

$0E ($2E)

Read/Write

Initial Value

WCOL

SPSR

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-

ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and

is driven low when the SPI is in Master Mode, this will also set the SPIF flag. SPIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set

(one), then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write Collision flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-

ister with WCOL set (one) and then accessing the SPI Data Register.

• Bit 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and will always read as zero.

The SPI interface on the AT90S8535 is also used for program memory and EEPROM

downloading or uploading. See page 99 for serial programming and verification.

SPI Data Register – SPDR

Bit

7

6

5

4

3

2

1

0

$0F ($2F)

Read/Write

Initial Value

MSB

R/W

X

LSB

R/W

X

SPDR

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a read/write register used for data transfer between the regis-

ter file and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

58

AT90S/LS8535

1041H–11/01

AT90S/LS8535

UART

The AT90S8535 features a full duplex (separate receive and transmit registers) Univer-

sal Asynchronous Receiver and Transmitter (UART). The main features are:

• Baud Rate Generator that can Generate a Large Number of Baud Rates (bps)

• High Baud Rates at Low XTAL Frequencies

• 8 or 9 Bits Data

• Noise Filtering

• Overrun Detection

• Framing Error Detection

• False Start Bit Detection

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Buffered Transmit and Receive

Data Transmission

A block schematic of the UART transmitter is shown in Figure 41.

Figure 41. UART Transmitter

Data transmission is initiated by writing the data to be transmitted to the UART I/O Data

Register, UDR. Data is transferred from UDR to the Transmit shift register when:

•

A new character is written to UDR after the stop bit from the previous character has

been shifted out. The shift register is loaded immediately.

•

A new character is written to UDR before the stop bit from the previous character

has been shifted out. The shift register is loaded when the stop bit of the character

currently being transmitted is shifted out.

If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the

shift register. The UDRE (UART Data Register Empty) bit in the UART Status Register,

USR, is set. When this bit is set (one), the UART is ready to receive the next character.

At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0

of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word

59

1041H–11/01

is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in

UCR is transferred to bit 9 in the Transmit shift register.

On the baud rate clock following the transfer operation to the shift register, the start bit is

shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been

shifted out, the shift register is loaded if any new data has been written to the UDR dur-

ing the transmission. During loading, UDRE is set. If there is no new data in the UDR

register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR

is written again. When no new data has been written and the stop bit has been present

on TXD for one bit length, the TX Complete flag (TXC) in USR is set.

The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is

cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART

Transmitter will be connected to PD1, which is forced to be an output pin regardless of

the setting of the DDD1 bit in DDRD.

Data Reception

Figure 42 shows a block diagram of the UART Receiver.

Figure 42. UART Receiver

The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times

the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as

the falling edge of a start bit and the start bit detection sequence is initiated. Let sample

60

AT90S/LS8535

1041H–11/01

AT90S/LS8535

1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the

RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be

logical “1”s, the start bit is rejected as a noise spike and the receiver starts looking for

the next 1-to-0 transition.

If however, a valid start bit is detected, sampling of the data bits following the start bit is

performed. These bits are also sampled at samples 8, 9 and 10. The logical value found

in at least two of the three samples is taken as the bit value. All bits are shifted into the

Transmitter Shift register as they are sampled. Sampling of an incoming character is

shown in Figure 43.

Figure 43. Sampling Received Data

When the stop bit enters the receiver, the majority of the three samples must be one to

accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FE) flag in

the UART Status Register (USR) is set. Before reading the UDR register, the user

should always check the FE bit to detect framing errors.

Whether or not a valid stop bit is detected at the end of a character reception cycle, the

data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically

separate registers, one for transmitted data and one for received data. When UDR is

read, the Receive Data register is accessed and when UDR is written, the Transmit

Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Con-

trol Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit Shift

register when data is transferred to UDR.

If, after having received a character, the UDR register has not been read since the last

receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted

into the shift register could not be transferred to UDR and has been lost. The OR bit is

buffered and is updated when the valid data byte in UDR is read. Thus, the user should

always check the OR bit after reading the UDR register in order to detect any overruns if

the baud rate is high or CPU load is high.

When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This

means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART

Receiver will be connected to PD0, which is forced to be an input pin regardless of the

setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the

PORTD0 bit can still be used to control the pull-up resistor on the pin.

When the CHR9 bit in the UCR register is set, transmitted and received characters are

9 bits long, plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in

UCR register. This bit must be set to the wanted value before a transmission is initiated

by writing to the UDR register. The ninth data bit received is the RXB8 bit in the UCR

register.

61

1041H–11/01

UART Control

UART I/O Data Register – UDR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$0C ($2C)

Read/Write

Initial Value

LSB

R/W

0

UDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UDR register is actually two physically separate registers sharing the same I/O

address. When writing to the register, the UART Transmit Data register is written. When

reading from UDR, the UART Receive Data register is read.

UART Status Register – USR

Bit

7

RXC

R

6

5

UDRE

R

4

FE

R

3

OR

R

2

–

1

–

0

–

$0B ($2B)

Read/Write

Initial Value

TXC

R/W

0

USR

R

0

R

0

R

0

1

0

The USR register is a read-only register providing information on the UART status.

• Bit 7 – RXC: UART Receive Complete

This bit is set (one) when a received character is transferred from the Receiver Shift reg-

ister to UDR. The bit is set regardless of any detected framing errors. When the RXCIE

bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is

set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used,

the UART Receive Complete Interrupt routine must read UDR in order to clear RXC,

otherwise a new interrupt will occur once the interrupt routine terminates.

• Bit 6 – TXC: UART Transmit Complete

This bit is set (one) when the entire character (including the stop bit) in the Transmit

Shift register has been shifted out and no new data has been written to UDR. This flag is

especially useful in half-duplex communications interfaces, where a transmitting appli-

cation must enter receive mode and free the communications bus immediately after

completing the transmission.

When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete

interrupt to be executed. TXC is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical

“1” to the bit.

• Bit 5 – UDRE: UART Data Register Empty

This bit is set (one) when a character written to UDR is transferred to the Transmit Shift

register. Setting of this bit indicates that the transmitter is ready to receive a new charac-

ter for transmission.

When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be exe-

cuted as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven

data transmission is used, the UART Data Register Empty Interrupt routine must write

UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou-

tine terminates.

UDRE is set (one) during reset to indicate that the transmitter is ready.

• Bit 4 – FE: Framing Error

This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-

ing character is zero.

62

AT90S/LS8535

1041H–11/01

AT90S/LS8535

The FE bit is cleared when the stop bit of received data is one.

• Bit 3 – OR: OverRun

This bit is set if an Overrun condition is detected, i.e., when a character already present

in the UDR register is not read before the next character has been shifted into the

Receiver Shift register. The OR bit is buffered, which means that it will be set once the

valid data still in UDR is read.

The OR bit is cleared (zero) when data is received and transferred to UDR.

• Bits 2..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and will always read as zero.

UART Control Register – UCR

Bit

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

CHR9

R/W

0

1

RXB8

R

0

TXB8

W

$0A ($2A)

Read/Write

Initial Value

UCR

1

0

• Bit 7 – RXCIE: RX Complete Interrupt Enable

When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com-

plete Interrupt routine to be executed provided that global interrupts are enabled.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Com-

plete Interrupt routine to be executed provided that global interrupts are enabled.

• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data

Register Empty Interrupt routine to be executed provided that global interrupts are

enabled.

• Bit 4 – RXEN: Receiver Enable

This bit enables the UART receiver when set (one). When the receiver is disabled, the

RXC, OR and FE status flags cannot become set. If these flags are set, turning off

RXEN does not cause them to be cleared.

• Bit 3 – TXEN: Transmitter Enable

This bit enables the UART transmitter when set (one). When disabling the transmitter

while transmitting a character, the transmitter is not disabled before the character in the

shift register plus any following character in UDR has been completely transmitted.

• Bit 2 – CHR9: 9 Bit Characters

When this bit is set (one), transmitted and received characters are 9 bits long, plus start

and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR,

respectively. The ninth data bit can be used as an extra stop bit or a parity bit.

• Bit 1 – RXB8: Receive Data Bit 8

When CHR9 is set (one), RXB8 is the ninth data bit of the received character.

• Bit 0 – TXB8: Transmit Data Bit 8

When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.

63

1041H–11/01

Baud Rate Generator

The baud rate generator is a frequency divider which generates baud rates according to

the following equation:

f_CK

BAUD = -------------------------------------

16(UBRR + 1)

•

BAUD = Baud rate

f_CK= Crystal clock frequency

UBRR = Contents of the UART Baud Rate register, UBRR (0 - 255)

For standard crystal frequencies, the most commonly used baud rates can be generated

by using the UBRR settings in Table 24. UBRR values that yield an actual baud rate dif-

fering less than 2% from the target baud rate are boldface in the table. However, using

baud rates that have more than 1% error is not recommended. High error ratings give

less noise resistance.

Table 24. UBRR Settings at Various Crystal Frequencies (Examples)

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

0.2

%Error

0.0

1 MHz

1.8432 MHz

2 MHz

2.4576 MHz

UBRR=

25

47

23

11

7

51

63

31

15

10

7

4800

12

6

0.2

0.0

25

12

8

0.2

0.0

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

22.9 UBRR=

84.3 UBRR=

9600

0.0

0.2

0.0

3

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

22.9 UBRR=

7.8 UBRR=

3.1

14400

19200

28800

38400

57600

76800

115200

0.0

2

6

5

0.0

1

3

4

6.3

3

0.0

1

2

0.0

3

0.0

0

1

2

12.5

0.0

1

0.0

0

1

33.3 UBRR=

1

0

UBRR=

0

25.0

0

0.0

Baud Rate

2400

%Error

0.0

%Error

0.0

3.2768 MHz

3.6864 MHz

4 MHz

4.608 MHz

UBRR=

84

42

20

13

10

6

0.4

0.8

1.6

95

47

23

15

11

7

103

51

25

16

12

8

0.2

119

59

29

19

14

9

4800

0.0

9600

0.0

2.1 UBRR=

14400

19200

28800

38400

57600

76800

115200

0.0

3.1 UBRR=

UBRR=

0.0

0.2

0.0

UBRR=

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

1.6

0.0

4

6.3 UBRR=

12.5 UBRR=

6

7

6.7

5

0.0

3

2

0.0

4

0.0

2

3

6.7

0.0

1

2

20.0

1

0.0

Baud Rate

2400

%Error

0.2

%Error

0.0

%Error

-

7.3728 MHz

8 MHz

9.216 MHz

11.059 MHz

UBRR=

UBRR= 287

191

95

47

31

23

15

11

7

0.0

207

103

51

34

25

16

12

8

239

119

59

39

29

19

14

9

UBRR=

4800

0.2

0.0

143

71

47

35

23

17

11

8

0.0

9600

0.2

0.0

14400

19200

28800

38400

57600

76800

115200

0.8

0.0

0.2

0.0

2.1 UBRR=

0.0

UBRR=

0.2

0.0

3.7 UBRR=

7.5 UBRR=

7.8 UBRR=

0.0

6

7

6.7 UBRR=

5

3

UBRR=

3

4

0.0

5

Note:

Maximum baud rate to each frequency.

64

AT90S/LS8535

1041H–11/01

AT90S/LS8535

UART Baud Rate Register –

UBRR

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

$09 ($29)

Read/Write

Initial Value

LSB

R/W

0

UBRR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate

according to the equation on the previous page.

65

1041H–11/01

Analog Comparator

The Analog Comparator compares the input values on the positive input PB2 (AIN0) and

negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher

than the voltage on the negative input PB3 (AIN1), the Analog Comparator Output

(ACO) is set (one). The comparator’s output can be set to trigger the Timer/Counter1

Input Capture function. In addition, the comparator can trigger a separate interrupt,

exclusive to the Analog Comparator. The user can select Interrupt triggering on compar-

ator output rise, fall or toggle. A block diagram of the comparator and its surrounding

logic is shown in Figure 44.

Figure 44. Analog Comparator Block Diagram

Analog Comparator Control

and Status Register – ACSR

Bit

7

6

–

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

$08 ($28)

Read/Write

Initial Value

ACD

R/W

0

ACSR

R

0

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set (one), the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. When changing the ACD bit,

the Analog Comparator interrupt must be disabled by clearing the ACIE bit in ACSR.

Otherwise an interrupt can occur when the bit is changed.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8535 and will always read as zero.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined

by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit

is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logical “1” to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-

log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

66

AT90S/LS8535

1041H–11/01

AT90S/LS8535

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

cleared (zero), no connection between the Analog Comparator and the Input Capture

function is given. To make the comparator trigger the Timer/Counter1 Input Capture

interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).

• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events trigger the Analog Comparator interrupt.

The different settings are shown in Table 25.

Table 25. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

Note:

When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis-

abled by clearing its interrupt enable bit in the ACSR register. Otherwise an interrupt can

occur when the bits are changed.

Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write

a “1” back into ACI if it is read as set, thus clearing the flag.

67

1041H–11/01

Analog-to-Digital

Converter

Feature list

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

•

2 LSB Absolute Accuracy

• 65 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• 8 Multiplexed Input Channels

• Rail-to-Rail Input Range

• Free Running or Single Conversion Mode

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The AT90S8535 features a 10-bit successive approximation ADC. The ADC is con-

nected to an 8-channel Analog Multiplexer that allows each pin of Port A to be used as

an input for the ADC. The ADC contains a Sample and Hold Amplifier that ensures that

the input voltage to the ADC is held at a constant level during conversion. A block dia-

gram of the ADC is shown in Figure 45.

The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must

be connected to GND and the voltage on AV_CCmust not differ more than 0.3V from

V_CC. See “ADC Noise Canceling Techniques” on page 74 on how to connect these pins.

An external reference voltage must be applied to the AREF pin. This voltage must be in

the range 2V - AV_CC

.

Figure 45. Analog-to-Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL & STATUS

REGISTER (ADCSR)

ADC DATA REGISTER

(ADCH/ADCL)

AREF

PRESCALER

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

10-BIT DAC

CONVERSION LOGIC

8-

CHANNEL

MUX

-

+

SAMPLE & HOLD

COMPARATOR

68

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive

approximation. The minimum value represents AGND and the maximum value repre-

sents the voltage on the AREF pin minus one LSB. The analog input channel is selected

by writing to the MUX bits in ADMUX. Any of the eight ADC input pins ADC7..0 can be

selected as single-ended inputs to the ADC.

The ADC can operate in two modes – Single Conversion and Free Running. In Single

Conversion Mode, each conversion will have to be initiated by the user. In Free Running

Mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR

bit in ADCSR selects between the two available modes.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Input channel

selections will not go into effect until ADEN is set. The ADC does not consume power

when ADEN is cleared, so it is recommended to switch off the ADC before entering

power-saving sleep modes.

A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be set to zero by

hardware when the conversion is completed. If a different data channel is selected while

a conversion is in progress, the ADC will finish the current conversion before performing

the channel change.

The ADC generates a 10-bit result, which is presented in the ADC data register, ADCH

and ADCL. When reading data, ADCL must be read first, then ADCH, to ensure that the

content of the data register belongs to the same conversion. Once ADCL is read, ADC

access to data register is blocked. This means that if ADCL has been read and a con-

version completes before ADCH is read, neither register is updated and the result from

the conversion is lost. Then ADCH is read, ADC access to the ADCH and ADCL register

is re-enabled.

The ADC has its own interrupt that can be triggered when a conversion completes.

When ADC access to the data registers is prohibited between reading of ADCH and

ADCL, the interrupt will trigger even if the result is lost.

Prescaling

Figure 46. ADC Prescaler

Reset

ADEN

CK

7-BIT ADC PRESCALER

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

The successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to achieve maximum resolution. If a resolution of lower than 10 bits is

required, the input clock frequency to the ADC can be higher than 200 kHz to achieve a

69

1041H–11/01

higher sampling rate. See “ADC Characteristics” on page 75 for more details. The ADC

module contains a prescaler, which divides the system clock to an acceptable ADC

clock frequency.

The ADPS2..0 bits in ADCSR are used to generate a proper ADC clock input frequency

from any CPU frequency above 100 kHz. The prescaler starts counting from the

moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler

keeps running for as long as the ADEN bit is set and is continuously reset when ADEN

is low.

When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at

the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs

more clock cycles for initialization and to minimize offset errors. Extended conversions

take 25 ADC clock cycles and occur as the first conversion after the ADC is switched on

(ADEN in ADCSR is set).

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal

conversion and 13.5 ADC clock cycles after the start of an extended conversion. When

a conversion is complete, the result is written to the ADC data registers and ADIF is set.

In Single Conversion Mode, ADSC is cleared simultaneously. The software may then

set ADSC again and a new conversion will be initiated on the first rising ADC clock

edge. In Free Running Mode, a new conversion will be started immediately after the

conversion completes, while ADSC remains high. Using Free Running Mode and an

ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum res-

olution, 65 µs, equivalent to 15 kSPS. For a summary of conversion times, see Table

26.

Figure 47. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)

Conversion

Cycle number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC clock

ADEN

ADSC

ADIF

Sign and MSB of result

LSB of result

ADCH

ADCL

MUX and REFS

update

Conversion

complete

MUX and REFS

update

Sample & hold

70

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 48. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle number

ADC clock

ADSC

ADIF

ADCH

Sign and MSB of result

LSB of result

ADCL

Sample & hold

Conversion

complete

MUX and REFS

update

MUX and REFS

update

Figure 49. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle number

ADC clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of result

LSB of result

Sample & hold

MUX and REFS

update

Conversion

complete

Table 26. ADC Conversion Time

Sample and Hold (Cycles

from Start of Conversion)

Conversion

Time (Cycles)

Conversion

Time (µs)

Condition

Extended Conversion

Normal Conversion

14

25

26

125 - 500

130 - 520

ADC Noise Canceler

Function

The ADC features a noise canceler that enables conversion during Idle Mode to reduce

noise induced from the CPU core. To make use of this feature, the following procedure

should be used:

1. Make sure that the ADC is enabled and is not busy converting. Single Conver-

sion Mode must be selected and the ADC conversion complete interrupt must be

enabled.

ADEN = 1

ADSC = 0

ADFR = 0

ADIE = 1

71

1041H–11/01

2. Enter Idle Mode. The ADC will start a conversion once the CPU has been halted.

3. If no other interrupts occur before the ADC conversion completes, the ADC inter-

rupt will wake up the MCU and execute the ADC Conversion Complete Interrupt

routine.

ADC Multiplexer Select

Register – ADMUX

Bit

7

–

6

–

5

–

4

–

3

–

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

$07 ($27)

Read/Write

Initial Value

ADMUX

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S8535 and always read as zero.

• Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2-0

The value of these three bits selects which analog input ADC7..0 is connected to the

ADC. See Table 27 for details.

If these bits are changed during a conversion, the change will not go into effect until this

conversion is complete (ADIF in ADCSR is set).

Table 27. Input Channel Selections

MUX2.0

000

Single-ended Input

ADC0

001

ADC1

010

ADC2

011

ADC3

100

ADC4

101

ADC5

110

ADC6

111

ADC7

ADC Control and Status

Register – ADCSR

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADFR

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

$06 ($26)

Read/Write

Initial Value

ADCSR

• Bit 7 – ADEN: ADC Enable

Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is

turned off. Turning the ADC off while a conversion is in progress will terminate this

conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion Mode, a logical “1” must be written to this bit to start each conver-

sion. In Free Running Mode, a logical “1” must be written to this bit to start the first

conversion. The first time ADSC has been written after the ADC has been enabled or if

ADSC is written at the same time as the ADC is enabled, an extended conversion will

precede the initiated conversion. This extended conversion performs initialization of the

ADC.

72

AT90S/LS8535

1041H–11/01

AT90S/LS8535

ADSC will read as one as long as a conversion is in progress. When the conversion is

complete, it returns to zero. When a extended conversion precedes a real conversion,

ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no

effect.

• Bit 5 – ADFR: ADC Free Running Select

When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the

ADC samples and updates the data registers continuously. Clearing this bit (zero) will

terminate Free Running Mode.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set (one) when an ADC conversion completes and the data registers are

updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-

bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-

ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the

flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be dis-

abled. This also applies if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-

plete interrupt is activated.

• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input

clock to the ADC.

Table 28. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

ADC Data Register – ADCL

AND ADCH

Bit

15

14

13

12

11

10

9

8

$05 ($25)

$04 ($24)

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-

quently, it is essential that both registers are read and that ADCL is read before ADCH.

73

1041H–11/01

• ADC9..0: ADC Conversion result

These bits represent the result from the conversion. $000 represents analog ground and

$3FF represents the selected reference voltage minus one LSB.

Scanning Multiple

Channels

Since change of analog channel always is delayed until a conversion is finished, the

Free Running Mode can be used to scan multiple channels without interrupting the con-

verter. Typically, the ADC Conversion Complete interrupt will be used to perform the

channel shift. However, the user should take the following fact into consideration: The

interrupt triggers once the result is ready to be read. In Free Running Mode, the next

conversion will start immediately when the interrupt triggers. If ADMUX is changed after

the interrupt triggers, the next conversion has already started and the old setting is

used.

ADC Noise Canceling

Techniques

Digital circuitry inside and outside the AT90S8535 generates EMI that might affect the

accuracy of analog measurements. If conversion accuracy is critical, the noise level can

be reduced by applying the following techniques:

1. The analog part of the AT90S8535 and all analog components in the application

should have a separate analog ground plane on the PCB. This ground plane is

connected to the digital ground plane via a single point on the PCB.

2. Keep analog signal paths as short as possible. Make sure analog tracks run over

the analog ground plane and keep them well away from high-speed switching

digital tracks.

3. The AV_CCpin on the AT90S8535 should be connected to the digital V_CCsupply

voltage via an LC network as shown in Figure 50.

4. Use the ADC noise canceler function to reduce induced noise from the CPU.

5. If some Port A pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

Figure 50. ADC Power Connections

1

44

43

42

41

40

PA4 (ADC4)

39

38

37

36

35

34

33

32

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

AGND

AVCC

PC0

74

AT90S/LS8535

1041H–11/01

AT90S/LS8535

ADC Characteristics

T_A= -40°C to 85°C

Symbol

Parameter

Condition

Min

Typ

Max

Units

Resolution

10

Bits

VREF = 4V

ADC clock = 200 kHz

Absolute accuracy

1

4

2

LSB

VREF = 4V

ADC clock = 1 MHz

VREF = 4V

ADC clock = 2 MHz

16

Integral Non-linearity

Differential Non-linearity

Zero Error (Offset)

V_REF> 2V

0.5

1

LSB

µs

V_REF> 2V

Conversion Time

65

260

200

Clock Frequency

50

kHz

V

AV_CC

V_REF

R_REF

V_IN

Analog Supply Voltage

Reference Voltage

V_CC- 0.3⁽¹⁾

V_CC+ 0.3⁽²⁾

2

6

AV_CC

V

Reference Input Resistance

Input Voltage

10

13

kΩ

V

AGND

AREF

R_AIN

Analog Input Resistance

100

MΩ

Notes: 1. Minimum for AV_CCis 2.7V.

2. Maximum for AV_CCis 6.0V.

75

1041H–11/01

I/O Ports

All AVR ports have true read-modify-write functionality when used as general digital I/O

ports. This means that the direction of one port pin can be changed without unintention-

ally changing the direction of any other pin with the SBI and CBI instructions. The same

applies for changing drive value (if configured as output) or enabling/disabling of pull-up

resistors (if configured as input).

Port A

Port A is an 8-bit bi-directional I/O port.

Three I/O memory address locations are allocated for Port A, one each for the Data

Register – PORTA, $1B($3B), Data Direction Register – DDRA, $1A($3A) and the Port

A Input Pins – PINA, $19($39). The Port A Input Pins address is read-only, while the

Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port A output buffers can

sink 20 mA and thus drive LED displays directly. When pins PA0 to PA7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

Port A has an alternate function as analog inputs for the ADC. If some Port A pins are

configured as outputs, it is essential that these do not switch when a conversion is in

progress. This might corrupt the result of the conversion.

During Power-down mode, the Schmitt trigger of the digital input is disconnected. This

allows analog signals that are close to V_CC/2 to be present during power-down without

causing excessive power consumption.

Port A Data Register – PORTA

Bit

7

PORTA7

R/W

0

6

PORTA6

R/W

0

5

PORTA5

R/W

0

4

PORTA4

R/W

0

3

PORTA3

R/W

0

2

PORTA2

R/W

0

1

PORTA1

R/W

0

PORTA0

R/W

0

PORTA

DDRA

PINA

$1B ($3B)

Read/Write

Initial Value

Port A Data Direction Register

– DDRA

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

$1A ($3A)

Read/Write

Initial Value

Port A Input Pins Address –

PINA

Bit

7

PINA7

R

6

PINA6

R

5

PINA5

R

4

PINA4

R

3

PINA3

R

2

PINA2

R

1

PINA1

R

0

PINA0

R

$19 ($39)

Read/Write

Initial Value

N/A

The Port A Input Pins address (PINA) is not a register; this address enables access to

the physical value on each Port A pin. When reading PORTA, the Port A Data Latch is

read and when reading PINA, the logical values present on the pins are read.

76

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Port A as General Digital I/O

All eight pins in Port A have equal functionality when used as digital I/O pins.

PAn, general I/O pin: The DDAn bit in the DDRA register selects the direction of this pin.

If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn

is configured as an input pin. If PORTAn is set (one) when the pin is configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTAn has to be cleared (zero) or the pin has to be configured as an output pin.The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Table 29. DDAn Effects on Port A Pins

DDAn

PORTAn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PAn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6…0, pin number.

Port A Schematics

Note that all port pins are synchronized. The synchronization latch is, however, not

shown in the figure.

Figure 51. Port A Schematic Diagrams (Pins PA0 - PA7)

RD

MOS

PULL-

UP

RESET

Q

D

DDAn

C

WD

RESET

Q

D

PAn

PORTAn

C

RL

WP

RP

PWRDN

ADCn

TO ADC MUX

WP: WRITE PORTA

WD: WRITE DDRA

RL: READ PORTA LATCH

RP: READ PORTA PIN

RD: READ DDRA

n:

0-7

77

1041H–11/01

Port B

Port B is an 8-bit bi-directional I/O port.

Three I/O memory address locations are allocated for the Port B, one each for the Data

Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B

Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can

sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

The Port B pins with alternate functions are shown in Table 30.

Table 30. Port B Pin Alternate Functions

Port Pin

PB0

Alternate Functions

T0 (Timer/Counter0 External Counter Input)

T1 (Timer/Counter1 External Counter Input)

AIN0 (Analog Comparator Positive Input)

AIN1 (Analog Comparator Negative Input)

SS (SPI Slave Select Input)

PB1

PB2

PB3

PB4

PB5

MOSI (SPI Bus Master Output/Slave Input)

MISO (SPI Bus Master Input/Slave Output)

SCK (SPI Bus Serial Clock)

PB6

PB7

When the pins are used for the alternate function, the DDRB and PORTB registers have

to be set according to the alternate function description.

Port B Data Register – PORTB

Bit

7

PORTB7

R/W

0

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

DDRB

PINB

$18 ($38)

Read/Write

Initial Value

Port B Data Direction Register

– DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

$17 ($37)

Read/Write

Initial Value

Port B Input Pins Address –

PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16 ($36)

Read/Write

Initial Value

N/A

The Port B Input Pins address (PINB) is not a register and this address enables access

to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch

is read and when reading PINB, the logical values present on the pins are read.

78

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Port B As General Digital I/O

All eight pins in Port B have equal functionality when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin.

If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn

is configured as an input pin. If PORTBn is set (one) when the pin is configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Table 31. DDBn Effects on Port B Pins

DDBn

PORTBn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PBn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6…0, pin number.

Alternate Functions of Port B The alternate pin configuration is as follows:

• SCK – Port B, Bit 7

SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is

enabled as a slave, this pin is configured as an input regardless of the setting of DDB7.

When the SPI is enabled as a master, the data direction of this pin is controlled by

DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB7 bit. See the description of the SPI port for further details.

• MISO – Port B, Bit 6

MISO: Master data input, slave data output pin for SPI channel. When the SPI is

enabled as a master, this pin is configured as an input regardless of the setting of

DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by

DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB6 bit. See the description of the SPI port for further details.

• MOSI – Port B, Bit 5

MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is

enabled as a slave, this pin is configured as an input regardless of the setting of DDB5.

When the SPI is enabled as a master, the data direction of this pin is controlled by

DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB5 bit. See the description of the SPI port for further details.

• SS – Port B, Bit 4

SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as

an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin

is driven low. When the SPI is enabled as a master, the data direction of this pin is con-

trolled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled

by the PORTB4 bit. See the description of the SPI port for further details.

• AIN1 – Port B, Bit 3

AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is

cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared

[zero]), this pin also serves as the negative input of the on-chip Analog Comparator.

During Power-down mode, the Schmitt trigger of the digital input is disconnected. This

79

1041H–11/01

allows analog signals that are close to V_CC/2 to be present during power-down without

causing excessive power consumption.

• AIN0 – Port B, Bit 2

AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared

[zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]),

this pin also serves as the positive input of the on-chip Analog Comparator. During

Power-down mode, the Schmitt trigger of the digital input is disconnected. This allows

analog signals that are close to V_CC/2 to be present during power-down without causing

excessive power consumption.

• T1 – Port B, Bit 1

T1, Timer/Counter1 counter source. See the timer description for further details.

• T0 – Port B, Bit 0

T0: Timer/Counter0 counter source. See the timer description for further details.

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 52. Port B Schematic Diagram (Pins PB0 and PB1)

2

80

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 53. Port B Schematic Diagram (Pins PB2 and PB3)

RD

MOS

PULL-

UP

RESET

Q

D

DDBn

C

WD

RESET

Q

D

PBn

PORTBn

C

RL

WP

PWRDN

RP

AINm

TO COMPARATOR

WP: WRITE PORTB

WD: WRITE DDRB

RL: READ PORTB LATCH

RP: READ PORTB PIN

RD: READ DDRB

n:

m:

2, 3

0, 1

Figure 54. Port B Schematic Diagram (Pin PB4)

RD

MOS

PULL-

UP

RESET

Q

D

DDB4

C

WD

RESET

Q

D

PB4

PORTB4

C

RL

WP

RP

MSTR

SPE

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

MSTR: SPI MASTER ENABLE

SPE: SPI ENABLE

SPI SS

81

1041H–11/01

Figure 55. Port B Schematic Diagram (Pin PB5)

RD

MOS

PULL-

UP

RESET

R

DDB5

C

Q

D

WD

RESET

R

Q

D

PB5

PORTB5

C

RL

RP

WP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

SPI ENABLE

MASTER SELECT

WP:

WD:

RL:

RP:

RD:

SPE:

MSTR

SPE

SPI MASTER

OUT

SPI SLAVE

IN

Figure 56. Port B Schematic Diagram (Pin PB6)

RD

MOS

PULL-

UP

RESET

R

DDB6

C

Q

D

WD

RESET

R

Q

D

PB6

PORTB6

C

RL

RP

WP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

SPI ENABLE

MASTER SELECT

WP:

WD:

RL:

RP:

RD:

SPE:

MSTR

SPE

SPI SLAVE

OUT

SPI MASTER

IN

82

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 57. Port B Schematic Diagram (Pin PB7)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDB7

C

WD

RESET

R

Q

D

PB7

PORTB7

C

RL

RP

WP

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

SPI ENABLE

MASTER SELECT

WP:

WD:

RL:

RP:

RD:

SPE:

MSTR

SPE

SPI CLOCK

OUT

SPI CLOCK

IN

83

1041H–11/01

Port C

Port C is an 8-bit bi-directional I/O port.

Three I/O memory address locations are allocated for the Port C, one each for the Data

Register – PORTC, $15($35), Data Direction Register – DDRC, $14($34) and the Port C

Input Pins – PINC, $13($33). The Port C Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port C output buffers can

sink 20 mA and thus drive LED displays directly. When pins PC0 to PC7 are used as

inputs and are externally pulled low, they will source current if the internal pull-up resis-

tors are activated.

Port C Data Register – PORTC

Bit

7

PORTC7

R/W

0

6

PORTC6

R/W

0

5

PORTC5

R/W

0

4

PORTC4

R/W

0

3

PORTC3

R/W

0

2

PORTC2

R/W

0

1

PORTC1

R/W

0

PORTC0

R/W

0

PORTC

$15 ($35)

Read/Write

Initial Value

Port C Data Direction Register

– DDRC

Bit

7

DDC7

R/W

0

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

$14 ($34)

Read/Write

Initial Value

DDRC

Port C Input Pins Address –

PINC

Bit

7

PINC7

R

6

PINC6

R

5

PINC5

R

4

PINC4

R

3

PINC3

R

2

PINC2

R

1

PINC1

R

0

PINC0

R

$13 ($33)

Read/Write

Initial Value

PINC

N/A

The Port C Input Pins address (PINC) is not a register; this address enables access to

the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is

read and when reading PINC, the logical values present on the pins are read.

Port C As General Digital I/O

All eight pins in Port C have equal functionality when used as digital I/O pins.

PCn, general I/O pin: The DDCn bit in the DDRC register selects the direction of this pin.

If DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn

is configured as an input pin. If PORTCn is set (one) when the pin is configured as an

input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off,

PORTCn has to be cleared (zero) or the pin has to be configured as an output pin.The

port pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Table 32. DDCn Effects on Port C Pins

DDCn

PORTCn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PCn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7…0, pin number

84

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Alternate Functions of Port C When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of

Timer/Counter2, pins PC6 and PC7 are disconnected from the port. In this mode, a

crystal oscillator is connected to the pins and the pins cannot be used as I/O pins.

Port C Schematics

Note that all port pins are synchronized. The synchronization latch is, however, not

shown in the figure.

Figure 58. Port C Schematic Diagram (Pins PC0 - PC5)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDCn

C

WD

RESET

R

Q

D

PCn

PORTCn

C

RL

RP

WP

WP: WRITE PORTC

WD: WRITE DDRC

RL: READ PORTC LATCH

RP: READ PORTC PIN

RD: READ DDRC

n:

0-5

Figure 59. Port C Schematic Diagram (Pins PC6)

RD

MOS

PULL-

UP

RESET

R

DDC6

C

Q

D

WD

RESET

R

Q

D

PC6

PORTC6

C

RL

WP

RP

WP: WRITE PORTC

WD: WRITE DDRC

AS2

RL: READ PORTC LATCH

RP: READ PORTC PIN

RD: READ DDRC

T/C2 OSC

AMP INPUT

AS2: ASYNCH SELECT T/C2

85

1041H–11/01

Figure 60. Port C Schematic Diagram (Pins PC7)

Port D

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for Port D, one each for the Data

Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D

Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data

Register and the Data Direction Register are read/write.

The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally

pulled low will source current if the pull-up resistors are activated. Some Port D pins

have alternate functions as shown in Table 33.

Table 33. Port D Pin Alternate Functions

Port Pin

PD0

Alternate Function

RXD (UART Input line)

PD1

TXD (UART Output line)

PD2

INT0 (External interrupt 0 input)

PD3

INT1 (External interrupt 1 input)

PD4

OC1B (Timer/Counter1 output compareB match output)

OC1A (Timer/Counter1 output compareA match output)

ICP (Timer/Counter1 input capture pin)

OC2 (Timer/Counter2 output compare match output)

PD5

PD6

PD7

86

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Port D Data Register – PORTD

Bit

7

PORTD7

R/W

0

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

$12 ($32)

Read/Write

Initial Value

Port D Data Direction Register

– DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

$11 ($31)

Read/Write

Initial Value

Port D Input Pins Address –

PIND

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

$10 ($30)

Read/Write

Initial Value

N/A

The Port D Input Pins address (PIND) is not a register; this address enables access to

the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is

read and when reading PIND, the logical values present on the pins are read.

Port D As General Digital I/O

PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.

If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn

is configured as an input pin. If PDn is set (one) when configured as an input pin, the

MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be

cleared (zero) or the pin has to be configured as an output pin.The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Table 34. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PDn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 7,6…0, pin number.

Alternate Functions of Port D • OC2 – Port D, Bit 7

OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an

external output for the Timer/Counter2 output compare. The pin has to be configured as

an output (DDD7 set [one]) to serve this function. See the timer description on how to

enable this function. The OC2 pin is also the output pin for the PWM mode timer

function.

• ICP – Port D, Bit 6

ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for

Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to

serve this function. See the timer description on how to enable this function.

87

1041H–11/01

• OC1A – Port D, Bit 5

OC1A, Output compare matchA output: The PD5 pin can serve as an external output for

the Timer/Counter1 output compareA. The pin has to be configured as an output (DDD5

set [one]) to serve this function. See the timer description on how to enable this function.

The OC1A pin is also the output pin for the PWM mode timer function.

• OC1B – Port D, Bit 4

OC1B, Output compare matchB output: The PD4 pin can serve as an external output for

the Timer/Counter1 output compareB. The pin has to be configured as an output (DDD4

set [one]) to serve this function. See the timer description on how to enable this function.

The OC1B pin is also the output pin for the PWM mode timer function.

• INT1 – Port D, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source

to the MCU. See the interrupt description for further details and how to enable the

source.

• INT0 – Port D, Bit 2

INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source

to the MCU. See the interrupt description for further details and how to enable the

source.

• TXD – Port D, Bit 1

Transmit Data (data output pin for the UART). When the UART Transmitter is enabled,

this pin is configured as an output, regardless of the value of DDD1.

• RXD – Port D, Bit 0

Receive Data (data input pin for the UART). When the UART Receiver is enabled, this

pin is configured as an input, regardless of the value of DDD0. When the UART forces

this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.

88

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1041H–11/01

AT90S/LS8535

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 61. Port D Schematic Diagram (Pin PD0)

RD

MOS

PULL-

UP

RESET

Q

D

DDD0

C

WD

RESET

Q

D

PD0

PORTD0

C

RL

RP

WP

RXEN

RXD

WP: WRITE PORTD

WD: WRITE DDRD

RL:

RP:

RD:

READ PORTD LATCH

READ PORTD PIN

READ DDRD

RXD: UART RECEIVE DATA

RXEN: UART RECEIVE ENABLE

Figure 62. Port D Schematic Diagram (Pin PD1)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDD1

C

WD

RESET

R

Q

D

PD1

PORTD1

C

RL

RP

WP

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

WP:

WD:

RL:

RP:

RD:

TXEN

TXD

UART TRANSMIT DATA

UART TRANSMIT ENABLE

TXD:

TXEN:

89

1041H–11/01

Figure 63. Port D Schematic Diagram (Pins PD2 and PD3)

Figure 64. Port D Schematic Diagram (Pins PD4 and PD5)

90

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 65. Port D Schematic Diagram (Pin PD6)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDD6

C

WD

RESET

R

Q

D

PD6

PORTD6

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

0

1

NOISE CANCELER

ICNC1

EDGE SELECT

ICES1

ICF1

RL:

RP:

READ PORTD LATCH

READ PORTD PIN

RD: READ DDRD

ACIC: COMPARATOR IC ENABLE

ACO: COMPARATOR OUTPUT

ACIC

ACO

Figure 66. Port D Schematic Diagram (Pin PD7)

91

1041H–11/01

Memory

Programming

Program and Data

Memory Lock Bits

The AT90S8535 MCU provides two Lock bits that can be left unprogrammed (“1”) or can

be programmed (“0”) to obtain the additional features listed in Table 35. The Lock bits

can only be erased with the Chip Erase command.

Table 35. Lock Bit Protection Modes

Memory Lock Bits

Mode

LB1

1

LB2 Protection Type

1

2

3

1

0

No memory lock features enabled.

0

Further programming of the Flash and EEPROM is disabled.⁽¹⁾

0

Same as mode 2 and verify is also disabled.

Note:

1. In Parallel Mode, further programming of the Fuse bits is also disabled. Program the

Fuse bits before programming the Lock bits.

Fuse Bits

The AT90S8535 has two Fuse bits, SPIEN and FSTRT.

•

When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading

is enabled. Default value is programmed (“0”). The SPIEN Fuse is not accessible in

Serial Programming Mode.

•

When the FSTRT Fuse is programmed (“0”), the short start-up time is selected.

Default value is unprogrammed (“1”).

The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes

All Atmel microcontrollers have a three-byte signature code that identifies the device.

This code can be read in both Serial and Parallel modes. The three bytes reside in a

separate address space.

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $93 (indicates 8K bytes Flash memory)

3. $002: $03 (indicates AT90S8535 device when signature byte $001 is $93)

Note:

1. When both Lock bits are programmed (lock mode 3), the signature bytes cannot be

read in Serial Mode. Reading the signature bytes will return: $00, $01 and $02.

Programming the Flash

and EEPROM

Atmel’s AT90S8535 offers 8K bytes of in-system reprogrammable Flash program mem-

ory and 512 bytes of EEPROM data memory.

The AT90S8535 is shipped with the On-chip Flash program and EEPROM data memory

arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This

device supports a high-voltage (12V) Parallel Programming Mode and a low-voltage

Serial Programming Mode. The +12V is used for programming enable only and no cur-

rent of significance is drawn by this pin. The Serial Programming Mode provides a

convenient way to download program and data into the AT90S8535 inside the user’s

system.

The program and data memory arrays on the AT90S8535 are programmed byte-by-byte

in either programming mode. For the EEPROM, an auto-erase cycle is provided within

the self-timed write instruction in the Serial Programming Mode.

During programming, the supply voltage must be in accordance with Table 36.

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AT90S/LS8535

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AT90S/LS8535

Table 36. Supply Voltage during Programming

Part

Serial Programming

4.0 - 6.0V

Parallel Programming

4.5 - 5.5V

AT90S8535

AT90LS8535

2.7 - 6.0V

4.5 - 5.5V

Parallel Programming

This section describes how to parallel program and verify Flash program memory,

EEPROM data memory, Lock bits and Fuse bits in the AT90S8535.

Signal Names

In this section, some pins of the AT90S8535 are referenced by signal names describing

their function during parallel programming. See Figure 67 and Table 37. Pins not

described in Table 37 are referenced by pin name.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding are shown in Table 38.

When pulsing WR or OE, the command loaded determines the action executed. The

command is a byte where the different bits are assigned functions as shown in Table 39.

Figure 67. Parallel Programming

AT90S8535

+5V

VCC

PD1

RDY/BSY

OE

PD2

PB7 - PB0

DATA

WR

BS

PD3

PD4

XA0

PD5

XA1

PD6

+12 V

RESET

XTAL1

GND

93

1041H–11/01

Table 37. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

0: Device is busy programming, 1: Device is ready

for new command

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (Active low)

Write Pulse (Active low)

WR

Byte Select (“0” selects low byte, “1” selects high

byte)

BS

PD4

I

XA0

XA1

PD5

PD6

I

XTAL Action Bit 0

XTAL Action Bit 1

DATA

PB7 - 0

I/O Bi-directional Data Bus (Output when OE is low)

Table 38. XA1 and XA0 Coding

XA1

XA0 Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (high or low address byte determined by BS)

Load Data (High or low data byte for Flash determined by BS)

Load Command

No Action, Idle

Table 39. Command Byte Bit Coding

Command Byte

1000 0000

Command Executed

Chip Erase

0100 0000

Write Fuse Bits

Write Lock Bits

Write Flash

0010 0000

0001 0000

0001 0001

Write EEPROM

Read Signature Bytes

Read Lock and Fuse Bits

Read Flash

0000 1000

0000 0100

0000 0010

0000 0011

Read EEPROM

Enter Programming Mode

The following algorithm puts the device in Parallel Programming Mode:

1. Apply supply voltage according to Table 36, between V_CCand GND.

2. Set the RESET and BS pin to “0” and wait at least 100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has

been applied to RESET, will cause the device to fail entering programming mode.

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Chip Erase

The Chip Erase command will erase the Flash and EEPROM memories and the Lock

bits. The Lock bits are not reset until the Flash and EEPROM have been completely

erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash

or EEPROM is reprogrammed.

Load Command “Chip Erase”:

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a t_{WLWH_CE}-wide negative pulse to execute Chip Erase. See Table 40

for t_{WLWH_CE}value. Chip Erase does not generate any activity on the RDY/BSY

pin.

Programming the Flash

A: Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B: Load Address High Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “1”. This selects high byte.

3. Set DATA = Address high byte ($00 - $0F).

4. Give XTAL1 a positive pulse. This loads the address high byte.

C: Load Address Low Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “0”. This selects low byte.

3. Set DATA = Address low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

D: Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data low byte.

E: Write Data Low Byte

1. Set BS to “0”. This selects low data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 68 for signal waveforms.)

F: Load Data High Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data high byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data high byte.

G: Write Data High Byte

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1041H–11/01

1. Set BS to “1”. This selects high data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 69 for signal waveforms.)

The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered:

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Address high byte needs only be loaded before programming a new 256-word page

in the Flash.

• Skip writing the data value $FF, that is, the contents of the entire Flash and EEPROM

after a Chip Erase.

These considerations also apply to EEPROM programming and Flash, EEPROM and

signature byte reading.

Figure 68. Programming the Flash Waveforms

$10

ADDR. HIGH

ADDR. LOW

DATA LOW

DATA

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

12V

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AT90S/LS8535

Figure 69. Programming the Flash Waveforms (Continued)

DATA

DATA HIGH

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

+12V

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” for details on command and address loading):

1. A: Load Command “0000 0010”.

2. B: Load Address High Byte ($00 - $0F).

3. C: Load Address Low Byte ($00 - $FF).

4. Set OE to “0” and BS to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read from DATA.

6. Set OE to “1”.

Programming the EEPROM

The programming algorithm for the EEPROM data memory is as follows (refer to “Pro-

gramming the Flash” for details on command, address and data loading):

1. A: Load Command “0001 0001”.

2. B: Load Address High Byte ($00 - $01).

3. C: Load Address Low Byte ($00 - $FF).

4. D: Load Data Low Byte ($00 - $FF).

5. E: Write Data Low Byte.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” for details on command and address loading):

1. A: Load Command “0000 0011”.

2. B: Load Address High Byte ($00 - $01).

3. C: Load Address Low Byte ($00 - $FF).

4. Set OE to “0” and BS to “0”. The EEPROM data byte can now be read at DATA.

5. Set OE to “1”.

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Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to “Programming the

Flash” for details on command and data loading):

1. A: Load Command “0100 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 5 = SPIEN Fuse bit.

Bit 0 = FSTRT Fuse bit.

Bit 7-6,4-1 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. Give WR a t_{WLWH_PFB}-wide negative pulse to execute the programming, t_{WLWH_PFB}

is found in Table 40. Programming the Fuse bits does not generate any activity

on the RDY/BSY pin.

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 95 for details on command and data loading):

1. A: Load Command “0010 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bit 7-3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. E: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on page 95 for details on command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0” and BS to “1”. The status of the Fuse and Lock bits can now be

read at DATA (“0” means programmed).

Bit 7 = Lock Bit1

Bit 6 = Lock Bit2

Bit 5 = SPIEN Fuse bit

Bit 0 = FSTRT Fuse bit

3. Set OE to “1”.

Observe that BS needs to be set to “1”.

Reading the Signature Bytes

The algorithm for reading the signature bytes is as follows (refer to “Programming the

Flash” on page 95 for details on command and address loading):

1. A: Load Command “0000 1000”.

2. C: Load Address Low Byte ($00 - $02).

Set OE to “0” and BS to “0”. The selected signature byte can now be read at DATA.

3. Set OE to “1”.

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Parallel Programming

Characteristics

Figure 70. Parallel Programming Timing

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDXt_BVWL

Data & Contol

(DATA, XA0/1, BS)

t_WLWH

WR

t_RHBX

t_WHRL

RDY/BSY

t_WLRH

t_OHDZ

OE

t_XLOL

t_OLDV

DATA

Table 40. Parallel Programming Characteristics, T_A= 25°C 10%, V_CC= 5V 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Setup before XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

250.0

µA

ns

t_DVXH

t_XHXL

t_XLDX

t_XLWL

t_BVWL

t_RHBX

t_WLWH

t_WHRL

t_WLRH

t_XLOL

67.0

ns

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

ns

BS Valid to WR Low

ns

BS Hold after RDY/BSY High

WR Pulse Width Low⁽¹⁾

ns

WR High to RDY/BSY Low⁽²⁾

WR Low to RDY/BSY High⁽²⁾

XTAL1 Low to OE Low

20.0

0.7

ns

0.5

0.9

ms

ns

67.0

t_OLDV

t_OHDZ

t_{WLWH_CE}

OE Low to DATA Valid

20.0

ns

OE High to DATA Tri-stated

WR Pulse Width Low for Chip Erase

20.0

15.0

ns

5.0

1.0

10.0

1.5

ms

WR Pulse Width Low for Programming the

Fuse Bits

t_{WLWH_PFB}

1.8

ms

Notes: 1. Use t_{WLWH_CE}for Chip Erase and t_{WLWH_PFB}for programming the Fuse bits.

2. If t_WLWHis held longer than t_WLRH, no RDY/BSY pulse will be seen.

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output), see Figure 71. After RESET is set low, the Programming

Enable instruction needs to be executed first before program/erase operations can be

executed.

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Figure 71. Serial Programming and Verify

2.7 - 6.0V

AT90S8535

GND

VCC

PB7

PB6

RESET

SCK

MISO

MOSI

PB5

CLOCK INPUT

XTAL1

GND

For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction

and there is no need to first execute the Chip Erase instruction. The Chip Erase instruc-

tion turns the content of every memory location in both the program and EEPROM

arrays into $FF.

The program and EEPROM memory arrays have separate address spaces: $0000 to

$0FFF for program memory and $0000 to $01FF for EEPROM memory.

Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock

(SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycles

High: > 2 XTAL1 clock cycles

Serial Programming

Algorithm

When writing serial data to the AT90S8535, data is clocked on the rising edge of SCK.

When reading data from the AT90S8535, data is clocked on the falling edge of SCK.

See Figure 72, Figure 73 and Table 43 for timing details.

To program and verify the AT90SS8535 in the Serial Programming Mode, the following

sequence is recommended (see 4-byte instruction formats in Table 42):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. If a crys-

tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the

XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held

low during power-up. In this case, RESET must be given a positive pulse of at least

two XTAL1 cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to the MOSI (PB5) pin.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync, the second byte ($53) will echo back when issu-

ing the third byte of the Programming Enable instruction. Whether the echo is

correct or not, all four bytes of the instruction must be transmitted. If the $53 did

not echo back, give SCK a positive pulse and issue a new Programming Enable

instruction. If the $53 is not seen within 32 attempts, there is no functional device

connected.

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4. If a Chip Erase is performed (must be done to erase the Flash), wait t_{WD_ERASE}

after the instruction, give RESET a positive pulse and start over from step 2. See

Table 44 for t_{WD_ERASE}value.

5. The Flash or EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM

memory location is first automatically erased before new data is written. Use

Data Polling to detect when the next byte in the Flash or EEPROM can be writ-

ten. If polling is not used, wait t_{WD_PROG}before transmitting the next instruction.

See Table 45 for t_{WD_PROG}value. In an erased device, no $FFs in the data file(s)

needs to be programmed.

6. Any memory location can be verified by using the Read instruction that returns

the content at the selected address at the serial output MISO (PB6) pin.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set XTAL1 to “0” (if a crystal is not used).

Set RESET to “1”.

Turn V_CCpower off.

Data Polling EEPROM

When a byte is being programmed into the EEPROM, reading the address location

being programmed will give the value P1 until the auto-erase is finished and then the

value P2. See Table 41 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read

correctly. This is used to determine when the next byte can be written. This will not work

for the values P1 and P2, so when programming these values, the user will have to wait

for at least the prescribed time t_{WD_PROG}before programming the next byte. See Table

45 for t_{WD_PROG}value. As a chip-erased device contains $FF in all locations, program-

ming of addresses that are meant to contain $FF can be skipped. This does not apply if

the EEPROM is reprogrammed without first chip-erasing the device.

Table 41. Read Back Value during EEPROM Polling

Part

P1

P2

AT90S/LS8535

$00

$FF

Data Polling Flash

When a byte is being programmed into the Flash, reading the address location being

programmed will give the value $FF. At the time the device is ready for a new byte, the

programmed value will read correctly. This is used to determine when the next byte can

be written. This will not work for the value $FF, so when programming this value, the

user will have to wait for at least t_{WD_PROG}before programming the next byte. As a chip-

erased device contains $FF in all locations, programming of addresses that are meant

to contain $FF can be skipped.

Figure 72. Serial Programming Waveforms

SERIAL DATA INPUT

PB5(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

PB6(MISO)

MSB

SERIAL CLOCK INPUT

PB7(SCK)

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f

Table 42. Serial Programming Instruction Set

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte4

Operation

1010 1100

0101 0011

100x xxxx

xxxx aaaa

xxxx xxxx

Enable serial programming

while RESET is low.

Programming Enable

1010 1100

xxxx xxxx

Chip Erase Flash and

EEPROM memory arrays.

Chip Erase

0010 H000

bbbb bbbb

oooo oooo

Read H (high or low) data o

from program memory at word

address a:b.

Read Program Memory

0100 H000

xxxx aaaa

bbbb bbbb

iiii iiii

Write H (high or low) data i to

program memory at word

address a:b.

Write Program Memory

1010 0000

1100 0000

0101 1000

xxxx xxxa

xxxx xxxx

bbbb bbbb

xxxx xxxx

oooo oooo

iiii iiii

12Sx xxxF

Read data o from EEPROM

memory at address a:b.

Read EEPROM Memory

Write EEPROM Memory

Write data i to EEPROM

memory at address a:b.

Read Lock and Fuse bits.

“0” = programmed

Read Lock and Fuse Bits

“1” = unprogrammed

1010 1100

0011 0000

1010 1100

1111 1211

xxxx xxxx

1011 111F

xxxx xxxx

xxxx xxbb

xxxx xxxx

oooo oooo

xxxx xxxx

Write Lock bits. Set bits 1,2 =

“0” to program Lock bits.

Write Lock Bits

Read signature byte o at

address b.⁽²⁾

Read Signature Byte

Write FSTRT fuse. Set bit

F = “0” to program,

“1” to unprogram.

Write FSTRT Fuse

Notes: 1. a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High Byte

o = data out

i = data in

x = don’t care

1 = Lock Bit 1

2 = Lock Bit 2

F = FSTRT Fuse

S = SPIEN Fuse

2. The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed.

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Serial Programming

Characteristics

Figure 73. Serial Programming Timing

MOSI

t_OVSH

t_SLSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 43. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 2.7 - 6.0V

(unless otherwise noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (V_CC= 2.7 - 6.0V)

Oscillator Period (V_CC= 2.7 - 4.0V)

Oscillator Frequency (V_CC= 4.0 - 6.0V)

Oscillator Period (V_CC= 4.0 - 6.0V)

SCK Pulse Width High

4.0

250.0

0

1/t_CLCL

t_CLCL

8.0

MHz

ns

125.0

2.0 t_CLCL

t_CLCL

t_SHSL

ns

t_SLSH

SCK Pulse Width Low

ns

t_OVSH

t_SHOX

t_SLIV

MOSI Setup to SCK High

MOSI Hold after SCK High

SCK Low to MISO Valid

ns

2.0 t_CLCL

10.0

ns

16.0

32.0

ns

Table 44. Minimum Wait Delay after the Chip Erase instruction

Symbol

3.2V

3.6V

4.0V

12 ms

5.0V

t_{WD_ERASE}

18 ms

14 ms

8 ms

Table 45. Minimum Wait Delay after Writing a Flash or EEPROM Location

Symbol

3.2V

3.6V

4.0V

5.0V

t_{WD_PROG}

9 ms

7 ms

6 ms

4 ms

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Electrical Characteristics

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature ................................ -40°C to +105°C

Storage Temperature .................................... -65°C to +150°C

Voltage on Any Pin except RESET

with Respect to Ground.............................-1.0V to V_CC+ 0.5V

Voltage on RESET with Respect to Ground ....-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.6V

I/O Pin Maximum Current ........................................... 40.0 mA

Maximum Current V_CC

and GND (PDIP package) ....................................... 200.0 mA

Maximum Current V_CC

and GND (TQFP, PLCC package) ............................ 400.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 6.0V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Min

-0.5

Typ

Max

Units

(1)

Input Low Voltage

Input High Voltage

0.3V_CC

V

V_IL1

XTAL

0.2 V_CC

(2)

V_IH

Except (XTAL, RESET)

0.6 V_CC

0.8 V_CC

0.9 V_CC

V_CC+ 0.5

V_IH1

V_IH2

XTAL

RESET

Output Low Voltage⁽³⁾

(Ports A, B, C, D)

Output High Voltage⁽⁴⁾

(Ports A, B, C, D)

I_OL= 20 mA, V_CC= 5V

I_OL= 10 mA, V_CC= 3V

0.6

0.5

V

V_OL

V_OH

I_IL

I_OH= -3 mA, V_CC= 5V

4.2

2.3

V

I_OH= -1.5 mA, V_CC= 3V

Input Leakage

Current I/O Pin

V_CC= 6V, Vin = 0.45V

(absolute value)

8.0

µA

Input Leakage

Current I/O Pin

V_CC= 6V, Vin = 6.0V

(absolute value)

I_IH

RRST

R_I/O

Reset Pull-up

100.0

35.0

500.0

120.0

5.0

kΩ

I/O Pin Pull-up Resistor

Active 4 MHz, V_CC= 3V

Idle 4 MHz, V_CC= 3V

mA

3.0

Power-down, V_CC= 3V

WDT enabled⁽⁵⁾

15.0

5.0

µA

I_CC

Power Supply Current

Power-down, V_CC= 3V

WDT disabled⁽⁵⁾

Power Save, V_CC= 3V

WDT disabled⁽⁵⁾

15.0

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AT90S/LS8535

DC Characteristics (Continued)

T_A= -40°C to 85°C, V_CC= 2.7V to 6.0V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

Analog Comparator Input

Offset Voltage

V_CC= 5V

V_in= V_CC/2

40.0

mV

V_ACIO

Analog Comparator Input

Leakage A

V_CC= 5V

I_ACLK

t_ACPD

-50.0

50.0

nA

ns

V_in= V_CC/2

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750.0

500.0

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).

2. “Min” means the lowest value where the pin is guaranteed to be read as high (logical “1”).

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all I_OL, for all ports, should not exceed 200 mA.

2] The sum of all I_OL, for port A0 - A7, should not exceed 100 mA.

3] The sum of all I_OL, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.

PLCC and TQFP Packages:

1] The sum of all I_OL, for all ports, should not exceed 400 mA.

2] The sum of all I_OL, for ports A0 - A7, should not exceed 100 mA.

3] The sum of all I_OL, for ports B0 - B3, should not exceed 100 mA.

4] The sum of all I_OL, for ports B4 - B7, should not exceed 100 mA.

5] The sum of all I_OL, for ports C0 - C3, should not exceed 100 mA.

6] The sum of all I_OL, for ports C4 - C7, should not exceed 100 mA.

7] The sum of all I_OL, for ports D0 - D3 and XTAL2, should not exceed 100 mA.

8] The sum of all I_OL, for ports D4 - D7, should not exceed 100 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (3 mA at V_CC= 5V, 1.5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all I_OH, for all ports, should not exceed 200 mA.

2] The sum of all I_OH, for port A0 - A7, should not exceed 100 mA.

3] The sum of all I_OH, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.

PLCC and TQFP Packages:

1] The sum of all I_OH, for all ports, should not exceed 400 mA.

2] The sum of all I_OH, for ports A0 - A7, should not exceed 100 mA.

3] The sum of all I_OH, for ports B0 - B3, should not exceed 100 mA.

4] The sum of all I_OH, for ports B4 - B7, should not exceed 100 mA.

5] The sum of all I_OH, for ports C0 - C3, should not exceed 100 mA.

6] The sum of all I_OH, for ports C4 - C7, should not exceed 100 mA.

7] The sum of all I_OH, for ports D0 - D3 and XTAL2, should not exceed 100 mA.

8] The sum of all I_OH, for ports D4 - D7, should not exceed 100 mA.

If I_OHexceeds the test condition, V_OHmay exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

5. Minimum V_CCfor power-down is 2V.

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1041H–11/01

External Clock Drive

Waveforms

Figure 74. External Clock

VIH1

VIL1

Table 46. External Clock Drive

V_CC= 2.7V to 6.0V

V_CC= 4.0V to 6.0V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Min

0

Max

Units

MHz

ns

4

8.0

250.0

100.0

125.0

50.0

t_CHCX

t_CLCX

ns

Low Time

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

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AT90S/LS8535

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

C_L•V_CC•f where C_L= load capacitance, V_CC= operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in with Watchdog Timer enabled and

Power-down mode with Watchdog Timer disabled represents the differential current

drawn by the Watchdog Timer.

Figure 75. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

40

35

30

25

20

15

10

5

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

V_cc= 3.0V

V_cc= 2.7V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

107

1041H–11/01

Figure 76. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 77. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

A

20

18

16

14

12

10

8

V_cc= 6V

V_cc= 5.5V

V_cc= 5V

V_cc= 4.5V

V_cc= 4V

V_cc= 3.6V

V_cc= 3.3V

V_cc= 3.0V

V_cc= 2.7V

6

4

2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

108

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 78. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

7

6

5

4

3

2

1

0

T_A= 85˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 79. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

90

80

70

60

50

40

30

20

10

0

T_A= 85˚C

T_A= 70˚C

T_A= 45˚C

T_A= 25˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

109

1041H–11/01

Figure 80. Power-down Supply Current vs. V_CC

POWER DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER ENABLED

140

120

100

80

T_A= 85˚C

60

40

T_A= 25˚C

20

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 81. Power Save Supply Current vs. V_CC

POWER SAVE SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

90

80

70

60

50

40

30

20

10

T_A= 85˚C

T_A= 25˚C

0

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

110

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 82. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V

cc

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Note:

Analog comparator offset voltage is measured as absolute offset.

Figure 83. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 5V

18

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Common Mode Voltage (V)

111

1041H–11/01

Figure 84. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

V_cc= 2.7V

10

8

T_A= 25˚C

6

T_A= 85˚C

4

2

0

0.5

1

1.5

2

2.5

3

Common Mode Voltage (V)

Figure 85. Analog Comparator Input Leakage Current

ANALOG COMPARATOR INPUT LEAKAGE CURRENT

V_CC= 6V

T_A= 25˚C

60

50

40

30

20

10

0

-10

0

0.5

1

1.5

2

2.5

3

3.5

V (V)

4

4.5

5

5.5

6

6.5

7

IN

112

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 86. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V

cc

1600

1400

1200

1000

800

600

400

200

0

T_A= 25˚C

T_A= 85˚C

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Note:

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 87. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 5V

120

100

80

60

40

20

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OP(V)

113

1041H–11/01

Figure 88. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_cc= 2.7V

30

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OP(V)

Figure 89. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

70

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OL(V)

114

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 90. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 5V

20

18

16

14

12

10

8

T_A= 25˚C

T_A= 85˚C

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OH(V)

Figure 91. I/O Pin Sink Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

2.5

3

V_OH(V)

115

1041H–11/01

Figure 92. I/O Pin Source Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_cc= 2.7V

25

20

15

10

5

T_A= 25˚C

T_A= 85˚C

0

0.5

1

1.5

2

V_OL(V)

Figure 93. I/O Pin Input Threshold Voltage vs. V_CC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

T_A= 25˚C

2.5

2

1.5

1

0.5

0

2.7

4.0

5.0

V_cc

116

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Figure 94. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V

cc

T_A= 25˚C

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

2.7

4.0

5.0

V_cc

117

1041H–11/01

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($20)

$02 ($22)

$01 ($21)

$00 ($20)

SREG

I

T

H

S

V

N

Z

C

page 19

page 20

SPH

-

SP9

SP1

SP8

SP0

SPL

SP7

SP6

SP5

SP4

SP3

SP2

Reserved

GIMSK

GIFR

INT1

INTF1

OCIE2

OCF2

INT0

INTF0

TOIE2

TOV2

-

page 25

page 26

page 27

TIMSK

TIFR

TICIE1

ICF1

OCIE1A

OCF1A

OCIE1B

OCF1B

TOIE1

TOV1

-

TOIE0

TOV0

Reserved

MCUCR

MCUSR

TCCR0

TCNT0

Reserved

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

-

SE

SM1

SM0

ISC11

ISC10

-

ISC01

EXTRF

CS01

ISC00

PORF

CS00

page 29

page 24

page 34

-

CS02

Timer/Counter0 (8 Bits)

COM1A1

ICNC1

COM1A0

ICES1

COM1B1

-

COM1B0

-

PWM11

CS11

PWM10

CS10

page 36

page 37

page 38

page 39

page 40

page 43

page 44

page 46

page 49

-

CTC1

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Output Compare Register A High Byte

Timer/Counter1 – Output Compare Register A Low Byte

Timer/Counter1 – Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

TCCR2

TCNT2

OCR2

-

PWM2

Timer/Counter2 (8 Bits)

Timer/Counter2 Output Compare Register

COM21

COM20

CTC2

CS22

CS21

CS20

ASSR

-

AS2

TCN2UB

WDP2

OCR2UB

WDP1

TCR2UB

WDP0

WDTCR

Reserved

EEARH

EEARL

EEDR

WDTOE

WDE

EEAR8

EEAR0

page 51

page 76

page 78

page 84

page 87

page 58

page 57

page 62

page 63

page 65

page 66

page 72

page 73

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEPROM Data Register

EECR

-

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA

DDRA

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

PINA

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PORTB5

DDB5

PINA4

PORTB4

DDB4

PINA3

PINA2

PINA1

PINA0

PORTB

DDRB

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

PINB

PINB7

PORTC7

DDC7

PINB6

PORTC6

DDC6

PINB5

PORTC5

DDC5

PINB4

PORTC4

DDC4

PINB3

PINB2

PINB1

PINB0

PORTC

DDRC

PORTC3

DDC3

PORTC2

DDC2

PORTC1

DDC1

PORTC0

DDC0

PINC

PINC7

PORTD7

DDD7

PINC6

PORTD6

DDD6

PINC5

PORTD5

DDD5

PINC4

PORTD4

DDD4

PINC3

PORTD3

DDD3

PINC2

PINC1

PORTD1

DDD1

PINC0

PORTD0

DDD0

PORTD

DDRD

PORTD2

DDD2

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

SPDR

SPI Data Register

SPIF

SPSR

WCOL

SPE

-

SPCR

SPIE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

UDR

UART I/O Data Register

USR

RXC

TXC

UDRE

FE

OR

-

UCR

RXCIE

TXCIE

UDRIE

RXEN

TXEN

CHR9

RXB8

TXB8

UBRR

UART Baud Rate Register

ACSR

ACD

-

ACO

ACI

ACIE

ACIC

MUX2

ADPS2

-

ACIS1

MUX1

ADPS1

ADC9

ADC1

ACIS0

MUX0

ADPS0

ADC8

ADC0

ADMUX

ADCSR

ADCH

-

ADEN

-

ADSC

-

ADFR

-

ADIF

-

ADIE

-

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

Reserved

118

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

119

1041H–11/01

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ←=Rd • Rr

Rd ← Rd •=K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ←=Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC=← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC=← PC + 2 or 3

Rd − Rr

None

Z,N,V,C,H

None

1/2/3

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ←=PC + k + 1

if (SREG(s) = 0) then PC ←=PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BRID

k

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move between Registers

Load Immediate

Rd ← Rr

None

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, -X

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

LD

120

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

LD

Rd, Y

Load Indirect

Rd ← (Y)

None

2

3

1

2

LD

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z + 1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X)=← Rr

ST

X+, Rr

-X, Rr

Y, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect

(X)=← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

(k) ← Rr

R0 ← (Z)

Rd, P

P, Rr

Rr

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)

Z,C,N,V

Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I=← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

121

1041H–11/01

Ordering Information

Power Supply

Speed (MHz)

Ordering Code

Package

Operation Range

2.7 - 6.0V

4

AT90LS8535-4AC

AT90LS8535-4JC

AT90LS8535-4PC

AT90LS8535-4MC

44A

Commercial

44J

(0°C to 70°C)

40P6

44M1

AT90LS8535-4AI

AT90LS8535-4JI

AT90LS8535-4PI

AT90LS8535-4MI

44A

Industrial

44J

(-40°C to 85°C)

40P6

44M1

4.0 - 6.0V

8

AT90S8535-8AC

AT90S8535-8JC

AT90S8535-8PC

AT90LS8535-8MC

44A

Commercial

44J

(0°C to 70°C)

40P6

44M1

AT90S8535-8AI

AT90S8535-8JI

AT90S8535-8PI

AT90LS8535-8MI

44A

Industrial

44J

(-40°C to 85°C)

40P6

44M1

Package Type

44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

44-lead, Plastic J-leaded Chip Carrier (PLCC)

44J

40P6

44M1

40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)

122

AT90S/LS8535

1041H–11/01

AT90S/LS8535

Packaging Information

44A

44-lead, Thin (1.0mm) Plastic Quad Flat Package

(TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch.

Dimension in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

12.25(0.482)

11.75(0.462)

SQ

PIN 1 ID

PIN 1

0.45(0.018)

0.30(0.012)

0.80(0.0315) BSC

10.10(0.394)

9.90(0.386)

SQ

1.20(0.047) MAX

0.20(0.008)

0.09(0.004)

0˚~7˚

0.75(0.030) 0.15(0.006)

0.45(0.018) 0.05(0.002)

*Controlling dimension: millimetter

REV. A 04/11/2001

123

1041H–11/01

44J

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Milimeters and (Inches)*

JEDEC STANDARD MS-018 AC

1.14(0.045) X 45˚

PIN NO. 1

IDENTIFY

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

16.00(0.630)

15.00(0.590)

0.533(0.021)

SQ

16.70(0.656)

SQ

16.50(0.650)

0.813(0.032)

0.660(0.026)

17.70(0.695)

17.40(0.685)

0.330(0.013)

SQ

1.27(0.050) TYP

0.50(0.020)MIN

2.11(0.083)

12.70(0.500) REF SQ

1.57(0.062)

3.05(0.120)

2.29(0.090)

4.57(0.180)

4.19(0.165)

0.51(0.020)MAX 45˚ MAX (3X)

*Controlling dimensions: Inches

REV. A 04/11/2001

124

AT90S/LS8535

1041H–11/01

AT90S/LS8535

40P6

40-lead, Plastic Dual Inline

Parkage (PDIP), 0.600" wide

Demension in Millimeters and (Inches)*

JEDEC STANDARD MS-011 AC

52.71(2.075)

51.94(2.045)

1

13.97(0.550)

13.46(0.530)

48.26(1.900) REF

4.83(0.190)MAX

SEATING

PLANE

0.38(0.015)MIN

3.56(0.140)

3.05(0.120)

0.56(0.022)

0.38(0.015)

1.65(0.065)

1.27(0.050)

2.54(0.100)BSC

15.88(0.625)

15.24(0.600)

0º ~ 15º REF

0.38(0.015)

0.20(0.008)

17.78(0.700)MAX

*Controlling dimension: Inches

REV. A 04/11/2001

125

1041H–11/01

44M1

D

Marked pin#1 identifier

E

A1

A3

TOP VIEW

A

L

SIDE VIEW

PIN #1 CORNER

D2

COMMON DIMENSIONS

(*Unit of Measure = mm)

NOTE

SYMBOL

MAX

1.00

0.05

NOM

MIN

0.80

0.00

A

0.90

0.02

0.25 REF

0.23

A1

A3

b

E2

0.18

0.30

D

D2

E

7.00 BSC

4.70

2.25

0.35

5.25

0.75

7.00 BSC

4.70

E2

e

0.50 BSC

0.55

L

e

b

BOTTOM VIEW

NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1

07/23/01

TITLE

DRAWING NO. REV

2325 Orchard Parkway

San Jose, CA 95131

44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm

Micro lead frame package (MLF)

R

44M1

A

126

AT90S/LS8535

1041H–11/01

Atmel Headquarters

Atmel Product Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel Grenoble

Atmel SarL

Avenue de Rochepleine

BP 123

Route des Arsenaux 41

Casa Postale 80

CH-1705 Fribourg

Switzerland

38521 Saint-Egreve Cedex, France

TEL (33) 4-7658-3000

FAX (33) 4-7658-3480

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Atmel Heilbronn

Theresienstrasse 2

POB 3535

Asia

Atmel Asia, Ltd.

Room 1219

D-74025 Heilbronn, Germany

TEL (49) 71 31 67 25 94

FAX (49) 71 31 67 24 23

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Atmel Nantes

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 0 2 40 18 18 18

FAX (33) 0 2 40 18 19 60

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Smart Card ICs

Scottish Enterprise Technology Park

East Kilbride, Scotland G75 0QR

TEL (44) 1355-357-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®and AVR^®are the registered trademarks of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

1041H–11/01/0M


型号：	AT90LS8535-4JC
厂家：	ATMEL
描述：	8-bit Microcontroller with 8K Bytes In-System Programmable Flash 8位微控制器具有8K字节的系统内可编程闪存闪存微控制器
文件：	总127页 (文件大小：2362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT90LS8535-4JC [ATMEL]

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