AT78C1502_技术文档

Features

• Servo Processing Unit (SPU), Using Dedicated 16-bit Instruction Cycle AVR^®RISC

Cores (3), Giving 120 MIPS Maximum Processing Power with 40 MHz SYSCLK

• SPU Includes 17 x 17 Single-clock Cycle MAC

• On-chip Debugger Monitor for Program Development (OCDM)

• 8K Words Program RAM

• 4K Bytes Data RAM

• On-chip Clock Frequency Synthesizer with Output Clock Buffers for AT78C1501

Controller

• On-chip S/H and WCS Timing State Machine (TSM) for Conversion of Focus, Tracking

and SUM Signals

• 10-bit 1.2 µsec ADC with six-channel MUX

• Synchronized ADC Conversions with SPU Interrupt Service Routine

• Three Fast 10-bit 500 nsec (rise time) DACs for Servo Loops and Adjustments

• Three 8-bit DACs for Offset Adjustment and Spin Loop

• Bandgap ADC and DAC Midpoint Reference Outputs

• SPU Implemented Spindle Speed Control

DVD/CD Servo

AT78C1502

• Spindle Interface Logic and Hardware Support for Both CAV and CLV Spindle Control

Modes

• Eight General Purpose I/O Pins

• SPU Servo Control of Focus, Fine Track, Coarse Track and Tray Load Motors

• High-speed Track Counter for Accurate High-speed Track Counts (1.4 MHz when used

with AT78C1503 Read Channel)

• Lower Power Operations with 3.3V Core and 5V Tolerant I/Os

• 8-bit Data and 14-bit Address Controller/Microprocessor Interface

• 3-pin Universal Serial Port Interface to Program Read Channel and Power Devices

• Power Management

• On-chip UART to Access OCDM Unit

Description

The Atmel AT78C1502 high-performance servo controller fully integrates all of the

control and demodulation functions for DVD and CD, optical/mechanical systems.

Packaged in 128-lead TQFP and fabricated in 0.35 micron CMOS, the device oper-

ates on a 3.3V logic/analog supply and provides 5V tolerance for digital I/O. An AVR-

based Servo Processing Unit (SPU) embedded in the device provides programmable

control of spindle speed, coarse and fine tracking, focus, sled, draw motor and tilt. The

three parallel programmable AVR microcontrollers in the SPU are the heart of the sys-

tem, offering a range of servo sample rates. With only a 40 MHz system clock, 120

MIPS of processing power is provided. Real-time notch filters can also be calculated.

Fast 10-bit DACs provide real-time control of servo loops and other system adjust-

ments. A universal serial port and many general purpose I/Os are provided.

AVR0 is the master AVR of the three microcontrolloers, communicating with AVR1,

AVR2 and the ARMTDMI in the AT78C1501 interface controller and to the AT78C1503

read channel. An On-Chip Debugger Monitor (OCDM) is offered to enable program-

mers to easily observe theeffect of changes to code on each AVR.

System-level evaluation boards are available with development code in both C and

native code for basic operation of all servos. Simple changes to the code allow any

mechadeck to be interfaced to the AT78C1502.

Rev. 2050A–DVD–07/02

1

Figure 1. DVD System Block Diagram

DRAM Flash

AT78C1502

Servo

Power

Drivers

Sled

Control

System

AT78C1501

ATAPI I/F

Controller

DBM

ECC

SRAM

ARM7TDMI

Spindle

Focus

Laser

AT78C1503

Read

Channel

AT78C1504

Laser Power

Controller

T08XX

Laser Amp

AT78C1507

Read

Channel Adj.

AT78C1505

Pre-amp

2

AT78C1502

2050A–DVD–07/02

AT78C1502

Figure 2. Pin-out

128

103

102

1

DGND

D0

DGND

N/C

D1

CAP

D2

D3

DVDD

D4

GPP7

GPP6

GPP5

GPP4

GPP3

GPP2

GPP1

GPP0

DVDD

SPCLK

BEMF

TXD

D5

D6

D7

DGND

WRB

RDB

CSB

CINT

CINTAQK

TESTMODE

DVDD

OCDM

TM4

RXD

SCLK

SDATA

SDEN2

SDEN1

SDEN0

DGND

AGND

FDAC

AT78C1502

128-lead TQFP

TM3

TM2

TM1

TM0

DGND

MRST

WG

IDF

JTRIG

LHP

FDACREF

FINDAC

FINDACREF

AVDD

CRSDAC

CRSDACREF

DAC1

DVDD

TOK

DAC0

BCA

N/C

TZC

MIRR

FOK

AVDD

2VBG

VBG

HD1,2

DGND

N/C

AGND

38

65

39

64

3

2050A–DVD–07/02

External Pin

Definition

P = Power or ground, B = Bidirectional, I = Digital Input, O = Digital Output.

AI = Analog Input, AO = Analog Output.

Table 1. External Pin Definition

Pin #

1

Symbol

DGND

D0

Type

Description

P

B

P

B

P

I

Digital Ground

2

Data Bus

3

D1

Data Bus

4

D2

Data Bus

5

D3

Data Bus

6

DVDD

D4

Digital VDD

7

Data Bus

8

D5

Data Bus

9

D6

Data Bus

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

D7

Data Bus

DGND

WRB

Digital Ground

Chip Write Select

RDB

I

Chip Read Select

CSB

I

Chip Select Input

CINT

I

Interrupt Input from Controller

Controller Interrupt Acknowledge

Test Mode Select Input – Active-low

Digital VDD

CINTACK

TMODE

DVDD

OCDM_ENAB

TM4/MUX4

TM3/MUX3

TM2/MUX2

TM1/MUX1

TM0/MUX0

DGND

MRST

WG

O

I

P

I

On-chip Debug/Monitor Mode

Test Mode Select

I

Test Mode Select Input/MUX Output

Digital Ground

I

P

I

Master Reset Input

I

Write Gate Input from Controller

I/D Field Input from Controller

Jump Trigger Input from Controller

Laser High Power Input from Controller

Digital Power

IDF

I

JTRIG

LHP

I

DVDD

TOK

P

I

Track OK Input from Read Channel

Burst Cutting Area (Defect Flag Input)

BCA

I

4

AT78C1502

2050A–DVD–07/02

AT78C1502

Table 1. External Pin Definition (Continued)

Pin #

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

Symbol

TZC

Type

I

Description

Track Zero Crossing from Read Channel

Mirror Input from Read Channel

Focus OK Signal from Read Channel

Header 1, 2 Input from Read Channel

Digital Ground

MIRR

FOK

I

HD1,2

DGND

HD3,4

CNTRST

SINT

I

P

Digital Ground

I

Header 3, 4 Input from Read Channel

TSM Counter Reset Signal

Servo Interrupt Output to Controller

Servo Fault Output to Controller

ADC Strobe Output from TSM

Analog VDD

I

O

P

SF

ADCSTR

AVDD

MUX_OUT

AIN6

AO

AI

P

Analog MUX Output

Analog Input to MUX

AIN5

Analog Input to MUX

MTRK

MTRKFB

AGND

LPS

MUXed Track Track/Hold Input

MUXed Track Filter Input

Analog Ground

AI

P

Lens Position Sensor Track/Hold Input

Lens Position Sensor Filter Input

Focus Error Signal Track/Hold Input

Focus Error Signal Filter Input

Analog VDD

LPS

FCS

FCSF

AVDD

SUM

AI

Slow Sum Track/Hold Input

Slow Sum Input Filter

SUMF

RDSZ

RDSZF

N/C

Read Size Input

Read Size Input Filter

No Connect

N/C

No Connect

ADCREF

AGND

N/C

AI

P

Reference I/P for ADC

Analog GND

P

Analog GND

No Connect

VBG

AO

P

Bandgap Output Voltage

2*Bandgap Output Voltage

Analog VDD

2VBG

AVDD

5

2050A–DVD–07/02

Table 1. External Pin Definition (Continued)

Pin #

70

Symbol

N/C

Type

Description

No Connect

71

DAC0

AO

AI

P

8-bit Offset DAC Output

10-bit Coarse Tracking DAC

Coarse DAC Ref Input

Analog VDD

72

DAC1

73

CRSDAC

CRSDACREF

AVDD

74

75

76

FINDAC

FINDACREF

FDAC

AO

AI

AO

AI

P

10-bit Fine Tracking DAC

Fine DAC Ref Input

77

78

10-bit Focus DAC

79

FDACREF

AGND

DGND

SDEN0

SDEN1

SDEN2

SDATA

SCLK

Focus DAC Ref Input

Analog GND

80

81

P

Digital GND

82

O

B

Serial Data Enable #0

Serial Data Enable #1

Serial Data Enable #2

Serial Data

83

84

85

86

O

I

Serial CLK

87

RXD

UART Receive Data Input

UART Transmit Data Output

Back EMF Zero Crossing Input

Spin Pseudo Register Output

Digital VDD

88

TXD

O

I

89

BEMF

SPCLK

DVDD

GPP0

90

O

P

91

92

B

General Purpose I/O Port Bit

External Event Capture

No Connect

93

GPP1

B

94

GPP2

B

95

GPP3

B

96

GPP4

B

97

GPP5

B

98

GPP6

B

99

GPP7

B

100

101

102

103

104

105

CAP

I

N/C

DGND

FSIS

P

I

Digital Ground

Frequency Synthesizer Iset

Frequency Synthesizer Filter

FSFILT

I

6

AT78C1502

2050A–DVD–07/02

AT78C1502

Table 1. External Pin Definition (Continued)

Pin #

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

Symbol

N/C

DVDD

CLK1

CLK2

XOUT

XIN

Type

Description

No Connect

P

O

I

Digital VDD

Clock 1 Output

Crystal Out Connection

Crystal Input/Clock Input

Digital Ground

DGND

A0

P

I

Address Bus Input

Digital VDD

A1

I

A2

I

A3

I

A4

I

DVDD

A5

P

I

Address Bus Input

Digital GND

A6

I

A7

I

A8

I

A9

I

A10

A11

A12

A13

DGND

I

P

7

2050A–DVD–07/02

Figure 3. Block Diagram

SDENA2

SDENA1

SDENA0

SDATA

Program Space

and

Data Space

Dual-Port

RAM

A (13:0)

D (7:0)

WRB

Serial Interface

Port

UART

Controller

Interface

(CIF)

(SIP)

SCLK

RDB

CSB

General

Purpose

Port

GPP (7:0)

CINT

CINTACK

SINT

Servo

Processing

Unit (SPU)

Interrupt

Control

Logic

(GPP)

(ICL)

CRSDAC

FINDAC

FDAC

DAC1

DAC0

DAC

Output

Block

SF

ADCREF

MUXOUT

(DOB)

CNTRST

CAP

MTRK

FCS

FOK

IDF

WG

JTRIG

LHP

BCA

HD1,2

HD3,4

Track

Hold &

Filter

Timing State

Machine (TSM)

MUX

&

ADC

(MAD)

SUM

RDSZ

LPS

Servo

Input

Block

(SIB)

(THF)

AIN4

AIN5

Track

Counter

(TRCNT)

TOK

TZC

MIRR

Clock Osc

Frequency

Synthesizer

(FQS)

and

Distribution

(COD)

Band Gap

Ref

Spindle

Control

Logic

SPCLK

BEMF

(SCL)

8

AT78C1502

2050A–DVD–07/02

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Other terms and product names may be the trademarks of others.

Printed on recycled paper.

2050A–DVD–07/02


型号：	AT78C1502
厂家：	ATMEL
描述：	DVD/CD Servo DVD / CD伺服 CD DVD
文件：	总9页 (文件大小：78K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT78C1502 [ATMEL]

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