AT697E-2E-MQ [ATMEL]
Rad-Hard 32 bit SPARC V8 Processor; 抗辐射32位SPARC V8处理器
| 型号： | AT697E-2E-MQ |
| 厂家： | 
ATMEL |
| 描述： | Rad-Hard 32 bit SPARC V8 Processor |
| 文件： | 总7页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
Smart Card Interface
– Compliance with Standards
• ISO/IEC 7816-1, 2, 3 and 4
• EMV 2000
• CB
• Mondex®, Proton, ZKA, Other: Contact Gemplus®
– Supported Smart Cards
• Number of Smart Cards Supported: 1
• Asynchronous Cards: T=0 and T=1
• Synchronous/Memory Cards Using a Command Interpreter
• EMV or Non EMV Cards
GemCore Serial
Lite PRO
•
•
Electrical Interface
• Transmission Speed: 9.6 Kbps to 115 Kbps
• Card Power Supply: 1.8V/3V/5V
• ESD Protection On Card Pins: 4 KV - Human Body Model
• Card Presence or Insertion Detection
• Short Circuit Current Limitation
Host Interface
AT83C21GC
Summary
– Physical Layer
• Serial Asynchronous Link
• Programmable Transmission Speed From 1,200 bps to 115,200 bps
• Format: 8 bits, No Parity, 1 Stop Bit
• Adjustable Signal Voltage
– Protocol
• Gemplus Block Protocol (GBP)
• GBP Interface Library Kit Source Code
Chip Power Supply
•
•
– Voltage: VCC- 2.85V to 5.4V
– Consumption: 8 mA Typical, 150 mA Max - Smart Card Powered
– Power Down Mode
• 100 µA Max Power Down Current
• Power-down/Power-up by Host Command
Additional Features
– Operating Temperature Range: 0°C to +70°C (-40°C to +85°C)
– Package: SS0P24, QFN32
– LED Management: The LED is On When the Card is Powered On
Description
AT83C21GC is designed to simplify the integration of smart card interfaces in elec-
tronic devices.
It manages the electrical interface and communication with ISO 7816 –1/2/3/4 com-
patible smart cards and memory cards.
Figure 1. Basic Architecture of a Smart Card Reader
Host
Processor
AT83C21GC
Smart Card
Smart Card
Connector
4247DS–SCR–03/07
This is a summary Document. A complete document is
available on the Gemplus Web site. www.gemplus.com
The connection with the host processor is achieved via a serial asynchronous link; the rate can
be selected from a range from 1200 to 115,200 bps.
The software inside the GemCore chip handles a communication protocol with the host system
called the Gemplus Block Protocol (GBP).
A complete set of documentation is available on the Gemplus web site:
http://www.gemplus.com.
A GBP Interface Library Kit can be provided, upon request. It consists of the source code of the
GBP communication layer between the host and GemCore. It is written in the C language. See
the Gemplus developers’ site at www.gemplus.com. Enquiries can also be posted to
cardreader@atmel.com.
For general information on the device, please refer to the AT83C5121 datasheet available on
the Atmel web site, www.atmel.com.
2
AT83C21GC
4247DS–SCR–03/07
AT83C21GC
Ordering
information
Part Number
Temperature Range
Industrial
Package
SSOP24
SSOP24
SSOP24
SSOP24
QFN32
Packing
Stick
AT83C21GCxxx-ICSIL
AT83C21GCxxx-ICRIL
AT83C21GCxxx-ICSUL
AT83C21GCxxx-ICRUL
AT83C21GCxxx-PUTUL
AT83C21GCxxx-PURUL
Industrial
Tape & Reel
Stick
Industrial & Green
Industrial & Green
Industrial & Green
Industrial & Green
Stick
Tray
QFN32
Tape & Reel
xxx : Firmware version
3
4247DS–SCR–03/07
Pin Description Figure 2. 24-pin SSOP Pinout
CVSS
24
1
2
VCC
LI
23
22
E
VCC
VCC
C
VCC
3
4
D
P1.5/CRST
P1.4/CCLK
21
VSS
P3.0/RxD
20
19
18
17
5
6
P1.3/CC4
P3.1/TxD
SSOP24
P3.3/INT1/OE
P3.4/T0
7
8
P1.2/CPRES
P1.1/CC8
P1.0/CIO
RST
P3.2/INT0
9
16
15
14
13
P3.5/CIO1/T1
10
11
XTAL2
P3.6/CCLK1/LED0
P3.7/CRST1/LED1
XTAL1 12
Figure 3. 32-pin QFN Pinout
32 31 30 29 28 27 26 25
CVcc
Vss
1
2
3
4
24
23
22
21
P1.5/CRST
P1.4/CCLK
P1.3/CC4
P1.2/CPRES
P1.1/CC8
P1.0/CIO
RST
Vss
P3.0/RxD
P3.1/TxD
QFN32
20 P3.3/INT1/OE
5
6
7
8
P3.4/T0
19
P3.2/INT0
18
17 P3.5/CIO1/T1
9 10 11 12 13 14 15 16
Table 1. Port Signal Description
Internal
Power
Signal
Port
Name
Supply
ESD
Type
Description
Smart Card Interface Function
P1.0
CIO
CVCC
4 kV
I/O
Card I/O – Pull-up medium is lower than 20KΩ
Smart Card Interface Function
P1.1
P1.2
CC8
CVCC
4 kV
4 kV
I/O
I
Card contact 8 – Pull-up medium must be less than 20KΩ
Smart Card Interface Function
CPRES
VCC
Card presence
4
AT83C21GC
4247DS–SCR–03/07
AT83C21GC
Table 1. Port Signal Description (Continued)
Internal
Power
Signal
Port
Name
Supply
ESD
Type
Description
Smart Card Interface Function
P1.3
CC4
CVCC
4 kV
I/O
Card contact 4 – Pull-up medium must be less than 20KΩ
Smart Card Interface Function
P1.4
P1.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
CCLK
CRST
RxD
CVCC
CVCC
EVCC
EVCC
DVCC
EVCC
EVCC
DVCC
4 kV
4 kV
O
O
Card clock
Smart Card Interface Function
Card reset – Pull-up medium must be less than 20KΩ
UART Function
I
Receive data input
UART Function
TxD
O
Transmit data output.
Input/Output Function
INT0
INT1
I/O
I/O
I/O
I/O
P3.2 is a bi-directional I/O port with internal pull-ups.
Input/Output Function
P3.3 is a bi-directional I/O port with internal pull-ups.
Input/Output Function
P3.4 is a bi-directional I/O port with internal pull-ups.
Alternate Card Function
CIO1
Card I/O: Pull-up medium must be less than 20K
LED function
These pins can be directly connected to the cathode of the standard LED without
external current limiting resistors. The typical current of each output can be
programmed by software to 2, 4 or 10 mA (LEDCON register).
P3.6
CCLK1
CRST1
DVCC
O
Input/Output Function
P3.7
RST
DVCC
VCC
I/O
I/O
P3.7 is a bi-directional I/O port with internal pull-ups.
Reset Input
Holding this pin low for 64 oscillator periods while the oscillatoris running resets the
device. The Port pins are driven to their reset conditions when a voltage lower than VIL
is applied, whether or not the oscillator is running. This pin has an internal pull-up
resistor which allows the device to be reset by connecting a capacitor between this pin
and VSS. Asserting RST when the chip is in Idle mode or Power-down mode returns
the chip to normal operation. The output is active for at least 12 oscillator periods when
an internal reset occurs.
XTAL1
XTAL2
VCC
I
Input to the on-chip Inverting Oscillator Amplifier
To use the internal oscillator, a crystal/resonator circuit is connected
to this pin. If an external oscillator is used, its output is connected to this pin.
VCC
O
Output of the on-chip Inverting Oscillator Amplifier
To use the internal oscillator, a crystal/resonator circuit is connected
to this pin. If an external oscillator is used, XTAL2 may be left unconnected.
VCC
PWR Supply Voltage
VCC is used to power the internal voltage regulators and internal I/O’s.
LI
PWR DC/DC Input
LI must be tied to VCC through an external coil (typically 4, 7 µH) and provide the
current for the pump charge of the DC/DC converter.
5
4247DS–SCR–03/07
Table 1. Port Signal Description (Continued)
Internal
Power
Signal
Port
Name
Supply
ESD
Type
Description
CVCC
PWR Card Supply Voltage
CVCC is the programmable voltage output for the Card interface. It must be connected
to an external decoupling capacitor.
DVCC
PWR Digital Supply Voltage
DVCC is used to supply the digital core and internal I/Os. It is internally connected to the
output of a 3V regulator and must be connected to an external decoupling capacitor.
EVCC
VCC
PWR Extra Supply Voltage
EVCC is used to supply the level shifters of UART interface I/O pins. It must be
connected to an external decoupling capacitor. This reference voltage is generated
internally (automatically or not), or it can be connected to an external voltage
reference.
CVSS
VSS
GND
GND
DC/DC Ground
CVSS is used to sink high shunt currents from the external coil.
Ground
6
AT83C21GC
4247DS–SCR–03/07
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4247DS–SCR–03/07
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