AT697E-KG-SV [ATMEL]
Rad-Hard 32 bit SPARC V8 Processor; 抗辐射32位SPARC V8处理器
| 型号： | AT697E-KG-SV |
| 厂家： | 
ATMEL |
| 描述： | Rad-Hard 32 bit SPARC V8 Processor |
| 文件： | 总154页 (文件大小：2656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• SPARC V8 High Performance Low-power 32-bit Architecture
– LEON2-FT 1.0.13 compliant
– 8 Register Windows
• Advanced Architecture:
– On-chip Amba Bus
– 5 Stage Pipeline
– 16 kbyte Multi-sets Data Cache
– 32 kbyte Multi-sets Instruction Cache
• On-chip Peripherals:
– Memory Interface
Rad-Hard 32 bit
SPARC V8
Processor
PROM Controller
SRAM Controller
SDRAM Controller
– Timers
Two 24-bit Timers
Watchdog Timer
– Two 8-bit UARTs
– Interrupt Controller with 4 External Programmable Inputs
– 32 Parallel I/O Interface
AT697E
– 33MHz PCI Interface Compliant with 2.2 PCI Specification
• Integrated 32/64-bit IEEE 754 Floating-point Unit
• Fault Tolerance by Design
– Full Triple Modular Redundancy (TMR)
– EDAC Protection
– Parity Protection
• Debug and Test Facilities
– Debug Support Unit (DSU) for Trace and Debug
– IEEE 1149.1 JTAG Interface
– Four Hardware Watchpoints
• Speed Optimized Code RAM Interface
8, 16 and 40-bit boot-PROM (Flash) Interface Possibilities
• Operating range
– Voltages
3.3V +/- 0.30V for I/O
1.8V +/- 0.15V for Core
– Temperature
-55°C to 125°C
• Clock: 0MHz up to 100MHz
• Power consumption: 1W at 100MHz
• Performance:
– 86MIPS (Dhrystone 2.1)
– 23MFLOPS (Whetstone)
• Radiation Performance
– Total dose radiation capability (parametric & functional): 60Krads (Si)
– SEU error rate better than 1 E-5 error/device/day
– No Single Event Latchup below a LET threshold of 70 MeV.cm²/mg
• Package MCGA 349
• Mass: 9g
• Development Kit Including
– AT697 Evaluation Board
– AT697 Sample
– GRMON Development Tool
Rev. 4226G–AERO–05/09
1
Description
The AT697 is a highly integrated, high-performance 32-bit RISC embedded processor
based on the SPARC V8 architecture. The implementation is based on the European
Space Agency (ESA) LEON2 fault tolerant model. By executing powerful instructions in
a single clock cycle, the AT697 achieves throughputs approaching 1MIPS per MHz,
allowing the system designer to optimize power consumption versus processing speed.
The AT697 is designed to be used as a building block in computers for on-board embed-
ded real-time applications. It brings up-to-date functionality and performance for space
application.
The AT697 only requires memory and application specific peripherals to be added to
form a complete on-board computer.
The AT697 contains an on-chip Integer Unit (IU), a Floating Point Unit (FPU), separate
instruction and data caches, hardware multiplier and divider, interrupt controller, debug
support unit with trace buffer, two 24-bit timers, Parallel and Serial interfaces, a Watch-
dog, a PCI Interface and a flexible Memory Controller. The design is highly testable with
the support of a Debug Support Unit (DSU) and a boundary scan through JTAG
interface.
An Idle mode holds the processor pipeline and allows Timer/Counter, Serial ports and
Interrupt system to continue functioning.
The processor is manufactured using the Atmel 0.18 µm CMOS process. It has been
especially designed for space, by implementing on-chip concurrent transient and per-
manent error detection and correction.
The AT697E is the first version of the AT697 processor. A second version of the AT697
processor, the AT697F, is under development.
The AT697F will have improved radiation capabilities (up to 100Krad) and will correct all
the bugs described in the AT697E errata sheet. The AT697F will be pinout compatible
with the AT697E.
2
AT697E
4226G–AERO–05/09
AT697
Figure 1. AT697 Block Diagram
AT697
I -Cache
Integer Unit
(SPARC V8)
BRDY*
READ
WRITE*
A[27:0]
D[31:0]
...
D-Cache
Flash
Memory
Controller
FPU
SRAM
SDRAM
TDI
JTAG
TDO
...
AMBA
Controller
AHB
RxD
DSU
TxD
...
AMBA
bridge
RESET*
Reset
PCI/AMBA
bridge
PCI
CLK
BYPASS
...
Clock
Generator
APB
interrupt
Interrupt
Controller
config
PIO
RxD
TxD
RS232
Watchdog
Timers
WDOG*
IOs
3
4226G–AERO–05/09
Pin Configuration
MCGA349 package
Table 1. AT697E MCGA349 pinout
A
B
C
D
E
PIO[6]
N.C.
F
G
RAMS[1]
RAMS[2]
RAMOE[3]
RAMS[4]
RAMOE[1]
VSS33
PIO[7]
PIO[8]
CB[3]
1
2
VDD18
VDD18
VSS18
PIO[9]
PIO[11]
VCC33
N.C.
VSS18
PIO[0]
VCC33
N.C.
PIO[1]
PIO[4]
N.C.
VSS18
VDD18
VDD18
N.C.
3
VDD18
VSS18
N.C.
PIO[2]
PIO[5]
N.C.
4
PIO[3]
VSS33
N.C.
5
N.C.
6
PIO[13]
CB[1]
CB[6]
D[3]
PIO[10]
VSS33
CB[4]
N.C.
Reserved
PIO[15]
VCC33
VSS33
VSS33
D[13]
CB[0]
VSS33
CB[7]
D[6]
7
PIO[12]
CB[2]
VCC33
D[10]
D[15]
D[16]
VSS33
VSS33
N.C.
8
D[2]
9
D[1]
10
11
12
13
14
15
16
17
18
19
D[8]
D[5]
VCC33
VCC33
D[11]
Reserved
D[7]
D[4]
D[12]
D[17]
D[21]
D[25]
D[30]
VSS18
VDD18
VSS33
D[18]
N.C.
VSS33
VCC33
D[27]
D[14]
VSS33
N.C.
D[19]
D[23]
VCC33
D[22]
A[1]
N.C.
A[3]
N.C.
D[26]
D[29]
N.C.
A[12]
VSS18
VDD18
VSS18
D[28]
VCC33
D[31]
N.C.
N.C.
A[6]
VSS18
VDD18
VDD18
N.C.
A[7]
VSS33
A[8]
VCC33
VSS18
A[0]
A[4]
A[2]
VSS33
A[9]
Table 2. AT697E MCGA349 pinout (suite)
H
j
k
l
m
n
p
1
2
RAMOE[0]
RAMOE[2]
VCC33
VSS33
ROMS[1]
ROMS[0]
RWE[0]
WRITE
RWE[2]
N.C.
READ
TCK
DSUACT
DSURX
DSUTX
DSUEN
TMS
BEXC
VCC33
VSS33
SDDQM[1]
N.C.
SDWE
PCI_CLK
VSS33
SDCS[0]
SDCAS
A/D[24]
A/D[30]
A/D[18]
A/D[17]
IRDY
SDCLK
DSUBRE
SDDQM[2]
N.C.
3
TDI
4
RAMOE[4]
RWE[1]
RWE[3]
RAMS[0]
RAMS[3]
CB[5]
TDO
VSS33
IOS
5
SDDQM[3]
GNT
6
VSS33
SDDQM[0]
BRDY
VSS33
VSS33
VCC33
A/D[22]
VSS33
7
TRST
OE
VCC33
A/D[21]
A/D[16]
PERR
8
VCC33
PIO[14]
D[0]
9
VSS33
N.C.
SDRAS
A/D[14]
10
D[9]
4
AT697E
4226G–AERO–05/09
AT697
H
j
k
l
m
n
p
11
12
13
14
15
16
17
18
19
D[20]
D[24]
N.C.
A[10]
N.C.
A[11]
A[19]
A[13]
A[15]
A[5]
A[16]
A[26]
A[21]
A[27]
VCC33
A[23]
VSS33
A[22]
A[25]
N.C.
A/D[12]
AGNT[3]
N.C.
A/D[9]
A/D[15]
A/D[8]
A/D[5]
AGNT[1]
CLK
A[14]
VCC33
VCC33
VSS33
VSS33
A[17]
A[18]
A[20]
VDD_PLL
N.C.
A/D[1]
VSS33
A/D[0]
LOCK
A[24]
SKEW[1]
Reserved
LFT
BYPASS
AREQ[2]
N.C.
RESET
VCC33
VSS33
ERROR
VSS33
VSS33
N.C.
WDOG
VSS_PLL
SKEW[0]
AREQ[3]
VCC33
AREQ[1]
Table 3. AT697E MCGA349 pinout (suite 2)
r
REQ
t
u
v
w
1
2
VSS18
SDCS[1]
A/D[31]
A/D[29]
N.C.
VDD18
VDD18
VSS18
VCC33
A/D[26]
IDSEL
VCC33
FRAME
N.C.
N.C.
VSS18
VDD18
VSS18
N.C.
3
PCI_RST
N.C.
VDD18
VSS18
A/D[28]
A/D[25]
A/D[23]
A/D[19]
VSS33
VCC33
SERR
4
5
N.C.
6
N.C.
A/D[27]
VSS33
VSS33
VCC33
DEVSEL
VCC33
A/D[11]
A/D[7]
VSS33
C/BE[3]
A/D[20]
C/BE[2]
VCC33
C/BE[1]
VSS33
VSS33
A/D[4]
7
SYSEN
VSS33
TRDY
PCI_LOCK
VSS33
N.C.
8
9
10
11
12
13
14
15
16
17
18
19
STOP
VSS33
PAR
A/D[13]
VSS33
A/D[6]
VCC33
VCC33
N.C.
A/D[10]
C/BE[0]
VCC33
N.C.
VSS33
A/D[2]
N.C.
A/D[3]
N.C.
VCC33
AGNT[0]
AGNT[2]
VSS18
VDD18
VDD18
VSS18
VSS18
VDD18
VCC33
N.C.
VSS18
VDD18
VDD18
AREQ[0]
Notes: 1. ‘Reserved’ pins shall not be driven to any voltage
2. N.C. refers to unconnected pins
5
4226G–AERO–05/09
QFP256 Package
Table 4. AT697E MQFP256 pinout
pin
number
pin
pin
number
pin name
pin name
pin name
number
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
VCC33
PCI_REQ
PCI_GNT
PCI_CLK
PCI_RST
SDCS0
VSS
TCK
TMS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
VCC33
PIO7
PIO8
PIO9
VSS
2
3
VSS
4
TDI
5
TDO
6
WRITE
READ
OE
7
8
VDD18
SDCS1
SDWE
9
IOS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC33
ROMS0
ROMS1
RWE0
RWE1
RWE2
RWE3
RAMOE0
RAMOE1
RAMOE2
RAMOE3
RAMOE4
RAMS0
VCC33
RAMS1
RAMS2
RAMS3
VSS
SDRAS
VSS
VDD18
PIO10
PIO11
Reserved
PIO12
PIO13
PIO14
PIO15
VCC33
CB0
VSS
SDCAS
VCC33
SDDQM0
SDDQM1
SDDQM2
SDDQM3
SDCLK
BRDY
BEXC
CB1
VSS
CB2
VSS
CB3
DSUEN
DSUTX
DSURX
DSUBRE
DSUACT
TRST
VCC33
CB4
CB5
VDD18
RAMS4
PIO0
CB6
CB7
D0
6
AT697E
4226G–AERO–05/09
AT697
Table 5. AT697E MQFP256 pinout (suite)
pin
number
pin
pin
number
pin name
pin name
pin name
number
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
91
92
VCC33
D1
D25
D26
D27
D28
D29
D30
VCC33
D31
N.C.
A0
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
A19
A20
93
D2
A21
94
D3
A22
95
D4
VSS
96
D5
VCC33
A23
97
D6
98
Reserved
VCC33
D7
A24
99
A25
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
A26
D8
A1
A27
D9
VSS
VDD18
A2
WDOG
ERROR
VCC33
RESET
Reserved
LOCK
D10
D11
D12
A3
VCC33
D13
A4
VCC33
A5
D14
SKEW1
SKEW0
BYPASS
VSS_PLL
FLT
D15
A6
D16
A7
D17
A8
VSS
D18
A9
A10
VCC33
A11
A12
A13
A14
A15
A16
VCC33
A17
A18
VDD_PLL
CLK
VCC33
D19
VCC33
PCI_AREQ3
PCI_AGNT3
PCI_AREQ2
VSS
D20
D21
D22
D23
D24
VDD18
PCI_AGNT2
PCI_AREQ1
VCC33
VSS
VDD18
VCC33
7
4226G–AERO–05/09
Table 6. AT697E MQFP256 pinout (suite 2)
pin
number
pin
pin
number
pin name
pin name
pin name
number
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
PCI_AGNT1
PCI_AREQ0
PCI_AGNT0
A/D0
A/D12
A/D13
A/D14
A/D15
VCC33
C/BE1
PAR
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
A/D19
SYSEN
A/D20
VCC33
A/D21
A/D22
A/D23
IDSEL
C/BE3
VCC33
A/D24
A/D25
A/D26
VSS
VCC33
A/D1
A/D2
A/D3
SERR
PERR
VCC33
PCI_LOCK
STOP
A/D4
VSS
VDD18
VCC33
A/D5
DEVSEL
TRDY
A/D6
A/D7
VCC33
IRDY
VDD18
A/D27
VCC33
A/D28
A/D29
A/D30
A/D31
C/BE0
VSS
FRAME
VSS
VCC33
A/D8
C/BE2
A/D16
VCC33
A/D17
A/D18
A/D9
A/D10
A/D11
VCC33
Notes: 1. ‘Reserved’ pins shall not be driven to any voltage
2. N.C. refers to unconnected pins
8
AT697E
4226G–AERO–05/09
AT697
Pin Description
IU and FPU Signals
A[27:0] - Address bus (output)
A[27:0] bus carries the addresses during accesses to external memory. When access to
cache memory is performed, the address of the last external memory access remains
driven on the address bus.
D[31:0] - Data bus (bi-directional)
D[31:0] bus carries the data during accesses to memory. The processor automatically
configures the bus as output and drive the lines during write cycles.
During accesses to 8-bit areas, only D[31:24] are used.
During accesses to 16-bit areas, only D[31:16] are used.
CB[7:0] - Check bits (bi-directional)
CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7](1) takes the
value of tcb[7] in the error control register. Processor only drives CB[7:0] during write
cycles to areas programmed to be EDAC protected.
Note:
1. CB[7] is implemented to enable programming of flash memories. When only 7 bits
are useful for EDAC protection, 8 are needed for programming.
Memory Interface Signals
General management
OE* - Output enable (output)
This active low output is asserted during read cycles on the memory bus.
BRDY* - Bus ready (input)
When driven low, this input indicates to the processor that the current memory access
can be terminated on the next rising clock edge. When driven high, this input indicates
to the processor that it must wait and not end the current access.
READ - Read cycle (output)
This active high output is asserted during read cycles on the memory bus.
WRITE* - Write enable (output)
This active low output provides a write strobe during write cycles on the memory bus.
PROM
SRAM
ROMS*[1:0] - PROM chip-select (output)
These active low outputs provide the chip-select signal for the PROM area. ROMS*[0] is
asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while
ROMS*[1] is asserted for the upper half.
RAMOE*[4:0] - RAM output enable (output)
These active low signals provide an individual output enable for each RAM bank.
RAMS*[4:0] - RAM chip-select (output)
These active low outputs provide the chip-select signals for each RAM bank.
RWE* [3:0] - RAM write enable (output)
These active low outputs provide individual write strobes for each byte. RWEN[0] con-
trols D[31:24], RWEN[1] controls D[23:16], etc.
9
4226G–AERO–05/09
I/O
IOS* - I/O select (output)
This active low output is the chip-select signal for the memory mapped I/O area.
SDRAM Interface
SDCLK - SDRAM clock (output)
SDRAM clock provides the SDRAM interface clock reference.
SDCAS* - SDRAM column address strobe (output)
This active low signal provides a common CAS for all SDRAM devices.
SDCS*[1:0] - SDRAM chip select (output)
These active low outputs provide the chip select signals for the two SDRAM banks.
SDDQM[3:0] - SDRAM data mask (output)
These active low outputs provide the DQM signals for both SDRAM banks.
SDRAS*- SDRAM row address strobe (output)
This active low signal provides a common RAS for all SDRAM devices.
SDWEN - SDRAM write strobe (output)
This active low signal provides a common write strobe for all SDRAM devices.
System Signals
CLK - Processor clock (input)
The CLK input provides the main processor clock reference.
RESET* - Processor reset (input)
When asserted, this active low input will reset the processor and all on-chip peripherals.
WDOG* - Watchdog time-out (open-drain output)
This active low output is asserted when the watchdog expires.
BEXC* - Bus exception (input)
This active low input is sampled simultaneously with the data during accesses on the
memory bus. If asserted, a memory error will be generated.
ERROR* - Processor error (open-drain output)
This active low output is asserted when the processor has entered error state and is
halted. This happens when traps are disabled and a synchronous (un-maskable) trap
occurs.
PIO[15:0] - Parallel I/O port (bi-directional)
These bi-directional signals can be used as inputs or outputs to control external devices.
BYPASS - PLL bypass (input)
When driven to VCC, this active high input set the PLL in bypass mode. The device is
then directly clocked by the external clock. When grounded, the device is clocked
through the PLL.
SKEW[1:0] - Clock tree skew (input)
These input signals configurate the programmable skew on the triplicated clock trees.
LOCK - PLL lock (output)
10
AT697E
4226G–AERO–05/09
AT697
This active high output is asserted when the PLL output (internal node) is locked at the
frequency corresponding to four times the input command.
LFT - PLL passive low pass filter (input)
This input is used to connect the PLL passive low pass filter.
DSU Signals
DSUACT - DSU active (output)
This active high output is asserted when the processor is in debug mode and controlled
by the DSU.
DSUBRE - DSU break enable (input)
A low-to-high transition on this active high input will generate break condition and put
the processor in debug mode.
DSUEN - DSU enable (input)
The active high input enables the DSU unit. If de-asserted, the DSU trace buffer will
continue to operate but the processor will not enter debug mode.
DSURX - DSU receiver (input)
This active high input provides the data to the DSU communication link receiver
DSUTX - DSU transmitter (output)
This active high input provides the output from the DSU communication link transmitter.
JTAG
TCK - Test Clock (input)
Used to clock serial data into boundary scan latches and control sequence of the test
state machine. TCK can be asynchronous with CLK.
TMS - Test Mode select (input)
Primary control signal for the state machine. Synchronous with TCK. A sequence of val-
ues on TMS adjusts the current state of the TAP.
TDI - Test data input (input)
Serial input data to the boundary scan latches. Synchronous with TCK
TDO - Test data output (output)
Serial output data from the boundary scan latches. Synchronous with TCK
TRST - Test Reset (input)
Resets the test state machine. Can be asynchronous with TCK. Shall be grounded for
end application.
PCI Arbiter
AREQ*[3:0] - PCI bus request (Input)
When asserted, these active low inputs indicate that a PCI agent is requesting the bus.
AGNT*[3:0] - PCI bus grant (Output)
When asserted, these active low outputs indicate that a PCI agent is granted the PCI
bus.
11
4226G–AERO–05/09
PCI interface
A/D[31:0] - PCI Address Data (bi-directional)
Address and Data are multiplexed on the same PCI pins.
During the address phase, A/D[31::00] contain a physical address (32 bits). For I/O, this
is a byte address; for configuration and memory, it is a DWORD address. During data
phases, A/D[07::00] contain the least significant byte and A/D[31::24] contain the most
significant byte.
C/BE[3:0]* - PCI Bus Command and Byte Enables (bi-directional)
During the address phase of a transaction, C/BE[3::0]* define the bus command. During
the data phase, C/BE[3::0]* are used as Byte Enables. The Byte Enables are valid for
the entire data phase.
PAR - Parity (bi-directional)
The number of "1"s on A/D[31::00], C/BE[3::0]*, and PAR equals an even number
FRAME* - Cycle Frame (bi-directional)
It is driven by the current master to indicate the beginning and duration of an access.
FRAME* is asserted to indicate a bus transaction is beginning. While FRAME* is
asserted, data transfers continue. When FRAME* is deasserted, the transaction is in the
final data phase or has completed.
IRDY* - Initiator Ready (bi-directional)
IRDY* indicates the initiating agent’s ability to complete the current data phase of the
transaction. IRDY* is used in conjunction with TRDY*. During a write, IRDY* indicates
that valid data is present on A/D[31::00]. During a read, it indicates the master is pre-
pared to accept data.
TRDY* - Target Ready (bi-directional)
TRDY* indicates the target agent’s (selected device’s) ability to complete the current
data phase of the transaction. TRDY* is used in conjunction with IRDY*. During a read,
TRDY* indicates that valid data is present on AD[31::00]. During a write, it indicates the
target is prepared to accept data.
STOP* - Stop (bi-directional)
STOP* indicates the current target is requesting the master to stop the current
transaction.
PCI_LOCK* - Lock (bi-directional)
PCI_LOCK* indicates an atomic operation to a bridge that may require multiple transac-
tions to complete.
IDSEL - Initialization Device Select (input)
Initialization Device Select is used as a chip select during configuration read and write
transactions.
DEVSEL* - Device Select (bi-directional)
When actively driven, indicates the driving device has decoded its address as the target
of the current access. As an input, DEVSEL* indicates whether any device on the bus
has been selected.
REQ* - PCI bus request (output)
12
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AT697
REQ* indicates to the arbiter that this agent desires use of the bus. This is a point-to-
point signal. Every master has its own REQ* which must be tri-stated while PCI_RST* is
asserted.
GNT* - PCI Bus Grant (input)
GNT* indicates to the agent that access to the bus has been granted. This is a point-to-
point signal. Every master has its own GNT* which must be ignored while PCI_RST* is
asserted.
PCI_CLK - PCI clock (input)
PCI_CLK provides timing for all transactions on PCI. All other PCI signals, except
PCI_RST*, are sampled on the rising edge of PCI_CLK and all other timing parameters
are defined with respect to this edge.
PCI_RST* - PCI Reset (input)
Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent
state.
PERR* - Parity Error (bi-directional)
Parity Error is only for the reporting of data parity errors during all PCI transactions
except a Special Cycle. The PERR* pin is sustained tri-state and must be driven active
by the agent receiving data two clocks following the data when a data parity error is
detected. The minimum duration of PERR* is one clock for each data phase that a data
parity error is detected.
SERR* - System Error (bi-directional)
System Error is for reporting address parity errors, data parity errors on the special cycle
command, or any other system error where the result will be catastrophic. If an agent
does not want a non-maskable interrupt (NMI) to be generated, a different reporting
mechanism is required.
SYSEN* - PCI Host (input)
This active low input specifies the configuration of the device. At boot-up time, if
SYSEN* is sampled at a low level, the device is configured as the host of the PCI bus. If
SYSEN* is sampled at a high level, the device is configured as a satellite.
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4226G–AERO–05/09
AT697 CPU Core
This section discusses the SPARC core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
SPARC Architecture
Overview
The AT697 CPU core is based on the LEON2 architecture.
Figure 2. Block diagram of the AT697 Integer Unit architecture
call/branch address
I-cache
+1
Add
jmpa tbr
f_pc
‘0’
data
address
Fetch
d_inst
e_inst
d_pc
Decode
imm, tbr, wim, psr
e_pc
rs1
operand2
Execute
mul/div
y
alu/shift
32
30
ex pc
jmpl address
m_inst
w_inst
m_pc
w_pc
result
ytmp
D-cache
Memory
Write
32
32
address/dataout
datain
wres
Y
30
tbr, wim, psr
rd
regfile
rs2
rs1
The AT697 integer unit (IU) implements SPARC integer instructions as defined in
SPARC Architecture Manual version 8. The IU is designed for highly dependable space
and military applications by including fault tolerance features.
To execute instructions at a rate approaching one instruction per clock cycle, the IU
employs a five-stage instruction pipeline that permits parallel execution of multiple
instructions.
•
Instruction Fetch: If the instruction cache is enabled, the instruction is fetched from
the instruction cache. Otherwise, the fetch is forwarded to the memory controller.
The instruction is valid at the end of this stage and is latched inside the IU.
•
Decode: The instruction is decoded and the operands are read. Operands may
come from the register file or from internal data bypasses. CALL and Branch target
addresses are generated in this stage.
•
•
Execute: ALU, logical, and shift operations are performed. For memory operations
and for JMPL/RETT, the address is generated.
Memory: Data cache is accessed. For cache reads, the data will be valid by the end
of this stage, at which point it is aligned as appropriate. Store data read out in the
Execute stage is written to the data cache at this time.
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AT697
•
Write: The result of any ALU, logical, shift, or cache read operations re written back
to the register file.
All five stages operate in parallel, working on up to five different instructions at a time. A
basic ’single-cycle’ instruction enters the pipeline and completes in five cycles.
By the time it reaches the write stage, four more instructions have entered and are driv-
ing through the pipeline behind it. So, after the first five cycles, a single-cycle instruction
exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of
course, a ’single-cycle’ instruction actually takes five cycles to complete, but they are
called single cycle because with this type of instruction the processor can complete one
instruction per cycle after the initial five-cycle delay.
In order to maximize performance and parallelism, the AT697 SPARC implementation uses
powerful AMBA bus. Instructions in the program memory are executed with a five level pipelin-
ing. While one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle.
Program Counters
Two 32-bit program counters (PC and nPC) are provided. The 32-bit PC contains the
address of the instruction currently being executed by the IU. The nPC holds the
address of the next instruction to be executed (assuming a trap does not occur).
When a trap occurs, the PC address is saved in the local register (l1) while the nPC
address is saved in the local register (l2). When returning from trap, l1 value is copied
back to PC and l2 value is copied back to nPC.
ALU - Arithmetic Logic Unit
The high-performance ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate memory address are exe-
cuted. The implementation of the architecture also provide a powerful multiplier/divider
supporting both signed and unsigned multiplication/division.
Support for high performance 64-bit operation is also provided.The 32-bit Y register con-
tains the most significant word of the double-precision product of an integer
multiplication, as a result of either an integer multiply instruction, or of a routine that uses
the integer multiply step instruction. The Y register also holds the most significant word
of the double-precision dividend for an integer divide instruction.
Register File - Windows
The fast access register file contains 8 SPARC register windows. Each window consists
in a 32-register set. When a program is running, it has access to 32 32-bit processor
registers which include 8 global registers plus 24 registers that belong to the current reg-
ister window.
•
•
•
The first 8 registers in the window are called the in registers’ (i0-i7). When a function
is called, these registers may contain arguments that can be used.
The next 8 are the ’local registers’ (l0-l7) which are scratch registers that can be
used for anything while the function executes.
The last 8 registers are the ’out registers’ (o0-o7) which the function uses to pass
arguments to functions that it calls.
AT697 register file implementation is based on two dual-port rams. The first dual-port
ram corresponds to %rs1 operand of a SPARC instruction while the second corre-
sponds to %rs2 operand. The two dual-port rams contents are always equal.
When one function calls another, the calling function can choose to execute a SAVE
instruction. This instruction decrements an internal counter, the current window pointer
(cwp), shifting the register window downward. The caller’s out registers then become
15
4226G–AERO–05/09
the calling function’s in registers, and the calling function gets a new set of local and out
registers for its own use. Only the pointer changes because the registers and return
address do not need to be stored on a stack. The RETURN instruction acts in the oppo-
site way
Figure 3. Overlapping Windows
W7
cwp
w7
w7
ins
locals
w7
outs
w0
w0 outs
w6
w1
outs
locals
ins
w6
w0
ins
locals
W0
w1
W1
W6
w5
ins
w6
outs
locals
globals
w2
outs
w5
w1
ins
locals
W2
W5
w2
W4
w4
ins
locals
w5
outs
w4
w2
ins
locals
w4
outs
w3
outs
w3
w3
ins
locals
W3
The Window Invalid Mask register (WIM) is controlled by supervisor software and is
used by hardware to determine whether a window overflow or underflow trap is to be
generated by a SAVE, RESTORE, or RETT instruction.
When a SAVE, RESTORE, or RETT instruction is executed, the current value of the
CWP is compared against the WIM register. If the SAVE, RESTORE, or RETT instruc-
tion would cause the CWP to point to an “invalid” register set, a window_overflow or
window_underflow trap is caused.
To prevent erroneous operations from SEU errors in the main register file, each word is
protected with a 7-bit EDAC checksum. The EDAC checksums are checked when the
register is used as operand in an instruction. Any single-bit error is corrected and written
back to the register file before the instruction is executed. If an un-correctable error is
detected, a register hardware error trap (trap 0x20) is generated.
The protection can be enabled/disabled by programming the ‘di’ bit from register file pro-
tection control register. By setting the ‘te’ bit, errors can be inserted in the register file to
test the protection function. When the ‘te’ bit is set, the register checksum is combined
with the ‘tcb’ field before being written to the register file.
Due to the presence of the two dual-port rams for register file implementation, the fol-
lowing rules apply to the error injection test process.
•
Test checkbits TCB[2:0] is Xored with checkbit[6:4] corresponding to the %rs1
operand.
•
Test checkbits TCB[5:3] is Xored with checkbit[6:4] corresponding to the %rs2
operand.
Here is a simple example for the test of a single error in register file %rs1
! 0x32 =
!
!
!
register file test enable
tcb[2:0] = 0x4
tcb[5:3] = 0x1
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AT697E
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AT697
mov 0x32, %l1
mov %l1, %asr16
! clear %l3
! => write 0x0 to %l3
!
forces 0x08 as checkbit for %l3 (error insertion in %rs1 dual-port ram)
mov %g0, %l3
! disable EDAC test mode
mov %g0, %asr16
! access to %l3 as %rs1 operand
! => single error detection and correction
add %l3,%l2,%l1
A correction counter ‘cnt’ is provided for error management. The ‘cnt’ field is incre-
mented each time a register correction is performed. It saturates at “111”.
State Register
The State Register (PSR) contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to per-
form conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the SPARC architecture specification. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The state also provides some global information on the current window used, the autho-
rized interrupts and peripheral (FPU and coprocessor) presence. A global interrupt
management is provided through the processor state register. Trap and Interrupts can
be individually enabled/disables from within this register.
Instruction Set
AT697 instructions fall into six functional categories: load/store, arithmetic/logical/ shift,
control transfer, read/write control register, floating-point, and miscellaneous. Please
refer to SPARC V8 Architecture manual that presents all the implemented instructions.
Floating Point Unit
The FPU is designed to provide execution of single and double-precision floating-point
instructions. During the execution of floating-point instructions the processor pipeline is
held.
The FPU is designed for highly dependable space and military applications, by including
fault tolerance features like error detection and correction and triple modular
redundancy.
The FPU depends upon the IU to access all addresses and control signals for memory
access. Floating-point loads and stores are executed in conjunction with the IU, which
provides addresses and control signals while the FPU supplies or stores the data.
Instruction fetch for integer and floating-point instructions is provided by the IU.
The FPU contains 32 32-bit floating-point f registers, which are numbered from f[0] to
f[31]. Unlike the windowed r registers, at a given time an instruction has access to any of
the 32 f registers. The f registers can be read and written by FPop (FPop1/FPop2 for-
mat) instructions, and by load/store single/double floating-point instructions (LDF,
LDDF, STF, STDF).
Rounding Direction
Rounding direction for floating point results is built according to the ANSI/IEEE Standard
754-1985.
In this way,
•
0 = round to nearest
17
4226G–AERO–05/09
•
•
•
1 = round to zero
2 = round to +infinity
3 = round to -infinity
Figure 4. Rounding Direction Schematic
Value < 0
0
Value > 0
- ∞
+
∞
round to - ∞
round to zero
round to + ∞
round to - ∞
round to + ∞
round to zero
Fault Tolerance
The processor has been especially designed for space application. To prevent errone-
ous operations from single event transient (SET) and single event upset (SEU) errors,
the AT697 processor implements a set of protection features including :
•
Full triple modular redundancy (TMR) architecture
The TMR architecture is based on a fully triplicated clock distribution (CLK1, CLK2
and CLK3). The PCI clock and the CPU clock are built as three-clock trees. The
same triplication is applied to the PCI reset and to the CPU reset. See figure 5 for an
overview of the TMR architecture.
Programmable skews on the clock trees are also provided to prevent the processor
from arbitrary single-event transient errors.
Refer to the ‘clock’ section for detailed information on TMR implementation and
skew implementation.
•
•
•
EDAC protection on Regfile
EDAC protection on external memory interface
Parity protection on instruction and data caches
Figure 5. TMR structure - Clock triplication principle
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AT697
Watch Points
The integer unit contains four hardware watch-points allowing generation of a trap on an
arbitrary memory address range. Any binary aligned address range can be watched (the
two less significant bits are ignored)
Each watch-point consists in a pair of application-specific registers
•
break address register
The break address defines a reference address for testing.
•
mask register
The mask indicates which bits of the break address register are to be effectively
taken in account during address test
Configuration
A watchpoint is enabled setting logical one at least one of the three bits IF, Dl or DS in
the watchpoint address and mask registers. When all three bits are set logical zero, the
watchpoint is disabled.
If the instruction fetch bit (IF) from the watchpoint address register is set logical one, any
attempt to fetch an instruction from one of the address defined by ADDR and MASK
results in a trap generation.
If the data store bit (DS) from the watchpoint address register is set logical one, any
attempt to store data to one of the address defined by ADDR and MASK results in a trap
generation.
If the data load bit (DL) from the watchpoint mask register is set logical one, any attempt
to load a data from one of the address defined by ADDR and MASK results in a trap
generation.
Operation
To detect if an address is part of the memory address range that traps, address bit 31
down to bit 2 are Xored with the ADDR field from the watchpoint address register.
This operation is based on the following segmentation of an address.
Table 7. Address Segmentation
bit num. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
field
Address
ignored
With such segmentation, it is possible to define trap segment from 4bytes up to 1Gbyte.
The result of the Xor is then Anded with the MASK field of the watchpoint mask register.
If the result is zero, this indicates that address specified is in the watched range. Then, a
watchpoint hit error is generated. Trap 0x0B is generated. If result is different from zero,
address is out of the watched address range.
Figure 6. Watchpoint Hit Principle
30
IF
30
DS
logic
Trap 0x0B
DL
30
30
Watchpoint Mask Reg.
%asry
Watchpoint Address Reg.
%asrx
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4226G–AERO–05/09
Traps and Interrupts
Overview
The AT697 supports two types of traps:
- synchronous traps
- asynchronous traps also called interrupts.
Synchronous traps are caused by hardware responding to a particular instruction: they
occur during the instruction that caused them. Asynchronous traps occur when an exter-
nal event interrupts the processor. They are not related to any particular instruction and
occur between the execution of instructions.
A trap is a vectored transfer of control to the supervisor through a special trap table that
contains the first four instructions of each trap handler. The trap base address (TBR) of
the table is established by supervisor and the displacement, within the table, is deter-
mined by the trap type.
A trap causes the current window pointer to advance to the next register window and the
hardware to write the program counters (PC & nPC) into two registers of the new
window.
Synchronous Traps
The AT697 follows the general SPARC trap model. The table below shows the imple-
mented traps and their individual priority.
Table 8. Trap Overview
Trap
TT (trap type)
0x00
Priority
Description
reset
1
2
Power-on reset
Write buffer error
write error
0x2b
Error during instruction fetch
Edac uncorrectable error during instruction fetch
instruction_access_exception
0x01
3
illegal_instruction
privileged_instruction
fp_disabled
0x02
0x03
0x04
0x24
0x0B
0x05
0x06
0x20
0x07
0x08
5
4
UNIMP or other un-implemented instruction
Execution of privileged instruction in user mode
FP instruction while FPU disabled
co-processor instruction while co-processor disabled
Instruction or data watchpoint match
SAVE into invalid window
6
cp_disabled
6
watchpoint_detected
window_overflow
window_underflow
register_hadrware_error
mem_address_not_aligned
fp_exception
7
8
8
RESTORE into invalid window
9
register file uncorrectable EDAC error
Memory access to un-aligned address
FPU exception
10
11
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AT697
data_access_exception
tag overflow
0x09
0x0A
13
14
15
16
Access error during load or store instruction
Tagged arithmetic overflow
Divide by zero
divide_exception
trap_instruction
0x2A
0x80 -0xFF
Software trap instruction (TA)
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4226G–AERO–05/09
Traps Description
•
reset - A reset trap is caused by an external reset request. It causes the processor
to begin executing at virtual address 0. After a Reset Trap, no special memory
states are defined exept the PSR’s ‘et’ and ‘s’ bits that are initialized respectively ‘0’
and ‘1’.
•
•
write error - An error exception occurred on a data store to memory.
instruction_access_exception - A blocking error exception occurred on an
instruction access.
•
illegal_instruction - An attempt was made to execute an instruction with an
unimplemented opcode, or an UNIMP instruction, or an instruction that would result
in illegal processor state.
•
•
•
•
privileged_instruction - An attempt was made to execute a privileged instruction
while supervisor bit (s) in PSR is ‘0’ (not in supervisor mode).
fp_disabled - An attempt was made to execute an FPU instruction while FPU is not
enabled or not present.
cp_disabled - An attempt was made to execute a co-processor instruction while co-
processor is not enabled or not present.
watchpoint_detected - An instruction fetch memory address or load/store data
memory address matched the contents of a pre-loaded implementation-dependent
“watchpoint” register.
•
•
•
window_overflow - A SAVE instruction attempted to cause the current window
pointer (CWP) to point to an invalid window in the WIM.
window_underflow - A RESTORE or RETT instruction attempted to cause the
current window pointer (CWP) to point to an invalid window in the WIM.
register_hardware_error - An error exception occurred on a read only register
access.
A register file uncorrectable error was detected.
•
•
mem_address_not_aligned - A load/store instruction would have generated a
memory address that was not properly aligned according to the instruction, or a
JMPL or RETT instruction would have generated a non-word-aligned address.
fp_exception - An FPU instruction generated an IEEE_754_exception and its
corresponding trap enable mask (TEM) bit was 1, or the FPU instruction was
unimplemented, or the FPU instruction did not complete, or there was a sequence
or hardware error in the FPU. The type of floating-point exception is encoded in the
FSR’s ftt field.
•
•
data_access_exception - A blocking error exception occurred on a load/store data
access. EDAC uncorrectable error.
tag_overflow - A tagged arithmetic instruction was executed, and either arithmetic
overflow occurred or at least one of the tag bits of the operands was non zero.
•
•
trap_division_by_zero - An integer divide instruction attempted to divide by zero.
trap_instruction - A software instruction (Ticc) was executed and the trap condition
evaluated to true.
When multiple synchronous traps occur at the same cycle (i.e hardware errors), the
highest priority trap is taken, and lower priority traps are ignored.
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AT697
Asynchronous Traps /
Interrupts
The AT697 handles 11 interrupts. Interrupts can be due to external interrupt requests
not directly related to any particular instruction or can be due to exception caused by
particular previously executed instruction.
Figure 7. Interrupt Controller Block Diagram
Interrupt Sources
Internal Interrupt
PIO[15:0]
(Timer1, Uart1,...)
I/O Interrupt Reg.
IOIT
Interrupt Clear Reg.
ITC
Interrupt Pending Reg.
ITP
mask
trap1x generation
Interrupt Force Reg.
ITF
priority
Interrupt Mask & Priority Reg.
ITMP
Operation
When an interrupt is generated, the corresponding bit is set in the interrupt pending reg-
ister (ITP). The pending bits are ANDed with the interrupt mask register and then
forwarded to the priority selector. The highest interrupt from priority level 1 will be for-
warded to the IU - if no unmasked pending interrupt exists on priority level 1, then the
highest unmasked interrupt from priority level 0 is forwarded.
When the IU acknowledges the interrupt, the corresponding pending bit will automati-
cally be cleared.
Interrupt can also be forced by setting a bit in the interrupt force register. In this case,
the IU acknowledgement will clear the force bit rather than the pending bit.
After reset, the interrupt mask register is set to all zeros while the remaining control reg-
isters are undefined.
Interrupt List
The following table presents the assignement of the interrupts.
Table 9. Interrupt Overview
Interrupt
TT (Trap Type)
0x1F
Source
15
14
13
12
11
10
9
unused
0x1E
PCI
0x1D
unused
0x1C
unused
0x1B
DSU trace buffer
unused
0x1A
0x19
Timer 2
8
0x18
Timer 1
7
0x17
I/O interrupt [3]
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4226G–AERO–05/09
Interrupt
TT (Trap Type)
0x16
Source
6
5
4
3
2
1
I/O interrupt [2]
I/O interrupt [1]
I/O interrupt [0]
UART 1
0x15
0x14
0x13
0x12
UART 2
0x11
Internal bus error
I/O interrupts
As an alternate function of the general purpose interface, the AT697 allows to input
interrupt from external devices. Up to four external interrupts can be programmed at the
same time. The four interrupts are assigned to interrupt 4, 5, 6 and 7.
Each I/O interrupt consists of four fields in the I/O interrupt register (IOIT) : ENx, LEx,
PLx and ISELx.
An I/O interrupt is enabled setting logical one the ENx bit in the IOIT register. Setting this
bit logical zero disables the interrupt. The ISELx field in the IOIT register defines which
port of the general purpose interface should generate I/O interrupt x. The port can be
selected from within PIO[15:0] and D[15:0]*.
Each I/O interrupt can have its trigger mode and its polarity individually configured.
When the LEx bit is set logical one, the corresponding I/O interrupt is edge triggered. If
the polarity bit (PLx) is driven logical one the interrupt triggers when a rising edge is
applied on the pin. If the polarity bit is driven logical zero the interrupt triggers when a
falling edge is applied on the pin.
When the LEx bit is set logical zero, the corresponding I/O interrupt is level sensitive. If
the polarity bit (PLx) is driven logical one the interrupt triggers when a high level is
applied on the pin. If the polarity bit is driven logical zero the interrupt triggers when a
low level is applied on the pin.
The following table summarizes the I/O interrupt configurations.
Table 10. I/O Interrupt Configuration
LEx
0
PLx
0
Trigger
low level
0
1
high level
falling edge
rising edge
1
0
1
1
Interrupt Priority
The 15 interrupts handled by the AT697 are prioritised, with interrupt 15 (TT = 0x1F)
having the highest priority and interrupt 1 (TT = 0x11) the lowest.
It is possible to change the priority level of an interrupt using the two priority levels from
the interrupt mask and priority register (ITMP). Each interrupt can be assigned to one of
two levels as programmed in the Interrupt mask and priority register. Level 1 has higher
priority than level 0. Within each level the interrupts are prioritised.
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Cache Memories
Overview
The AT697 processor implements a Harvard architecture with separate instruction and
data buses, connected to two independent cache controllers. In order to improve the
speed performance of the cpu core, multi-set-caches are used for both instruction and
data caches.
The cache replacement policy used for both instruction and data caches is based on the
LRU algorithm. The least recently used (LRU) set of the cache is replaced when new
data need to be stored in cache.
Cache mapping
Most of the main memory areas can be cached. The cacheable areas are the PROM
and RAM areas. The following table presents the caching capabilities of the processor.
Table 11. Cache Capability List
Address Range
Area
PROM
I/O
Cache status
Cached
0x00000000 - 0x1FFFFFFF
0x20000000 - 0x3FFFFFFF
0x40000000 -0x7FFFFFFF
0x80000000 -0xFFFFFFFF
Non-cacheable
Cached
RAM
Internal
Non-cacheable
Operation
During normal operation, the processor accesses instructions and data using ASI 0x8 -
0xB as defined in the SPARC standard.
Using the LDA/STA instructions, alternative address spaces as caches can be
accessed. ASI[3:0] are used for the mapping when ASI[7:4] have no influence on
operation.
•
Access with ASI 0 - 3 will force a cache miss, update the cache if the data was
previously cached or allocate a new line if the data was not in the cache and the
address refers to a cacheable location.
•
Access to ASI 4 and 7 will force a cache miss and update the cache if the data was
previously cached.
The following table shows the ASI implementation on the AT697.
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AT697
Table 12. ASI Usage
ASI
Usage
0x0, 0x1, 0x2, 0x3
Forced cache miss (replace if cacheable)
Forced cache miss (update on hit)
Flush instruction cache
Flush data cache
0x4, 0x7
0x5
0x6
0x8, 0x9, 0xA, 0xB
Normal cached access (replace if cacheable)
Instruction cache tags
0xC
0xD
0xE
0xF
Instruction cache data
Data cache tags
Data cache data
Note:
Please refer to the SPARC v8 specification for detailed information on ASI usage.
Instruction Cache
Overview
The AT697 instruction cache is a multi-set cache of 32 kbyte divided in 4 memory sets.
Multi-set-cache use improves speed performance of the core. The instruction cache is
divided into cache lines with 32 bytes of data. Each line has a cache tag associated with
it consisting of a tag field and one valid bit per 4-byte sub-block.
Cache Control
Operation
The instruction cache operations are controled with the cache control register (CCR).
On an instruction cache miss to a cachable location, the instruction is fetched and the
corresponding tag and data line updated. The instruction cache always works in one of
three modes:
•
•
•
disabled,
enabled
or frozen.
The instruction cache current state is reported in the instruction cache state field (ICS)
of the cache controler register (CCR).
Disabled mode
Enabled mode
If disabled, no cache operation is performed and load and store requests are passed
directly to the memory controller.
If enabled, the cache operates as described above. In the frozen state, the cache is
accessed and kept in synchronisation with the main memory as if it was enabled, but no
new lines are allocated on read misses.
Freeze mode
If the freeze on interrupt bit (IF) bit is set logical one on the cache control register (CCR),
the instruction cache is frozen when an asynchronous interrupt is taken. This can be
beneficial in real-time system to allow a more accurate calculation of worst-case execu-
tion time for a code segment. The execution of the interrupt handler will not evict any
cache lines and when control is returned to the interrupted task, the cache state is iden-
tical to what it was before the interrupt.
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4226G–AERO–05/09
If a cache has been frozen by an interrupt, it can only be enabled again by enabling the
cache in the CCR. This is typically done at the end of the interrupt handler before control
is returned to the interrupted task.
Burst fetch
An instruction burst fetch mode can be enabled setting logical one the burst fetch bit (IB)
in the cache control register. If the burst fetch is enabled, the cache line is filled from
main memory starting at the missed address and until the end of the line. At the same
time, the instructions are forwarded to the IU. If the IU cannot accept the streamed
instructions due to internal dependencies or multi-cycle instruction, the IU is halted until
the line fill is completed.
If the IU executes a control transfer instruction during the line fill, the line fill will be termi-
nated on the next fetch. If instruction burst fetch is enabled, instruction streaming is
enabled even when the cache is disabled. In this case, the fetched instructions are only
forwarded to the IU and the cache is not updated.
Cache Flush
Instruction cache can be flushed by executing the FLUSH instruction, setting logical one
the flush instruction cache bit (FI) in the cache control register, or writing any location
with ASI=0x5. The flush operation takes one cycle per line during which the IU will is not
halted, but during which the cache is disabled. When the flush operation is completed,
the cache will resume the state indicated in the cache control register.
Error reporting
If a memory access error occurs during a line fill with the IU halted, the corresponding
valid bit in the cache tag is not set. If the IU later fetches an instruction from the failed
address, a cache miss will occur, triggering a new access to the failed address.
If the error remains, an instruction access error trap (tt=0x1) is generated.
Instruction Cache Parity
Error detection of cache tags and data is implemented using two parity bits per tag and
per 4-byte data sub-block. The tag parity is generated from the tag value and the valid
bits. The data parity is derived from the sub-block data. The parity bits are written simul-
taneously with the associated tag or sub-block and checked on each access. The two
parity bits correspond to the parity of odd and even data (tag) bits.
If a tag parity error is detected during a cache access, a cache miss is generated. The
tag and the data are automatically updated. All valid bits except the one corresponding
to the newly loaded data are cleared. Each error is reported in the instruction cache tag
error counter from the CCR. The instruction cache tag error counter (ITE) is incre-
mented after each instruction cache tag error detection.
If a data sub-block parity error occurs, a miss is also generated but only the failed sub-
block is updated with data from main memory. Each error is reported in the instruction
cache data error counter from the CCR. The instruction cache data error counter (IDE)
is incremented after each instruction cache data error detection.
Data Cache
Overview
The AT697 data cache is a multi-set cache of 16 kbyte divided in 2 memory sets. Multi-
set-cache use improves speed performance. The data cache is divided into cache lines
with 16 bytes of data. Each line has a cache tag associated with it consisting of a tag
field and one valid bit per 4-byte sub-block.
Cache Control
Operation
The instruction cache operations are controled with the cache control register (CCR).
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AT697
Write
The write policy for stores is write-through with no-allocate on write-miss. The write buf-
fer (WRB) consists of three 32-bit registers used to temporarily hold store data until it is
sent to the destination device. For half-word or byte stores, the stored data replicated
into proper byte alignment for writing to a word-addressed device, before being loaded
into one of the WRB registers.
The WRB is emptied prior to a load-miss cache-fill sequence to avoid any stale data
from being read in to the data cache.
Read
On a data cache read-miss to a cachable location, 4 bytes of data are loaded into the
cache from main memory.
Cache Flush
Data cache can be flushed by executing the FLUSH instruction, setting logical one the
flush data cache bit (FD) in the cache control register, or writing any location with
ASI=0x6. The flush operation takes one cycle per line during which the IU will is not
halted, but during which the cache is disabled. When the flush operation is completed,
the cache will resume the state indicated in the cache control register.
Error Reporting
Since the processor executes in parallel with the write buffer, a write error will not cause
an exception to the store instruction. Depending on memory and cache activity, the write
cycle may not occur until several clock cycles after the store instructions has completed.
If a write error occurs, the currently executing instruction will take trap 0x2B.
Note:
the 0x2B trap handler should flush the data cache, since a write hit would update the
cache while the memory would keep the old value due the write error.
If a memory access error occurs during a data load, the corresponding valid bit in the
cache tag will not be set. and a data access error trap (tt=0x09) is generated.
Data Cache Parity
Error detection of cache tags and data is implemented using two parity bits per tag and
per 4-byte data sub-block. The tag parity is generated from the tag value and the valid
bits. The data parity is derived from the sub-block data. The parity bits are written simul-
taneously with the associated tag or sub-block and checked on each access. The two
parity bits correspond to the parity of odd and even data (tag) bits.
If a tag parity error is detected during a cache access, a cache miss is generated. The
tag and the data are automatically updated. All valid bits except the one corresponding
to the newly loaded data are cleared. Each error is reported in the instruction cache tag
error counter from the CCR. The data cache tag error counter (DTE) is incremented
after each data cache tag error detection.
If a data sub-block parity error occurs, a miss is also generated but only the failed sub-
block is updated with data from main memory. Each error is reported in the data cache
data error counter from the CCR. The data cache data error counter (DDE) is incre-
mented after each data cache data error detection.
Data Cache Snooper
In addition to the cache controller, a snooper is implemented on the on-chip cache sub-
system. The cache snooper is enabled setting logical one the snoop enable bit (DS) in
the cache control register.
This snooper is able to verify if a master on the internal bus accesses and modifies
some cached data. If a master accesses a data in memory and this data is cached, the
snooper will invalidate the corresponding cache tag. Next time the IU will access the
modified data, a cache miss will be generated due to not valid tag.
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Diagnostic Cache
Access
Tags and data in the instruction and data cache can be accessed through ASI address
space 0xC, 0xD, 0xE and 0xF by executing LDA and STA instructions. Address bits
making up the cache offset will be used to index the tag to be accessed while the least
significant bits of the bits making up the address tag will be used to index the cache set.
Diagnostic read of tags is possible by executing an LDA instruction with ASI=0xC for
instruction cache tags and ASI=0xE for data cache tags. The cache line and the cache
set are indexed by the address bits making up the cache offset and the least significant
bits of the address bits making up the address tag.
Similarly, the data sub-blocks may be read by executing an LDA instruction with
ASI=0xD for instruction cache data and ASI=0xF for data cache data. The sub-block to
be read in the indexed cache line and set is selected by A[4:2].
The tags can be directly written by executing a STA instruction with ASI=0xC for the
instruction cache tags and ASI=0xE for the data cache tags. The cache line and cache
set are indexed by the address bits making up the cache offset and the least significant
bits of the address bits making up the address tag.
D[31:10] is written into the ATAG filed and the valid bits are written with the D[7:0] of the
write data. The data sub-blocks can be directly written by executing a STA instruction
with ASI=0xD for the instruction cache data and ASI=0xF for the data cache data. The
sub-block to be read in the indexed cache line and set is selected by A[4:2].
Note:
Diagnostic access to the cache is not possible during a FLUSH operation and will cause
a data exception (trap=0x09) if attempted.
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AT697
Memory Interface
Overview
The AT697 provides a 32-bit bus capable to interface PROM, memories mapped I/O
devices, asynchronous static rams (SRAM) and synchronous dynamic rams (SDRAM).
The memory bus can be configured either for 8-bit, 16-bit, 32-bit or 40-bit accesses. The
memory controller manages up to 2 Gbytes of external memory. The following table
presents the memory controller address map.
Table 13. Memory Controller address map
Address Range
Size
512M
256M
1G
Mapping
PROM
0x00000000 - 0x1FFFFFFF
0x20000000 - 0x2FFFFFFF
0x40000000 - 0x7FFFFFFF
I/O
SRAM/SDRAM
For applications that require smaller memory areas and/or smaller performances, it is
possible to configure some memory spaces as 8-bit or 16-bit wide data bus.
All the configuration of the memory interface is done through the three memory control-
ler registers : MCFG1, MCFG2 and MCFG3. MCFG1 is the register dedicated to PROM
and IO configuration. SRAM and SDRAM are configured through MCFG2 and MCFG3.
Here is an overview of the 32-bit interconnection between the AT697 and external
memories.
Figure 8. Memory Interface Overview
CS
OE
WE
ROMS*[1:0]
OE*
A
D
PROM
I/O
WRITE*
CS
OE
WE
IOS*
A
D
AT697
CS
OE
WE
RAMS*[4:0]
RAMOE*[4:0]
RWE*[3:0]
A
D
SRAM
A[16:15]
A[14:2]
CLK
CSN
RAS
CAS
WE
SDCLK
SDCSN[1:0]
SDRAS*
SDCAS*
SDWE*
SDDQM[3:0]
BA
A
SDRAM
D
DQM
A[27:0]
D[31:0]
To improve the bandwidth of the memory bus, accesses to consecutive addresses can
be performed in burst mode. Burst transfers will be generated when the memory control-
ler is accessed using a burst request from the internal bus. These includes instruction
cache-line fills, double loads and double stores. The timing of a burst cycle is identical to
the programmed basic cycle with the exception that during read cycles, the lead-out
cycle will only occurs after the last transfer.
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RAM Interface
The memory controller gives the capability to control up to 1Gbyte of RAM. The global
RAM area supports two RAM types : asynchronous static RAM (SRAM) and synchro-
nous dynamic RAM (SDRAM).
SRAM interface
Overview
The SRAM interface can manage up to five SRAM banks. The control of the SRAM
memory accesses uses a standard set of pin, including chip selects (RAMS*x), output
enable (RAMOE*x) and write enable (RWE*x) lines.
The bank size of the four first banks of the SRAM area can be configured by setting the
value of the SRAM bank size field in MCFG2. The bank size can be programmed in
binary step from 8 Kbytes to 256 Mbytes. Whatever is the size of the four first banks,
they are always contiguous. These memory banks are selected with RAMS*[3] down to
RAMS*[0].
The fifth SRAM bank controlled by RAMS*[4] has a fix dimension. This bank always
resides at the upper address 0x60000000. This bank is always 256 Mbytes large.
Figure 9. SRAM bank organisation
SRAM bank size
256MB
128MB
64MB
Memory
assignement
Memory
assignement
Memory
assignement
Start Address
0x7C000000
0x78000000
0x74000000
0x70000000
0x6C000000
0x68000000
0x64000000
0x60000000
0x5C000000
0x58000000
0x54000000
0x50000000
0x4C000000
0x48000000
0x44000000
0x40000000
Unused
RAMS*[4](1)(2)
RAMS*[1]
Unused
Unused
RAMS*[4](2)
Unused
RAMS*[4](2)
RAMS*[3]
RAMS*[2]
RAMS*[1]
RAMS*[0]
RAMS*[3]
RAMS*[2]
RAMS*[1]
RAMS*[0]
RAMS*[0]
Notes: 1. If the SRAM bank size is set to 256Mbytes, SRAM bank 2 & bank 3 are in overlay
with SRAM bank 4. In this case, bank 2 and bank 3 control signals are never
asserted. Bank 4 has the priority.
2. When SDRAM is enabled, priority is given to the SDRAM. Any access to addresses
higher than 0x60000000 is driven to SDRAM. No SRAM control is activated.
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AT697
SRAM Read Access
A read access to SRAM consists in two data cycles and between zero and three wait-
states. On non-consecutive accesses, a lead-out cycle is added after a read cycle to
prevent bus contention due to slow turn-off time of memories or I/O devices. On consec-
utive accesses, no lead-out cycle is performed between the acesses but only one is
performed at the end of the operations (RAMSN and RAMOE are not deasserted).
When a read access to SRAM is performed, a separate output enable signal is provided
for each SRAM bank and it is only asserted when that bank is selected.
Figure 10. SRAM read cycle (0-waitstate)
data1
data2
lead-out
CLK
A
A1
RAMS*
RAMOE*
D
D1
SRAM Write Access
Each byte lane has an individual write strobe (RAMWE*) to allow efficient byte and half-
word writes.
Each write access to SRAM consists of three cycles and between zero and three wait-
states. The three mandatory cycles are divided in one write setup cycle, one data cycle
and one lead-out cycle.
Figure 11. SRAM write cycle (0-waitstate)
lead-in
data
lead-out
CLK
A
A1
RAMS*
RWE*
D
D1
If the external memory use a common write strobe for the full 16- or 32-bit data, set the
read-modify-write bit MCFG2. This will enable read-modify-write cycles for sub-word
writes.
Waitstates
For application using slow SRAM memories, the SRAM controller provides the capability
to insert wait-states during the SRAM accesses. Two types of wait-states can be
inserted :
•
Programmed delay, available for bank 0 up to bank 3
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•
‘Hardware’ delay, available for bank 4 only
Up to three waitstates can be programmed for SRAM accesses. Read and write wait-
states can be individually programmed. Setting the RAMRWS value in MCFG2 register
defines the number of waitstates to insert during an SRAM read. Setting the RAMWWS
value in MCFG2 register defines the number of waitstates to insert during an SRAM
write.
Figure 12. RAM read access with one programmed waitstate
data2
waitstate
lead-out
data1
CLK
A
A1
RAMS*
OE*
D
D1
If the application needs more delay during the SRAM transfer, it is possible to introduce
more delay by activating the hardware bus ready ( BRDY* ) detection in MCFG2. If the
BRDY bit is driven logical one on MCFG2 and the BRDY* pin is set high, the processor
wait before ending the transfer. As soon as the BRDY* pin is driven low, the processor
ends the access. If the BRDY bit is driven logical zero on MCFG2, no additional delay is
inserted.
Figure 13. RAM read access with one BRDY* controlled waitstate
data2
waitstate
lead-out
data1
CLK
A
A1
RAMS*[4]
OE*
D
D1
BRDY*
Bus width
To support applications with low memory and performance requirements, the SRAM
area can be configured for 8-bit operations. The configuration of SRAM in 8-bit mode is
done programming the SRAM bus width field in he memory configuration registers
MCFG2.
When the SRAM bus is configured as an 8-bit wide bus, data 31 downto 24 shall be
used as interface.
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AT697
Figure 14. SRAM 8-bit bus width connection
A
D
A[27:0]
CS
OE
WE
RAMS0*
RAMOE0*
RWE0*
A
D
SRAM
D[31:24]
AT697
A[27:0]
D[31:24]
Since access to memory is always done on 32-bit word basis, read access to 8-bit mem-
ory will be transformed in a burst of four read cycles. If EDAC protection is active, 5 read
cycles are necessary to complete the access (please refer to “Error Management -
EDAC” on page 41 for more details). During write operation, only the necessary bytes
are writen.
In addition to the 8-bit mode, the SRAM area can be configured for 16-bit accesses. In
this configuration, the SRAM device is accessed with a burst of two 16-bit accesses. No
EDAC protection can be used with suh configuration.
When the bus is configured as an 16-bit wide bus, data 31 downto 16 shall be used as
interface.
Figure 15. SRAM 16-bit bus width connection
A
D
A[27:1]
CS
OE
WE
RAMS0*
RAMOE0*
RWE0*
A
D
SRAM
D[31:16]
AT697
A[27:0]
D[31:24]
Write Protection
Write protection is provided to prevent accidental over-writing to the RAM area. Two
block protection units are available for RAM area. Each one is controlled through a write
protection register (WPRn). Two major fields are defined : a TAG and a MASK.
•
The TAG defines the 15 most significant bits of the address of the block to be write
protected.
•
The Mask specifies which bits of the TAG are really relevant for the protection.
Operation
The write protection on the RAM area is enabled setting logical one the enable bit (EN)
in the write protect register (WPRn). If this bit is set logical zero, no protection is
activated.
Two protection modes can be programmed. If the block protect bit (BP) of the write pro-
tect register (WPRn) is set logical one the protection is active within the segment. If the
BP bit is set logical zero, the exterior of the segment is protected.
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4226G–AERO–05/09
Figure 16. RAM Protection Mode Overview
Write Æ trap
Write Æ trap
Segment 1
Segment 1
Write Æ trap
Write Æ trap
Segment 2
Segment 2
Write Æ trap
Segment mode (bp = 0)
Block mode (bp = 1)
To detect if the written address is part of a protected segment (or block), address bit 29
down to bit 2 are Xored with the TAG field from the write protect register. This operation
is based on the following segmentation of an address.
Table 14. Address Segmentation
bit num. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
field
area
most significant byte
32Kbyte protected block
With such segmentation, memory block in the range of 32Kbyte up to 1Gbyte can be
protected.
The result of the Xor is then Anded with the MASK field of the write protect register.
If the result is zero, this indicates that address specified is in the protected range. If
result is different from zero, address is out of the protected address range. If a write pro-
tection error is detected, the write cycle is stopped. Then, a memory access error is
generated. Trap 0x2B is generated
Figure 17. RAM Write Protection Overview
15
15
logic
15
15
Trap 0x2B
Write Protection Reg.
EN
WRPn
SDRAM
34
The synchronous dynamic RAM interface can manage up to two SDRAM banks. The
control of the SDRAM memory accesses uses a standard set of pin, including chip
selects (SDCS*x), write enable (SDWE*), data masks (SDDQM*x) and clock lines.
AT697E
4226G–AERO–05/09
AT697
The bank size of the two SDRAM banks can be configured by setting the value of the
SDRAM bank size field in MCFG2. The bank size can be programmed in binary step
from 4 Mbytes to 512 Mbytes.
The controller supports 64M, 256M and 512M devices with 8 to 12 column-address bits,
up to 13 row-address bits, and 4 banks. Only 32-bit data bus width is supported for
SDRAM banks.
Address Mapping
The start address for the SDRAM banks depends upon the SRAM use in the applica-
tion. If the the SRAM disable bit (SI) and the SDRAM enable bit (SE) are set logical one
in the memory configuration register (MCFG2), the SDRAM start address is
0x40000000. If the the SRAM disable bit (SI) is set logical zero and the SDRAM enable
bit (SE) is set logical one in the memory configuration register (MCFG2), the SDRAM
start address is 0x60000000. If SE if set logical zero, no SDRAM can be used.
The address bus of the SDRAMs shall be connected to A[14:2], the bank address to
A[16:15]. Devices with less than 13 address pins should only use the less significant bits
of A[14:2].
Figure 18. SDRAM connection overview
A
D
AT697
A[16:15]
A[14:2]
CLK
CSN
RAS
CAS
WE
SDCLK
SDCSN[1:0]
SDRAS*
SDCAS*
SDWE*
SDDQM[3:0]
BA
A
SDRAM
D
DQM
A[27:0]
D[31:0]
SDRAM Timing Parameters
To provide optimum access cycles for different SDRAM devices some SDRAM parame-
ters can be programmed through memory configuration register 2. The programmable
SDRAM parameters are the following :
Table 15. SDRAM Programmable Timing Parameters
Function
CAS latency
Parameter
Range
2 - 3
Unit
clocks
clocks
clocks
clocks
Precharge to activate
Auto-refresh command period
Auto-refresh interval
tRP
2 - 3
tRFC
3 - 11
10 - 32768
SDRAM Commands
The SDRAM controller can issue three SDRAM commands. Commands to be executed
are programmed through the SDRAM command field in the memory configuration regis-
ter (MCFG2). When this field is writen with a non zero value, a SDRAM command is
issued :
•
•
•
if set to ‘01’, Precharge command is sent,
if set to ‘10’, Auto-Refresh command is sent,
if set to ‘11’, Load Mode Reg (LMR) is sent.
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4226G–AERO–05/09
When the LMR command is issued, the CAS delay programmed in MCFG2 is used. The
command field is cleared after a command is executed. When changing the value of the
CAS delay, a LOAD-MODE-REGISTER command should be generated at the same
time.
The SDRAM controller also provides a refresh command. It can be enabled by setting
logical one the refresh enable bit (SDRREF) in the memory configuration register.
The Auto-Refresh command enables a periodical refresh for both SDRAM banks. The
period between two Auto-Refresh command is programmed in the refresh counter
reload field of the third memory configuration register (MCFG3).
Depending on SDRAM type, required period is typically 7.8 or 15.6μs. This corresponds
to 780 or 1560 clock cycle at 100MHz.
Reload value + 1
Refresh period is calculated as
--------------------------------------------
Refresh Period =
sysclk
SDRAM Initialisation
After reset, the SDRAM controller automatically performs the SDRAM initialisation
sequence. It consists in PRECHARGE, two AUTO-REFRESH cycles and LOAD-MODE-
REG on both banks simultaneously.
The controller programs the SDRAM to use page burst on read and single location
access on write. A CAS latency of 3 is programmed by default. This value can be
updated later by software.
SDRAM Read Access
SDRAM Write Access
Access Error
A read cycle consists in three main operation. First, an ACTIVATE command to the
desired bank and row is performed. Then, after the programmed CAS delay, a READ
command is sent. The read cycle is terminated with a PRE-CHARGE command. No
bank is left open between two accesses.
A burst read is performed if a burst access is requested on the internal bus.
A write cycles consists in three main operations. First, an ACTIVATE command to the
desired bank and row is performed. Then, a WRITE command is sent. The write cycle is
terminated with the PRE-CHARGE command.
A burst write on the internall bus generates a burst of write commands without idle
cycles in-between.
An access error can be indicated to the processor asserting the BEXC* signal. If
enabled by setting logical one the BEXC* bit in the memory configuration register 1, the
BEXC* signal is sampled with the data.
If the BEXC* signal is driven low by the external device during the access, an error
response is generated on the internal bus.
•
•
•
Trap 0x01 is taken if an instruction fetch is in progress
Trap 0x09 is taken if a data space is in progress
Trap 0x2B is taken if a data store is in progress
PROM Interface
Overview
The memory controller give the capability to control up to 512Mbyte of PROM. The
PROM interface can manage up to two PROM banks. The control of the PROM memory
accesses uses a standard set of pin, including chip selects (ROMS*x), output enable
(OE*), read (READ) and write (WRITE*) lines.
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AT697
The bank size of the PROM banks is not programmable. The lower half part of the
PROM area (0x00000000 up to 0x0FFFFFFF) is controlled by the ROMS0* PROM
select signal. The upper half part of the PROM area (0x10000000 up to 0x1FFFFFFF) is
controlled by the ROMS1* PROM select signal.
PROM Read Access
A read access to PROM consists in two data cycles and waitstates if any programmed.
On non-consecutive accesses, a lead-out cycle is added after a read cycle to prevent
bus contention due to slow turn-off time of memories or I/O devices. On consecutive
accesses, no lead-out cycle is performed between the acesses but only one is per-
formed at the end of the operations.
Figure 19. PROM Read Cycle (0 Waitstate)
data1
data2
lead-out
CLK
A
A1
ROMS*
OE*
D
D1
PROM Write Access
Each write access to PROM consists of three cycles and of waitstates if any pro-
grammed. The three mandatory cycles are divided in one write setup cycle, one data
cycle and one lead-out cycle. The write operation is strobed by the WRITE* signal.
Figure 20. PROM Write Cycle (0 waitstate)
lead-in
data
lead-out
CLK
A
A1
ROMS*
WRITE*
D
D1
Waitstates
For application using slow PROM memories, the PROM controller provides the capabil-
ity to insert wait-states during the accesses. Two types of wait-states can be inserted :
•
•
Programmed delay,
‘Hardware’ delay.
Up to 30 waitstates can be programmed for PROM accesses. Read and write waitstates
can be individually programmed. Setting the PRRWS value in MCFG1 register defines
the number of waitstates to insert during a PROM read access. Setting the PRWWS
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4226G–AERO–05/09
value in MCFG1 register defines the number of waitstates to insert during a PROM
write.
PRRWS and PRWWS field can be programmed to take values from 0 up to 15. The
effective number of waitstates applied during an access is then twice the programmed
value. In that way, programming two waitstates result in the insertion of four wait cycles
during the access.
If the application needs more delay during the PROM access, it is possible to introduce
more delay acting on the bus ready line ( BRDY* ). If the BRDY* pin is set high, the pro-
cessor wait before ending the transfer. As soon as the BRDY* pin is driven low, the
processor ends the access.
After a reset operation of the processor (or at power up), the read and write waitstates
fields for the PROM area are set default to 15, resulting in 30 effective waitstates.
Write Protection
Bus width
Write protection is provided to prevent accidental over-writing to PROM area. It is con-
trolled through the PROM write enable bit (PRWE*) from the memory configuration
register 1. When set 1, this bit enables write to PROM. When set 0, no PROM write
cycle is available.
To support applications with low memory and performance requirements, the PROM
area can be configured for 8-bit operations. The configuration of PROM in 8-bit mode is
done programming the ROM bus width field in he memory configuration registers
MCFG1.
When the PROM bus is configured as an 8-bit wide bus, data 31 downto 24 shall be
used as interface.
Figure 21. PROM 8-bit bus width connection
A
D
A[27:0]
CS
OE
WE
ROMS0*
OE*
WRITE*
PROM AD
D[31:24]
AT697
A[27:0]
D[31:24]
Since access to memory is always done on 32-bit word basis, read access to 8-bit mem-
ory will be transformed in a burst of four read cycles. If EDAC protection is active, 5 read
cycles are necessary to complete the access (please refer to protection section for more
details). During write operation, only the necessary bytes are writen.
In addition to the 8-bit mode, the PROM area can be configured for 16-bit accesses. In
this configuration, the PROM device is accessed with a burst of two 16-bit accesses. No
EDAC protection can be used with suh configuration.
When the bus is configured as an 16-bit wide bus, data 31 downto 16 shall be used as
interface.
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AT697E
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AT697
Figure 22. PROM 16-bit bus width connection
A
D
A[27:1]
CS
OE
WE
ROMS0*
OE*
WRITE*
A
D
PROM
D[31:16]
AT697
A[27:0]
D[31:16]
During power-up or reset operation, the PROM bus width field in MCFG1 is set with the
value of PIO[1:0] inputs.
Access Error
An access error can be indicated to the processor asserting the BEXC* signal. If
enabled by setting logical one the BEXC* bit in the memory configuration register 1, the
BEXC* signal is sampled with the data.
•
•
•
Trap 0x01 is taken if an instruction fetch is in progress
Trap 0x09 is taken if a data space is in progress
Trap 0x2B is taken if a data store is in progress
Memory Mapped I/O
Overview
The memory controller give the capability to control up to 256Mbyte of I/O. The I/O area
consists in a single large bank. The control of the I/O area accesses uses a standard set
of pin, including chip selects (IOS*x), output enable (OE*), read (READ) and write
(WRITE*) lines.
The size of the I/O bank is not programmable. The entire I/O area (0x20000000 up to
0x2FFFFFFF) is controlled by the IOS* select signal.
I/O Read Access
A read access to I/O consists in a lead-in cycle, two data cycles, waitstates if any pro-
grammed and a lead-out cycle. On non-consecutive accesses, the lead-out cycle is
used to prevent bus contention due to slow turn-off time of memories or I/O devices. On
consecutive accesses, no lead-out cycle is performed between the acesses but only
one is performed at the end of the operations.
The I/O select signal (IOSEL*) is delayed one clock to provide stable address.
Figure 23. single I/O read cycle with lead-out
data 2
lead-out
data 1
A1
lead-in
CLK
A
IOS*
OE*
D
D1
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Figure 24. consecutive I/O read cycles without lead-out
data 2
lead-out
data 2
data 1
A2
data 1
A1
lead-in
lead-in
CLK
A
IOS*
OE*
D
D2
D1
I/O Write Access
Waitstates
40
Each write access to I/O consists of three cycles and of waitstates if any programmed.
The three mandatory cycles are divided in one write setup cycle, one data cycle and one
lead-out cycle. The write operation is strobed by the WRITE* signal.
Figure 25. I/O write cycle
lead-in
data
lead-out
CLK
A
A1
IOS*
WRITE*
D
D1
For application using slow I/O devices, the I/O controller provides the capability to insert
wait-states during the accesses. Two types of wait-states can be inserted :
•
•
Programmed delay,
‘Hardware’ delay.
Up to 15 waitstates can be programmed for I/O accesses. Read and write waitstates are
programmed simultaneously. Setting the IOWS field value in MCFG1 register defines
the number of waitstates to insert during any access to/from I/O areas. IOWS field can
be programmed to take values from 0 up to 15.
If the application needs more delay during the I/O access, it is possible to introduce
more delay acting on the bus ready line ( BRDY* ). If the bus ready bit (BRDY*) is set
logical one in MCFG1 and BRDY* pin is set high, the processor wait before ending the
transfer. As soon as the BRDY* pin is driven low, the processor ends the access.
AT697E
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AT697
Write Protection
Bus width
Read and write protections are provided to prevent accidental accesses to I/O area.
Protection is controlled through the I/O protection ‘iop’ bit from the memory configuration
register 1.
To support applications with low memory and performance requirements, I/O area can
be configured for 8-bit operations. The configuration of I/O in 8-bit mode is done pro-
gramming the I/O bus width field in he memory configuration registers MCFG1.
In such configuration, I/O device is not accessed by multiple 8-bit accesses as other
memory areas. Only one single access is performed
When the I/O bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as
interface.
Figure 26. I/O 8-bit bus width connection
A
D
A[27:0]
CS
OE
WE
IOS*
OE*
WRITE*
A
D
IO
D[31:24]
AT697
A[27:0]
D[31:24]
In addition to the 8-bit mode, the I/O area can be configured for 16-bit accesses. In such
configuration, I/O device is not accessed by multiple 8-bit accesses as other memory
areas. Only one single access is performed.
When the bus is configured as an 16-bit wide bus, data 31 downto 16 shall be used as
interface.
Figure 27. I/O 16-bit bus width connection
A
D
A[27:0]
CS
OE
WE
IOS*
OE*
WRITE*
A
D
IO
D[31:16]
AT697
A[27:0]
D[31:16]
Access Error
An access error can be indicated to the processor asserting the BEXC* signal. If
enabled by setting logical one the BEXC* bit in the memory configuration register 1, the
BEXC* signal is sampled with the data.
•
•
•
Trap 0x01 is taken if an instruction fetch is in progress
Trap 0x09 is taken if a data space is in progress
Trap 0x2B is taken if a data store is in progress
Error Management -
EDAC
Overview
The AT697 processor implements an on-chip error detector and corrector (EDAC). The
on-chip memory EDAC can correct one error in a 32-bit word and detect two errors in a
32-bit word. The processor EDAC implemention enables data correction on-the-fly so
that no timing penalty occurs during correction.
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4226G–AERO–05/09
EDAC capability mapping
Data error management with the EDAC can be used on both PROM and RAM memory
areas. The following table presents the EDAC protection capabilities provided by the
processor.
Table 16. EDAC capability on Memories
Address Range
Area
EDAC Protected
0x00000000 - 0x1FFFFFFF
PROM
8 bits
16 bits
32 bits
All
yes
no
yes
no
0x20000000 - 0x3FFFFFFF
0x40000000 - 0x7FFFFFFF
I/O
RAM
8 bits
16 bits
32 bits
yes
no
yes
PROM protection
Setting logical one the PROM EDAC enable bit (PE) in the memory configuration regis-
ter MCFG3, the data protection is enabled. For each read and write cycle to the PROM
area the EDAC act as an error detector and an error corrector. When set logical zero,
the EDAC is transparent for the PROM access.
At power-on or at reset, the value of the PE bit is directly copied from the PIO2 pin. In
that way, it is possible to start the application with the EDAC enabled by driving high
PIO2 during the power-on sequence (or reset sequence).
RAM protection
Setting logical one the RAM EDAC enable bit (RE) in the memory configuration register
MCFG3, the data protection is enabled. For each read and write cycle to the RAM area
the EDAC act as an error detector and an error corrector. When set logical zero, the
EDAC is transparent for the RAM access.
Operation
The processor uses an EDAC based on a seven bit Hamming code that detects any
double error on a 32-bit bus and corrects any single error on a 32-bit bus.
Hamming code
For each 32-bit data, a seven bit a 7-bit checksum is generated. The equations below
show how the Hamming checkbits (CBx) are generated:
CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31
CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28
CB2 = D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31
CB3 = D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29
CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31
CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
Write operation
Read operation
When the processor performs a write operation to a memory protected by the EDAC, it
also output the seven bit checksum on the CB[6:0] pins.
During a read operation from a protected memory, the seven bit checksum is sampled
from the CB[6:0] inputs. Then, the EDAC verify the checksum to check the presence of
an error.
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AT697
According to the checksum equations, the EDAC calculates its own checksum. Then a
syndrome generator uses the calculated and the read checksum to qualify if there is no
error, one error or two errors in the read word.
Correctable error
If a single error is detected, this leads to a correctable error. The correction is done on-
the-fly during the current access and no timing penalty is induced. The read-modify-
write bit (RMW) in MCFG2 shall be set to enable write back of the corrected data.
The correctable error detection event is reported in the fail address register (FAILAR)
and in the fail status register (FAILSR). If unmasked, interrupt 1 (trap 0x11) is
generated.
Uncorrectable error
If a double error is detected, this leads to an un-correctable error. An un-correctable
error detection during a data access leads to a data access exception (trap 0x09). In
case the double error is detected during instruction fetch, it leads to an instruction
access error (trap 0x01).
Figure 28. EDAC overview
Memory Configuration Reg.
MCFG3
Fail Address Reg.
FAILAR
CB[7:0]
EDAC
Fail Status Reg.
FAILSR
EDAC on 8-bit areas
EDAC protection on a memory configured in 8-bit mode is also possible but, the EDAC
checksum bus (CB[7:0]) is not used. The protection is done by allocating the top 25% of
the memory bank to the EDAC checksums.
If the EDAC is enabled, a read access will read the data bytes from the nominal
address, and the EDAC checksum from the top part of the bank. A write cycle is per-
formed the same way. The memory assignement is then :
•
•
•
75% of the bank memory available as program or data memory,
18.75% used for checkbits
6.25% unused.
EDAC testing
The operation of the EDAC can be tested trough the MCFG3 memory configuration
register.
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Figure 29. EDAC testing overview
WB
8
Memory Configuration Reg.
TCB
MCFG3
CB[7:0]
8
EDAC
8
TCB
RB
Write test
Read test
If the write bypass bit (WB) from MCFG3 is set logical one, the value of the test check-
sum from the TCB field replaces the normal checkbits during memory write cycles.
During memory read cycles, if the read bypass bit (RB) from MCFG3 is set logical one,
the memory checkbits of the loaded data is stored to the test checkbit field (TCB) of
MCFG3 .
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AT697
Timer Unit
Prescaler
Timer/Counter1, Timer/Counter2 and the watchdog share the same prescaler.
The prescaler consists of a 10-bit down counter clocked by the system clock. The pres-
caler is decremented on each clock cycle. When the prescaler underflows, it is
automatically reloaded with the content of the prescaler reload register. A count tick is
generated for the two timers and the watchdog.
The effective division rate is equal to prescaler reload register value + 1.
Figure 30. Prescaler Block Diagram
Reload Reg.
count tick
SCAR
Control Logic
clock
load
Counter Reg.
SCAC
=0x3FF
Caution :
The two timers and watchdog share the same decrementer. The minimum allowed pres-
caler division factor is 4 (reload register = 3).
Timer/Counter 1 &
Timer/Counter 2
Timer/Counter1, Timer/Counter2 are two general purpose 24-bit timers. They share the
same decrementer. The timer value is then decremented each time the prescaler gener-
ates a timer pulse.
Each timer operation is controlled through a dedicated Timer Control register (TIMCTR).
A timer is enabled/disabled by setting the enable bit (en) in the timer control register.
Each time a timer underflows, an interrupt is generated. These interrupts can be
masked with the Interrupt Mask and Priority register (ITMP).
Setting the load bit (rl) in the Timer Control register, the content of the reload register
(TIMR) is automatically reloaded in the Timer Counter register (TIMC) after an under-
flow and the timer continue running. If the reload bit is reset, the timer stops running
after its first underflow.
Timer Counter can be forced with the Timer Reload value at any time by asserting the
load bit (ld) in the Timer Control register.
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4226G–AERO–05/09
Figure 31. Timer/Counter 1/2 Block Diagram
Control Reg.
TIMCTRn
Reload Reg.
TIMRn
timer interrupts
(irq 8 & 9)
Control Logic
count tick
load
Counter Reg.
TIMCn
enable/disable
=0xFFFFFF
Watchdog
The watchdog operates the same way as the timers, with the difference that it is always
enabled and upon underflow asserts the external signal WDOG. This signal can be used
to generate a system reset.
If the watchdog counter is refreshed by writing to WDG register before the counter reaches zero,
the counter restarts counting from the new value.
If the counter is not refreshed before the counter reaches zero, WDOG signal is asserted.
After reset, the watchdog is automatically enabled and starts running.
Note:
Reading wdc field of the watchdog register gives the loading (or re-loading) value, not
the effective count value.
Figure 32. Watchdog Block Diagram
WDOG
Watchdog Reg.
Control Logic
=0xFFFFFF
TIMRn
clock
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AT697
General Purpose
Interface
The general purpose interface (GPI) consists in a 32-bit wide I/O port with alternate
facilities.
GPI as 32-bit I/O port
The interface is based on bi-directional I/O ports.The port is split in two parts, with the
lower 16-bits accessible by the parallel IO pads and the upper 16-bits via the data bus.
lower 16-bits
The lower 16-bits of the general purpose interface are accessible through PIO[15:0]. All
I/O ports have true Read-Modify-Write functionality when used as general I/O ports.
This means that the direction of one port pin can be changed without unintentionally the
direction of any other pin. The same applies when changing the drive value of the port.
Figure 33. I/O port block diagram - PIO[15:0]
IO Direction Reg.
D
D
Q
Q
D
IODIR
PIOx
IO Data Reg.
IODAT
Q
clock
configuring the pin
Each pin from PIO[15:0] consists of two register bits : IODIRx and IODATx. As shown in
the “Register Description” section, the IODIRx bits are accessed at IODIR address and
iodatx at IODAT address.
The IODIRxbit in the IODIR register selects the direction for port number x. If IODIRx is
written logic one, the corresponding pin is configured as output. If written logic zero, the
pin is configured as an input.
When the pin is configured as an input, a read of the IODATx bit in IODAT register
returns the current value of the pin. When the pin is configured as an output, if a logical
one is written to IODATx bit in IODAT register, the port x is driven high. If a logical zero
is written to IODATx bit in IODAT register, the port x is driven low.
switching between input &
output
When the port x is switched from input to output by switching IODIRx, the value of
IODATx is immediatly driven on the corresponding pin.When switched from output to
input by toggling IODIRx, the value from the pin is immediatly written to IODATx.
upper 16-bits
The upper 16-bits of the general purpose interface are accessible through D[15:0]. They
can only be used when all memory areas (ROM, RAM and I/O) are 8-bit or 16-bit wide. If
the SDRAM controller is enabled, the upper 16-bits cannot be used.
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4226G–AERO–05/09
Figure 34. I/O port block diagram - D[15:0]
IO Direction Reg.
MEDDIR/LOWDIR
D
D
Q
Q
D
Dx
IO Data Reg.
MEDDAT/LOWDAT
Q
clock
configuring the pin
The upper 16 bits of the general purpose interface can only be configured as outputs or
inputs on byte basis. D[15:8] is referenced as the medium byte when D[7:0] is refer-
enced as the lower byte.
Each byte from D[15:0] consists of two register fields. As shown in the “Register
Description” section, the direction fields are accessed at IODIR address when data
fields at IODAT address.
The MEDDIR bit and the LOWDIR bit in the IODIR register select the direction for
respectively the medium byte ( D[15:8] ) and the lower byte ( D[7:0] ). If MEDDIR (or
LOWDIR) is written logic one, the corresponding byte in D[15:0] is configured as output.
If written logic zero, the byte is configured as an input.
When configured as an input, a read of the MEDDAT fileds in IODAT register returns the
current value of D[15:8]. When configured as an output, the logical value from MEDDAT
field in IODAT register is translated in physical values on D[15:8] bus.
When configured as an input, a read of the LOWDAT fileds in IODAT register returns the
current value of D[7:0]. When configured as an output, the logical value from LOWDAT
field in IODAT register is translated in physical values on D[7:0] bus.
switching between input &
output
When the medium byte (or the lower) is switched from input to output by switching MED-
DIR (or LOWDIR), the value of MEDDAT (or LOWDAT) is immediatly driven on the
corresponding pin. When switched from output to input by toggling MEDDIR (or
LOWDIR), the value from the pins are immediatly written to MEDDAT (or LOWDAT).
GPI Alternate functions
Most GPI pins have alternate functions in addition to being general I/O. Facilities like
serial communication link, interrupt input and configuration are made available through
these functions. The following table summaryses the assignement of the alternate
functions.
Table 17. GPI alternate functions
GPI port pin
PIO[15]
PIO[14]
PIO[13]
PIO[12]
PIO[11]
PIO[10]
PIO[9]
Alternate function
TXD1 - UART1 transmitter data
RXD1 - UART1 receiver data
RTS1 - UART1 request-to-send
CTS1 - UART1 clear-to-send
TXD2 - UART2 transmitter data
RXD2 - UART2 receiver data
RTS2 - UART2 request-to-send
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AT697
GPI port pin
PIO[8]
Alternate function
CTS2 - UART2 clear-to-send
PIO[3]
UART clock - Use as alternative UART clock
EDAC enable - Enable EDAC checking at reset
Prom width - Defines PROM bus width at reset
PIO[2]
PIO[1:0]
In addition to these alternate functions, each GPI interface pin can be configured as an
interrupt input to catch interrupt from external devices. Up to four interrupts can be con-
figured on the GPI interface by programming the I/O interrupt register (IOIT).
For a detailed description of the external interrupt configuration, please refer to the
“Traps and Interrupts” section.
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PCI Arbiter
A PCI arbiter is embedded on the AT697 chip. The¨PCI arbiter enables the arbitration of
4 PCI agents numbered from 3 downto 0. A round-robin algorithm is implemented as
arbitration policy. The PCI arbiter is totally independent from the PCI interface
Operation
An Agent on the PCI bus requests the bus by driving low its REQ* line. When the arbiter
determines that the bus can be granted to an agent, it drives low the corresponding
GNT* line.
When the bus is granted to a PCI agent, the agent keeps the bus for only one transac-
tion. If the agent desires more accesses, it shall continue to assert its REQ* line and
wait to be granted the bus again.
Round Robin
The round robin algorithm used for the arbitration is based on various loops with differ-
ent priority levels. The implementation in the AT697 is based on two priority loops. A
high priority loop is defined as level 0. A low priority loop is defined as level 1.
Operation
The arbitration is done checking the REQ* lines of the PCI agents one after each other.
In first place, the loop with level 0 is checked. If a a REQ* is active and no master is cur-
rently granted ther bus, the corresponding GNT* line is driven low. Then, the agent is
granted the bus. At each complete round-turn in level 0, one step is done in level 1. The
following figure illustrates the operation of the arbitre.
Figure 35. Arbitre operation - Agent
Agent 0 Agent 1
Agent 0 Agent 1
Agent 0 Agent 1
level 0
level 1
time
Agent 2
Agent 3
Agent 2
With : agents 0 and 1 at level 0
agents 2 and 3 at level 1
If all agents have a request at the same time, the following probabilities of access are
implemented:
•
•
All agents in one level have equal probability
All agents in level 1 together have the same probability of access as one agent in
level 0.
•
If no agent is in level 0, or no agent in level 0 has a request, all agents in level 1 are
granted with equal probability
Bus Parking
As long as no bus request is active on the arbiter, the bus is granted to the last owner. It
remains granted to the last owner until another agent requests the bus. When another
request is asserted, re-arbitration occurs after one turnover cycle.
After reset, the bus is parked to agent 0. Agent 0 is the default owner after a reset
operation.
Re-arbitration
When a master is managing a transfer and another one makes a request to the arbiter,
re-arbitration occurs. Only one re-arbitration is performed during a transfer. A new arbi-
tration will take place when the master which was granted the bus frees the bus. As long
as all the PCI agents have no request pending, the arbitration is performed. A re-arbitra-
tion cycle also occurs when living the bus parking state.
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AT697
Priority definition
Two different priority levels are defined for the PCI arbiter. Level 0 is defined as the high
priority level. Level 1 defines the low priority level. Assignment of the PCI agents priority
level is programmable through the arbiter configuration register (ACR).
Each PCI agent can be individually configured to operate either on level 0 or on level 1,
except agent 3 that is defined by hardware with a low priority (level 1).
Setting logical one the Px bit in the arbiter configuration register leads the agents x to a
low priority level. Setting this bit logical zero leads to a high priority.
After reset, all the PCI agents are configured in the low priority loop.
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PCI Interface
Overview
The PCI interface implementation is compliant with the PCI 2.2 specification. It is a high
performance 32-bit bus interface with multiplexed address and data lines. It is intended
for use as an interconnect mechanism between processor/memory systems and periph-
eral controller components.
The AT697 processor embedds the In-Silicon PCI core. It is interfaced to the processor
core through the PCI to AMBA bridge developped by the European Space Agency.
The PCI bus operations can be clocked at a frequency up to 33MHz, independently of
the processor clock. Synchronization of the operation between PCI interface and AT697
core implies numerous FIFO usage. This implementation allows to use the device for
Initiator (Master) and Target operations. In each mode single word and burst transfer
can be executed.
Two different operating modes can be used with the PCI interface :
•
Host Bridge
The host-bridge connects the local bus of a processor to the PCI bus. Its PCI
configuration registers are accessible locally by the processor, but not through PCI
configuration cycles. Host-bridge initialises other satellite devices through PCI
configuration commands.
•
Sattelite
The satellite is a PCI device, configurable via PCI configuration cycles and the idsel
line, but not locally.
Both, host-bridge and satellites can be initiator and/or target on the bus. The present
interface has universal functionality, allowing both operation modes. The mode is config-
ured via an hardware bootstrap on the SYSEN* pin.
Some other features are supported by this interface like
•
•
•
•
•
•
•
Target lock support
Zero-latency Fast Back-to-Back transfers
Zero wait state burst mode transfers
Support for memory read line/multiple
Support for memory write and invalidate commands
Delayed read support
Flexible error reporting by polling
The PCI bus is a multiplexed one. In this way, address and data through the same
medium. That is why PCI communication is based on two phase burst transfer. Each
transfer is composed of the following phases :
•
An address phase
During the address phase, the initiator of the communication drives the 32-bit
address concerned by the transfer and the command involved through this transfer.
The command defines the space area concerned with the transfer and the direction
of the transfer.
•
A data phase
During the data phase the initiator of the communication drives the enable bit signal
so that only active part of the bus is enabled. When reading, the initiator drives the
enable bits and the target set the data on the bus.
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AT697
PCI Initiator (Master)
The PCI initiator mode of the AT697 gives a direct memory-mapped (initiator) access to
the PCI bus. Any access to a memory address in the PCI address range is automatically
translated by the interface into the appropriate PCI transaction. In this configuration, the
PCI bus is accessed by the same instructions as the main memory. The SPARC instruc-
tion set foresees various load/store instruction types. The PCI bus foresees 32 bit wide
transactions with byte-enables for each byte lane.
Initiator Mapping
For standard operation, the PCI interface only works in a limited address range. The
address range for such initiator transaction is limited to addresses between 0xA0000000
and 0xF0000000.
PCI addresses outside of this predefined range can be accessed only via DMA
transactions.
Instructions of different width (byte, half-word, word, double) can be performed for each
address of the PCI address range. The three low significant bits of the address A[2:0]
are used to determine which PCI byte enable line C/BE*[3:0] should be active during the
transaction.
According to the SPARC architecture, big-endian mapping is implemented, the most
significant byte standing at the lower address (0x..00) and the least significant byte
standing to the upper address (0x..03).
A byte-writing to A[1:0] = 00 results in the byte enable pattern 0111, indicating that the e
most significant byte lane (bits 31:24) of the PCI data bus is selected.
The following table presents the transaction width authorized for PCI transfers.
Table 18. Byte Enable Settings
width
8
ld[s/u]b, stb
char
16
32
64
Assembler
C-datatype
A[2:0]=000
A[2:0]=100
A[2:0]=x01
A[2:0]=x10
A[2:0]=x11
ld[s/u]h, sth
short
ld, st
ldd, std
int
long long
0000 (burst)
not aligned
not aligned
not aligned
not aligned
0111
0011
0000
0111
0011
0000
1011
not aligned
1100
not aligned
not aligned
not aligned
1101
1110
not aligned
Note:
PCI byte enables are active low.
For non-aligned accesses, the byte enable pattern (1111) is issued on PCI, to avoid
destroying data in the remote PCI target.
Memory cycles
Many memory cycles such as memory-read/write and memory-read-line/write-invalidate
can be issued from the processor with common SPARC instruction set. Selection of the
command to execute is performed setting the value of the command field (CMD) in the
PCI initiator configuration (PCIIC).
Setting logical ‘01’ the CMD field result in the generation of memory read/write access
when PCI address is accessed. A logical value of ‘10’ result in a memory read line or
write and invalidate on PCI address access.
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For the memory commands the address issued on the PCI bus is a word address with
bits (1:0) set to 00. This indicates that the linear incrementing mode is used.
operation
The following procedure shall be used to engage memory cycle on the PCI interface:
1. Select the initiator mode by setting logical one the MOD bit in the PCI initiator
configuration register.
2. Select the memory load/store command or the memory read-line/write and inval-
idate command in the PCI initiator configuration register. The CMD field shall be
set logical ‘01’ for simple load/store operation and shall be set logical ’11’ for
read-line/write-&-invalidate.
3. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical
one the initiator error bits in the PCI interrupt enable register (PCIITE). Up to four
interrupt sources can be defined : Initiator Error, Initiator Parity Error, PCI core
error and system error.
4. Engage an access to a memory address mapped in the PCI address range.
IO transaction cycles
operation
The following procedure shall be used to engage I/O cycle on the PCI interface:
1. Select the initiator mode by setting logical one the MOD bit in the PCI initiator
configuration register.
2. Select the I/O load/store command in the PCI initiator configuration register. The
CMD field shall be set logical ‘00’ for I/O operation.
3. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical
one the initiator error bits in the PCI interrupt enable register (PCIITE). Up to four
interrupt sources can be defined : Initiator Error, Initiator Parity Error, PCI core
error and system error.
4. Engage an access to an I/O address mapped in the PCI address range.
Configuration cycles
Target selection
Accesses to a configuration address space requires the target device to be selected.
Due to the address range limitation, the chip-select (IDSEL) connection necessary for
device selection shall be done using only A/D[27:16]. This allows up to 12 PCI devices
to be connected on the bus.
Devices with chip-select line connected to A/D[31:28] can’t be configured through stan-
dard operations. DMA configuration cycles shall be used to configure the devices
connected to A/D[31:28].
The PCI bus configuration cycles can be performed using the same instructions as the
main memory. To generate such configuration cycle with the standard instructions, the
command type field (COMMSB) of the PCI initiator configuration register (PCIIC) shall
be programmed to ‘01’.
Then, if a load (or store) cycle is performed to an addresss in the PCI address range, a
physical configuration cycle is performed on the PCI bus. The full 32-bit address defined
on the internal bus is propagated on the PCI bus. Once a target is selected (DEVSEL*
asserted).
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Operation
The following procedure shall be used to engage configuration cycle on the PCI
interface:
1. Select the initiator mode by setting logical one the MOD bit in the PCI initiator
configuration register.
2. Select the configuration load/store command in the PCI initiator configuration
register. The CMD field shall be set logical ‘10’ for configuration operation.
3. Enabling the interrupt signalisation is optionnal. It can be enabled setting logical
one the initiator error bits in the PCI interrupt enable register (PCIITE). Up to four
interrupt sources can be defined : Initiator Error, Initiator Parity Error, PCI core
error and system error.
4. Engage an access to an configuration space.
Limitation
Configuration cycles shall only be generated by the PCI host of the bus or by a PCI-to-
PCI bridges.
Special cycles
By default, all requests are translated into single cycle PCI transactions, each transac-
tion consisting in an address phase followed by a single data phase.
Linear incrementing store-word
Linear incrementing store-word sequences are translated into undetermined length PCI
write bursts with up to a maximum of 255 words. The PCI burst mode is then maintained
as long as possible. Read/write direction is unchanged and the address An+1 = An + 4.
When the sequence is discontinued, the PCI burst stops with a last data phase during
which byte enables are 1111.
Double word load/store
Double word load/store requests can be executed as a two word bursts, the burst (one
address phase, two data phases) on PCI.
A double word read is executed as a two word burst when the DWR bit is set logical one
in the PCI initiator configuration register. When set logical zero, a double word read is
translated to the PCI as two single read accesses.
A double word write is executed as a two word burst when the DWW bit is set logical
one in the PCI initiator configuration register. When set logical zero, a double word write
is translated to the PCI as a burst of undefined length as long as the addresses are
sequential.
The double word mode accelerates the transfer on the PCI side except in cases, where
linear incrementing bursts are done by subsequent storedouble instructions (An+1 = An +
8). In this case the double word write bit DWW shall be set logical zero.
It is in general recommended to set logical one both DWR and DWW and to use the
DMA to transfer large data blocks.
Fast back2back cycles
The PCI implementation only supports fast back2back cycles to the same target. Before
using fast back-2-back transfers, fast back-2-back cycles shall be enabled setting logical
one the bit COM9 in the status command register (PCISC). Bit COM9 shall only be set
one if all targets on the bus support fast back-2-back transfers.
Issuing a fast back to back transfer is done setting logical one the B2B bit in the
PCIDMA register.
Note:
Fast back-2-back can only be generated by the initiator. It is not accepted by the AT697
PCI target.
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Error reporting
Fatal (abort) and address parity On a fatal error ( or address parity error ), the interface flushes all the current buffer
errors
requests and all other buffer requests. Then, the interface reports the fatal error driven
logical one the pci core error (CMFER) in the PCi interrupt pending register.
The PCI core is restarted as soon as a new request is engaged.
Data parity errors
During load/read transactions, one PCI parity error is recoverable in hardware. If the
PERR bit is set in the PCI initiator configuration register, the interface ignores the erro-
neous PCI data and retries the request.
However, if the data parity error persists at the same address, it is considered to be
unrecoverable. Then, an error on the internal bus is detected and the PCI initiator error
is reported in the IMIER bit of the PCI interrupt pending register.
Parity error is also impossible in cases where the transaction is already finished on the
local bus when the error is detected/reported on the PCI bus. The parity error is then
reported in the initiator parity error bit (IMPER) and error recovery must be done in
software.
DMA transfer
A DMA facility is available on the AT697 processor. The DMA transfer are performed
through the PCI interface. The DMA controller executes data transfer between the local
memory and a remote target on the PCI bus.
The processor core only intervenes for the initiation of the transfer. Once transfer is initi-
ated, DMA controller is fully autonomous. DMA transfers take place in background of the
processor core activity. Thus, interrupts are provided to help to synchronise the applica-
tion with start and end of the transfer.
The DMA interface executes only word-size transactions with all 4 byte lanes enabled.
Operation
The DMA is enabled setting logical one the MOD bit in the PCI initiator configuration
register (PCIIC). To synchronize the application with the start and the end of the trans-
action, two interrupts can be enabled : DMAER for transfer control and IMIER for error
control.
Each DMA sequence shall program the following parameters :
•
•
•
•
PCI start address
PCI command type
number of words to be transferred
the start address in the local memory
A DMA transfer is performed assuming the following operations are done in the given
order :
1. Write the PCI start address of burst to the PCI start address register (PCISA).
The PCISA register shall be re-writen each time a DMA transfer is initiated, even
if the address is identical to the address of the previous DMA request.
2. Write together the PCI command and the number of words to be transfered in
the PCI DMA configuration register (PCIDMA).
Writing to the PCIDMA passes the PCI address, the word count and the PCI
command to the PCI core and initiates the transaction on the PCI bus.
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3. Write the start address in the local memory map to the PCI DMA address regis-
ter (PCIDMAA).
Once the three operation are executed, data transfer is started in background. Once the
specified number of words is transfered, the interface set logical one the dma end of
transfer bit (DMAER) and generate an interrupt if enabled. Then DMA controller goes
back to idle state.
Error Reporting
If the PCI core does not accept the DMA cycle request, the DMA state controller
remains locked and an error is reported as initiator error with the IMIER bit set logical
one. If the request on the PCI core was just delayed, rewriting PCIDMAA may succeed.
If the problem persists, reset the interface by writing –1 (0xFFFFFFFF) to PCIIC.
Transfer Limitation
A DMA transaction may never cross a 1 KByte border. The value represented by PCID-
MAA(9:2) + PCIDMA(7:0) must be less than 256. If this restriction is not respected, the
data transfer stops at the 1 kByte border. Then the PCI core is flushed. Simultaneously,
in the PCI interrupt pending register (PCIITP) the dma error bit (DMAER) and the initia-
tor error bit (IMIER) are asserted logical one.
If enabled with the PCI interrupr enable register (PCIITE) and unmasked in the general
interrupt mask register, the PCI interrupt 14 is generated (TT = 0x1E).
Debug Facilities
Not implemented for application use.
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Target Mode Transfer
In the target mode, the PCI interface receives requests originated from remote PCI initi-
ators (masters). Target data transfer is executed in background without AT697 core
intervention. AT697 core can only intervenes is the configuration of the target.
•
•
In host bridge mode the target is configured by the AT697 core
In satellite mode the configuration is done by a remote device using the PCI
command set
Target Programming
The target is configured through the following registers :
•
PCISC register
bits 0/1 for memory and I/O command response
bit 6 for check of data and address parity error
bit 7 for response to data and address parity error
•
base address registers
memory base address : MEMBAR1, MEMBAR2
I/O base address : IOBAR
•
•
PCITPA register to indicate the storage location
PCITSC(7) bit to write data in memory
transaction Ordering
As specified in the PCI standard, delayed read functionality is implemented, obeying to
the following rules:
•
The interface stores one delayed read at a time. When a read request was retried
(because local data not yet available), the interface remains locked for any other
target read (targeting different addresses). The initiator of the original read has to
repeat its request to the same address.
•
•
A retried (delayed) read can be interrupted by one or more PCI write accesses. The
PCI standard requires this write command to be processed first, to prevent a system
lock-up.
Meanwhile, the interface will prefetch read-data into the TXMT FIFO. After the
(interfering) write, when the read request is repeated, and the requested data is
available in the FIFO the delayed transfer completes normally.
All target read accesses are generally prefetching, also reads with I/O command. Once
a start address is given, the interface prefetches up to 8 words into the TXMT FIFO.
After the last required data word was transferred to PCI, the PCI core automatically
flushes the FIFO to discard the unused prefetched data. The interface assumes the
complete local address space to be ‘prefetchable’, defined here as the fact, that reading
from an address does not alter the data. This behaviour is to be considered if non-
prefetchable devices (for example the UART’s) shall be read through the PCI target.
PCI Error Reporting
According to the PCI standard error and status are implemented in the PCI status regis-
ter. The PCI standard foresees a single parity check, by which bus-errors can be
detected, but not corrected.
•
•
Read data parity errors can eventually be retried by the hardware.
In other cases, recovery must be done in software.
Therefore, events, which occur in the PCI interface or on the PCI bus, are saved in sta-
tus bits, and optionally, the PCI interrupt (IRQ14) is asserted.
Different events can be selected to assert the interrupt. By the interrupt enable register
(PCIITE) configuration you can select the interrupt events which will assert IRQ14. then
an interrupt handler can read the interrupting event in the status register (PCIITP).
Furthermore, interrupts can be forced for test purposes by writing to PCIITF.
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In host-bridge configuration, this allows an error detection by polling. Certain events and
errors are also reported by the interface in the interrupt status register. For each bit of
this register , interrupt generation can be programmed individualy. All PCI interrupt gen-
erated are then reported to AT697 core through the PCI interrupt (IT14). The different
interrupt causes are distinguished by the interrupt status registers settings.
Please refer to the register description chapter for more details on interrupt status
register.
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UARTs (UART1 and
UART2)
The Universal Asynchronous Receiver and Transmitter (UART) is a highly flexible serial
communication module. The AT697 implements two uarts : UART1 and UART2. Uarts
on the processor are defined as alternate functions of the general purpose interface
(GPI).
Overview
The two UART’s provide double buffering. Each UART consists of a transmitter holding
register, a receiver holding register, a transmitter shift register, and a receiver shift regis-
ter. Each of these registers are 8-bit wide.
Figure 36. UART Block Diagram
Uart Scaler Reg.
Uart Control Reg.
Uart Status Reg.
UASCAn
UASn
UACn
CTS
RTS
Baud-rate
generator
control logic
RX
Receiver Shift Register
Transmitter Shift Register
TX
Receiver Holding Register
Transmitter Holding Register
Uart Data Reg.
UADn
Each UART is fully controlled by a set of four registers including :
•
•
•
•
a control register
a status register
a scaler register
and a data register
Serial Frame
A serial frame is defined to be one character of data bits with synchronisation bits (start
and stop bits), and optionnaly a parity bit for error checking.
Frame formats
Two frame formats are accepted by the AT697 UARTs, the only difference being the
presence or the absence of the parity bit. All the frames are built on an eight data bits
basis.
A frame starts with the synchronization start bit followed by the least significant data bit.
Then the next data bits, up to a total of eight, are succeeding, ending with the most sig-
nificant bit. If enabled by setting the PE bit in the uart control register (UCRx), the parity
bit is inserted after the data bits and before the stop bit.
The following figure illustrates the accepted frame formats.
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AT697
Figure 37. Data frame format
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
Data frame, no parity:
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Data frame with parity:
Parity bit
The parity bit is calculated by doing an exclusive-or of all the data bits. The odd parity is config-
ured setting logical one the PS bit in the uart control register (UACn). In this case, the result of
the exclusive or is inverted. An even parity can be selected setting logical zero the PS bit.
If used, the parity bit is located between the last data bit and the stop bit of the serial frame.
The relation between the parity bit and data bits is as follows:
P
= d ⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0
even
7 3 2 1 0
P
= d ⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1
7 3 2 1 0
odd
Peven
Podd
dn
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
Clock Generation
The clock generation logic generates the base clock for the Transmitters and Receivers. The bit
rate of the UART is issued from the clock generator after a combination between the input clock
of the clock module and a scaler.
Uart Clock
Two clock inputs can be used by the clock generator :
•
•
An internal clock
An external clock
Each UART can be configured to use either the internal or the external clock source by
programming the EC bit in the uart control register (UACn). If set logical zero, the UART
is clocked by the internal clock. If EC is set logical one, the UART is clocked by the
external clock. When using the external configuration, the UART clock shall be provided
by PIO[3] from the general purpose interface. This clock input is used as an alternate
function for PIO[3].
caution :
When using the external clock source, the frequency of PIO[3] must be less than half the
frequency of the system clock.
Baud Rate Generation
To generate the bit-rate, each UART has a programmable 12-bits clock divider (UAS-
CAn). According to the configuration of the EC bit in the uart control register, the scaler
is clocked either by the system or by an external clock.
Each time the scaler underflows, a UART tick is generated. The scaler is automatically
reloaded with the value of the UART scaler register after each underflow. The resulting
UART tick frequency should be 8 times the desired baud-rate.
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The following equation shall be used to calculate the scaler value to define, depending
on the clock source and the expected baud rate.
uartclk × 10
---------------------------------
– 5
baudrate × 8
------------------------------------------
scaler =
10
variable description :
•
•
•
uartclk : frequency of the uart clock
baudrate : expected baud rate
scaler : value to set in UASCAn to reach the expected baudrate
Communication
Operations
UARTS operations are controlled through the uart control registers (UACn) and the Uart
status registers (UASn).
Transmitter Operation
The transmitter is enabled setting logical one the TE bit in the UART control register.
When ready to transmit, data is transferred from the transmitter holding register to the
transmitter shift register and converted to a serial frame on the transmitter serial output
pin (TX).
Following the transmission of the stop bit, if a new character is not available in the trans-
mitter holding register, the transmitter serial data output remains high and the
transmitter shift register empty bit (TS) in the UART status register is set logical one.
Transmission resumes and the TS bit is cleared when a new character is loaded in the
transmitter holding register.
If the transmitter is disabled, it will continue operating until the character currently being
transmitted is completely sent out. The transmitter holding register cannot be loaded
when the transmitter is disabled.
If flow control is enabled, the CTS input must be low in order for the character to be
transmitted. If it is deasserted in the middle of a transmission, the character in the shift
register is transmitted and the transmitter serial output then remains inactive until CTS is
asserted again. If the CTS is connected to a receivers RTS, overrun can effectively be
prevented.
Receiver Operation
The receiver is enabled for data reception when the receiver enable bit (RE) in the
UART control register is set logical one. The receiver looks for a high to low transition of
a start bit on the receiver serial data input pin. If a transition is detected, the state of the
serial input is sampled a half bit clocks later. If the serial input is sampled high the start
bit is invalid and the search for a valid start bit continues. If the serial input is still low, a
valid start bit is assumed and the receiver continues to sample the serial input at one bit
time intervals until the proper number of data bits and the parity bit have been assem-
bled and one stop bit has been detected. During this process the least significant bit is
received first.
The serial input is sampled three times for each bit and averaged to filter out noise.
The data is then transferred to the receiver holding register and the data ready bit (DR)
is set logical one in the UART status register. The parity, framing and overrun error bits
are set at the received byte boundary, at the same time as the receiver ready bit is set.
If both receiver holding and shift registers contain an un-read character when a new
start bit is detected, then the character held in the receiver shift register will be lost and
the overrun bit (OV) is set logical one in the UART status register.
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If flow control is enabled, then the RTS will be negated (high) when a valid start bit is
detected and the receiver holding register contains an un-read character. When the
holding register is read, the RTS will automatically be reasserted again.
A correctly received byte is indicated by the data ready bit (DR) in the UART status reg-
ister (UASn). In case of error (framing error, stop bit error,...), the respective bits FE, PE,
... are set logical one in the UART status register when the data ready bit remains logical
zero.
Interrupt Generation
The two UARTs can be configured to generate interrupt each time a byte is received or
a byte is sent.
If the TI bit in the UART control register is set logical one, an interrupt is issued after
each character sending. If set logical zero, no interrupt is issued on character sending.
If the RI bit in the UART control register is set logical one, an interrupt is issued after
each character reception. If set logical zero, no interrupt is issued after a character
reception.
If the receiver interrupt is enabled, when error is detected during the reception of a char-
acter,an interrupt is generated. To identify the origin of the transaction failure, refer to
the uart status register bits (OV, PE, TE) that indicate either it is a parity, a framing or an
overrun error.
Loop back mode
If the LB bit in the UART control register is set, the UART will be in loop back mode. In
this mode, the transmitter output is internally connected to the receiver input and the
RTS is connected to the CTS. It is then possible to perform loop back tests to verify
operation of receiver, transmitter and associated software routines. In this mode, the
outputs remain in the inactive state, in order to avoid sending out data.
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Debug Support Unit - DSU
Overview
The AT697 processor includes an hardware debug support unit to aid software debug-
ging on target hardware. The support is provided through two modules: a debug support
unit (DSU) and a debug communication link (DCL).
The DSU can put the processor in debug mode, allowing read/write access to all pro-
cessor registers and cache memories. The DSU also contains a trace buffer which
stores executed instructions or data transfers on the internal bus. The debug communi-
cations link implements a simple read/write protocol and uses standard asynchronous
UART communications.
Figure 38. Debug Support Unit and Communication Link
AT697 processor
Trace
Buffer
AT697 SPARC V8
Integer unit
Debug I/F
DSUEN
DSUBRE
DSUACT
Debug
Support Unit
I-Cache D-Cache
AHB interface
AMBA AHB
Debug
Comm. Link
DSUTX
DSURX
It is possible to debug the processor through any master on the internal bus. The PCI
interface is build in as a master on the internal bus. All debug features are available from
any PCI master.
Debug Support Unit
The debug support unit is used to control the trace buffer and the processor debug
mode. The DSU master occupies a 2 Mbyte address space on the internal bus. Through
this address space, any other masters like PCI can access the processor registers and
the contents of the trace buffer.
The DSU control registers can be accessed at any time, while the processor registers
and caches can only be accessed when the processor has entered debug mode. The
trace buffer can be accessed only when tracing is disabled or completed. In debug
mode, the processor pipeline is held and the processor is controlled by the DSU. Enter-
ing the debug mode can occur on the following events:
•
•
•
•
•
•
•
executing a breakpoint instruction (ta 1)
integer unit hardware breakpoint/watchpoint hit (trap 0x0B)
rising edge of the external break signal (DSUBRE)
setting the break-now (BN) bit in the DSU control register
a trap that would cause the processor to enter error mode
occurrence of any, or a selection of traps as defined in the DSU control register
after a single-step operation
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•
DSU breakpoint hit
The debug mode can only be entered when the debug support unit is enabled through
an external pin (DSUEN). Driving the DSUEN pin high enables the debug mode. When
the debug mode is entered, the following actions are taken:
•
•
•
PC and nPC are saved in temporary registers (accessible by the debug unit)
an output signal (DSUACT) is asserted to indicate the debug state
the timer unit is (optionally) stopped to freeze the AT697 timers and watchdog
The instruction that caused the processor to enter debug mode is not executed, and the
processor state is kept unmodified. Execution is resumed by clearing the BN bit in the
DSU control register or by de-asserting DSUEN. The timer unit will be re-enabled and
execution will continue from the saved PC and nPC. Debug mode can also be entered
after the processor has entered error mode, for instance when an application has termi-
nated and halted the processor. The error mode can be reset and the processor
restarted at any address.
DSU Breakpoint
The DSU contains two breakpoint registers for matching either internal bus addresses
or executed processor instructions. A breakpoint hit is typically used to freeze the trace
buffer, but can also put the processor in debug mode.
Freeze operation can be delayed by programming the TDELAY field in the DSU control
register to a non-zero value. In this case, the TDELAY value will be decremented for
each additional trace until it reaches zero, after which the trace buffer is frozen. If the
brake on trace freeze bit (BT) is set logical one in the DSU control register, the DSU
forces the processor into debug mode when the trace buffer is frozen.
Note:
Due to pipeline delays, up to 4 additional instruction can be executed before the proces-
sor is placed in debug mode.
A mask register is associated with each breakpoint, allowing breaking on a block of
addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared
during breakpoint detection.
Time Tag
The DSU implements a time tag counter. This counter is decremented each clock as
long as the processor is running. The counter is stopped when the processor enters
debug mode. It is restarted when execution is resumed.
This time tag counter is stored in the trace as an execution time reference.
Trace Buffer
The trace buffer consists of a circular buffer that stores the executed instructions or the
internal bus data transfers. The size of the trace buffer is 512 lines of 16 bytes. The
trace buffer operation is controlled through the DSU control register (DSUC) and the
trace buffer control register (TBC). When the processor enters debug mode, tracing is
suspended.
The trace buffer can contain the executed instructions, the transfers on the internal bus
or both (mixed-mode). The trace buffer control register (TBC) contains two counters
(BCNT ans ICNT) that store the address of the trace buffer location that will be written
on next trace. Since the buffer is circular, it actually points to the oldest entry in the buf-
fer. The indexes are automatically incremented after each stored trace entry.
Instruction trace
The instruction trace mode is enabled setting logical one the trace instruction enable bit
(TI) in the trace buffer control register (TBC).
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During instruction tracing, one instruction is stored per line in the trace buffer with the
exception of multi-cycle instructions. Multi-cycle instructions can be entered two or three
times in the trace buffer :
•
For store instructions, bits [63:32] correspond to the store address on the first entry
and to the stored data on the second entry (and third in case of STD). Bit 126 is set
logical one on the second and third entry to indicate this.
•
•
•
A double load (LDD) is entered twice in the trace buffer, with bits [63:32] containing
the loaded data.
Multiply and divide instructions are entered twice, but only the last entry contains the
result. Bit 126 is set for the second entry.
For FPU operation producing a double-precision result, the first entry puts the MSB
32 bits of the results in bit [63:32] while the second entry puts the LSB 32 bits in this
field.
Table 19. Trace buffer data allocation, Instruction tracing mode
Bits
Name
Definition
127
Instruction breakpoint hit
Set to ‘1’ if a DSU instruction breakpoint hit occurred.
Set to ‘1’ on the second and third instance of a multi-cycle
instruction (LDD, ST or FPOP)
126
Multi-cycle instruction
125:96 DSU counter
The value of the DSU counter
95:64
63:34
Load/Store parameters
Instruction result, Store address or Store data
Program counter (2 lsb bits removed since they are always
zero)
Program counter
33
Instruction trap
Processor error mode
Opcode
Set to ‘1’ if traced instruction trapped
Set to ‘1’ if the traced instruction caused processor error mode
Instruction opcode
32
31:0
When a trace is frozen, interrupt 11 is generated.
Bus Trace
The bus trace mode is enabled setting logical one the trace instruction enable bit (TA) in
the trace buffer control register (TBC).
During bus tracing, one operation of the internal bus is stored per line in the trace buffer.
Table 20. Trace Buffer Data Allocation, Internal bus Tracing Mode
Bits
127
126
Name
Definition
AHB breakpoint hit
-
Set to ‘1’ if a DSU AHB breakpoint hit occurred.
Unused
125:96 DSU counter
95:92 IRL
The value of the DSU counter
Processor interrupt request input
Processor interrupt level (psr.pil)
Processor trap type (psr.tt)
91:88 PIL
95:80 Trap type
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AT697
Bits
Name
Definition
79
Hwrite
AHB HWRITE
AHB HTRANS
AHB HSIZE
78:77 Htrans
76:74 Hsize
73:71 Hburst
70:67 Hmaster
AHB HBURST
AHB HMASTER
AHB HMASTLOCK
AHB HRESP
66
Hmastlock
65:64 Hresp
63:32 Load/Store data
31:0 Load/Store address
AHB HRDATA or HWDATA
AHB HADDR
Mixed Trace
In mixed mode, the buffer is divided on two halves, with instructions stored in the lower
half and bus transfers in the upper half. The MSB bit of the AHB index counter is then
automatically kept high, while the MSB of the instruction index counter is kept low.
DSU Memory Map
Table 21. DSU Map
Address
Register
0x800000c4
0x800000c8
0x800000cc
0x90000000
0x90000004
0x90000008
0x90000010
0x90000014
0x90000018
0x9000001C
0x90010000 - 0x90020000
..0
DSU UART status register
DSU UART control register
DSU UART scaler register
DSU control register
Trace buffer control register
Time tag counter
AHB break address 1
AHB mask 1
AHB break address 2
AHB mask 2
Trace buffer
Trace bits 127 - 96
Trace bits 95 - 64
Trace bits 63 - 32
Trace bits 31 - 0
...4
...8
...C
0x90020000 - 0x90040000
0x90080000 - 0x90100000
0x90080000
0x90080004
IU/FPU register file
IU special purpose registers
Y register
PSR register
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Address
Register
0x90080008
WIM register
0x9008000C
TBR register
0x90080010
PC register
0x90080014
NPC register
0x90080018
FSR register
0x9008001C
DSU trap register
ASR16 - ASR31 (when implemented)
Instruction cache tags
Instruction cache data
Data cache tags
Data cache data
0x90080040 - 0x9008007C
0x90100000 - 0x90140000
0x90140000 - 0x90180000
0x90180000 - 0x901C0000
0x901C0000 - 0x90200000
The addresses of the IU/FPU registersis defined according to how many register win-
dows has been implemented. The registers can be accessed at the following addresses
(NWINDOWS = number of SPARC register windows = 8):
•
•
•
•
•
%on: 0x90020000 + (((psr.cwp * 64) + 32 + n) mod (NWINDOWS*64))
%ln: 0x90020000 + (((psr.cwp * 64) + 64 + n) mod (NWINDOWS*64))
%in: 0x90020000 + (((psr.cwp * 64) + 96 + n) mod (NWINDOWS*64))
%gn: 0x90020000 + (NWINDOWS*64) + 128
%fn: 0x90020000 + (NWINDOWS*64)
Debug Operations
Instruction Breakpoints
To insert instruction breakpoints, the breakpoint instruction (ta 1) should be used. This
will leave the four IU hardware breakpoints free to be used as data watchpoints. Since
cache snooping is only done on the data cache, the instruction cache must be flushed
after the insertion or removal of breakpoints. To minimize the influence on execution, it
is enough to clear the corresponding instruction cache tag (which is accesible through
the DSU).
The DSU hardware breakpoints should only be used to freeze the trace buffer, and not
for software debugging since there is a 4-cycle delay from the breakpoint hit before the
processor enters the debug mode.
Single Stepping
By writing the SS bit and reseting the BN bit in the DSU control register, the processor
will resume execution for one instruction and then automatically enter debug mode.
DSU Trap
The DSU trap register (DTR) consists in a read-only register that indicates which
SPARC trap type caused the processor to enter debug mode.
When debug mode is forced by setting the BN bit in the DSU control register, the trap
type is 0x0B.
DSU Communication
Link
DSU communication link consists of a UART connected to the internal bus as a master.
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AT697
Figure 39. DSU Communication Link Block Diagram
Baud-rate
generator
Serial port
Controller
8*bitclk
AMBA APB
DSUTX
DSURX
Receiver shift register
AHB master interface
Transmitter shift register
AHB data/response
AMBA AHB
A simple communication protocol is supported to transmit access parameters and data.
A link command consist of a control byte, followed by a 32-bit address, followed by
optional write data. If the LR bit in the DSU control register is set, a response byte will be
sent after each AHB transfer. If the LR bit is not set, a write access does not return any
response, while a read access only returns the read data.
Data Frame
Commands
Data is sent on 8-bit basis.
Figure 40. DSU UART Data Frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
Through the communication link, a read or write transfer can be generated to any
address on the internal bus. A response byte is can optionally be sent when the proces-
sor goes from execution mode to debug mode. Block transfers can be performed be
setting the length field to n-1, where n denotes the number of transferred words. For
write accesses, the control byte and address is sent once, followed by the number of
data words to be written. The address is automatically incremented after each data
word. For read accesses, the control byte and address is sent once and the correspond-
ing number of data words is returned.
Figure 41. DSU Commands
DSU Write Command
11 Length -1
Send
Addr[31:24] Addr[23:16]
Addr[15:8]
Addr[7:0]
Data[31:24] Data[23:16]
Data[15:8]
Data[7:0]
Receive
Resp. byte (optional)
Response byte encoding
DSU Read command
bit 7:3 = 000000
bit 2 = DMODE
bit 1:0 = HRESP
10 Length -1
Send
Addr[31:24] Addr[23:16]
Addr[15:8]
Data[7:0]
Addr[7:0]
Receive
Data[31:24] Data[23:16]
Data[15:8]
Resp. byte (optional)
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Clock Generation
The UART contains a 14-bit down-counting scaler to generate the desired baud-rate.
The scaler is clocked by the system clock and generates a UART tick each time it
underflows. The scaler is reloaded with the value of the UART scaler reload register
after each underflow. The resulting UART tick frequency should be 8 times the desired
baud-rate.
If not programmed by software, the baud rate will be automatically be discovered. This
is done by searching for the shortest period between two falling edges of the received
data (corresponding to two bit periods). When three identical two-bit periods has been
found, the corresponding scaler reload value is latched into the reload register, and the
BL bit is set in the UART control register. If the BL bit is reset by software, the baud rate
discovery process is restarted. The baud-rate discovey is also restarted when a ‘break’
is received by the receiver, allowing to change to baudrate from the external transmitter.
For proper baudrate detection, the value 0x55 should be transmitted to the receiver after
reset or after sending break.
The best scaler value for manually programming the baudrate can be calculated as
follows:
sysclk × 10
---------------------------------
– 5
baudrate × 8
------------------------------------------
scaler =
10
Booting from DSU
By asserting DSUEN and DSUBRE at reset time, the processor will directly enter debug
mode without executing any instructions. The system can then be initialised from the
communication link, and applications can be downloaded and debugged. Additionally,
external (flash) PROMs for standalone booting can be re-programmed.
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AT697
JTAG Interface
Overview
The AT697 implements a standard interface compliant with the IEEE 1149.1 JTAG
specification. This interface can be used for PCB testing using the JTAG boundary-scan
capability.
The JTAG interface is accessed through five dedicated pins. In JTAG terminology,
these pins constitute the Test Access Port (TAP).
The following table summarizes the TAP pins and there function at JTAG level.
Table 22. TAP Pins
Pin
Name
Type
Description
Used to clock serial data boundary into scan latches and control
sequence of the test state machine. TCK can be asynchronous
with CLK
TCK
Test Clock
Input
Primary control signal for the state machine. Synchronous with
TCK. A sequence of values on TMS adjusts the current state of
the TAP.
TMS
TDI
Test Mode select
Test Data Input
Input
Input
Serial input data to the boundary scan latches. Synchronous
with TCK
Serial output data from the boundary scan latches.
Synchronous with TCK
TDO
Test Data Output
Test Reset
Output
Input
TRST
Resets the test state machine. can be asynchronous with TCK
For more details, please refer to the ‘IEEE Standard Test Access Port and Boundary
Scan’ specification.
Any AT697 based system will contain several JTAG compatible chips. These are con-
nected using the minimum (single TMS signal) configuration. This configuration contains
three broadcast signals (TMS, TCK, and TRST,) which are fed from the JTAG master to
all JTAG slaves in parallel, and a serial path formed by a daisy-chain connection of the
serial test data pins (TDI and TDO) of all slaves.
The TAP supports a BYPASS instruction which places a minimum shift path (1 bit)
between the chip’s TDI and TDO pins. This allows efficient access to any single chip in
the daisy-chain without board-level multiplexing.
Figure 42. JTAG Serial connection using 1 TMS Signal
Part 1
Part 2
Part 3
Part n
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TMS TCK TRST
TMS TCK TRST
TMS TCK TRST
TMS TCK TRST
TMS
TCK
TRST
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TAP Architecture
The TAP implemented in the AT697 consists of a TAP interface, a TAP controller, plus a
number of shift registers including an instruction register (IR) and some registers .
Figure 43. AT697 TAP Architecture
Boundary Scan Register
TDO
TDI
0
1
D
Device ID Register
Q
∇
Mux
EN
Test
Bypass Register
Data Registers
TAP
Clock DR
Shift DR
. . . .
Update DR
Reset
TMS
TAP
Instruction Decode
. . . . . . . . .
Clock IR
Shift IR
Update IR
TCK
Controller
TRST
Instruction Register
. . . .
Select
TCK
Ena TDO
. . . .
Design-Specific Data
TAP Controller
The TAP controller is a synchronous finite state machine (FSM) which controls the
sequence of operations of the JTAG test circuitry, in response to changes at the JTAG
bus. (Specifically, in response to changes at the TMS input with respect to the TCK
input.)
The TAP controller FSM implements the state (16 states) diagram as detailed in the fol-
lowing diagram. The IR is a 3-bit register which allows a test instruction to be shifted into
the AT697. The instruction selects the test to be performed and the test data register to
be accessed. Although any number of loops may be supported by the TAP, the finite
state machine in the TAP controller only distinguishes between the IR and a DR. The
specific DR can be decoded from the instruction in the IR.
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AT697
Figure 44. TAP - State Machine
Test Logic Reset
1
0
1
Run Test/Idle
0
1
1
Select DR Scan
Select IR Scan
0
0
1
1
Capture DR[1]
Capture IR
0
0
Shift DR
Shift IR
0
0
Transitions between
states are controlled
by TMS input value.
1
1
1
1
Exit_1 DR
Exit_1 IR
0
0
Pause DR
Pause IR
0
0
1
1
0
0
Exit_2 DR
Exit_2 IR
1
1
Update DR[1]
Update IR
1
0
1
0
Due to the scan cell layout, "Capture DR" and "Update DR" are states without associated action
during the scanning of internal chains.
TAP Instructions
The following instruction are supported by the AT697 TAP.
Table 23. TAP instruction set
Binary Value Instruction Name
Data Register
Scan Chain Accessed
000
001
010
111
EXTEST
Boundary scan register
Boundary scan register
Bypass register
Boundary scan chain
Boundary scan chain
Bypassscan chain
SAMPLE/PRELOAD
BYPASS
IDCODE
Device id register
ID register scan chain
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BYPASS
EXTEST
This instruction is binary coded "010"
It is used to speed up shifting at board level through components that are not to be
activated.
This instruction is binary coded "000"
It is used to test connections between components at board level. Components output
pins are controlled by boundary scan register during Capture DR on the rising edge of
TCK.
SAMPLE/PRELOAD
IDCODE
This instruction is binary coded "001"
It is used to get a snapshot of the normal operation by sampling I/O states during Cap-
ture DR on the rising edge of TCK. It allows also to preload a value on the output latches
during Update DR on falling edge of TCK. It do not modify system behaviour.
This instruction is binary coded "111"
Value of the IDCODE is loaded during Capture DR.
Test Data Registers
The following data registers are supported in the AT697 TAP:
Bypass Register
Bypass register containing a single shift register stage is connected between TDI and
TDO.
Figure 45. Bypass Register Cell
from TDI
D
to TDO
&
Shift DR
Clock DR
Device ID register
Device ID register is a read only 32-bit register. It is connected between TDI and TDO.
Figure 46. Device ID Register
31
28
27
12
11
1
0
Const.
1
Vers.
0001
Part ID
Manufacturer’s ID
1011 . 0110 . 0100 . 0101
000 . 0101 . 1000
ID. register value: 0x 1b64 50b1
Field Definitions:
[31:28]: Vers - Version number - 0x1
[27:12]: Part ID - Represent part number as assigned by Vendor- 0x b645
[11:01]: Manufacturer’s ID - Represent manufacturer’s ID as per JEDEC - 0x 058
[0]: Const - Constant tied to logic ’1’.
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AT697
Boundary Scan Register
A single scan chain consisting of all of the boundary scan cells (input, output and in/out
cells).
•
The purpose of the boundary scan is the support of scan-based board testing.
Boundary Scan register is connected between TDI and TDO.
To use the boundary scan feature, the PLL will be in bypass mode, i.e. BYPASS signal
direction to VCC.
Checker Scan Register
A single scan chain consisting of all of the scan cells of IU parity checkers. The checkers
scan is only used for factory test. Checkers scan register is connected between TDI and
TDO.
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Execution Mode
Reset Mode
When the RESET input is asserted for at least two cycles, the processor enters reset
mode. Under this mode, the CPU and all the peripherals are halted. Only the following
registers are affected by the reset. All other registers maintain their value or are
undefined.
Table 24. Reset Operation
Register
PC
Description
Reset Value
0x0000 0000
0x0000 0004
program counter
new program counter
nPC
et = 0
s = 1
PSR
processor status register
CCR
cache control register
PROM bus width
0x0000 0000
PIO[1:0]
MCFG1[9:8]
MCFG3[8]
PROM EDAC enable
PIO[2]
When RESET is deasserted, execution restarts from address 0.
Debug Mode
Debug mode can be entered when the DSU is enabled through the external DSUEN pin.
This allows read/write access to all processor registers and caches memories. In debug
mode, the processor pipeline is held and the processor is controlled by the DSU.
Power-down/Idle Mode
AT697 can be idled by writing any value to the power-down register. During power-down
mode, only the integer unit is halted. All other functions and peripherals operate as
nominal.
When a single write to the idle register is performed, idle mode is entered on the next
load instruction. Idle mode is terminated when an unmasked interrupt with higher level
than the current processor interrupt level is pending. Then, the integer unit is re-
enabled.
Here is a simple example allowing Idle mode entry :
! write any value to Idle register
st %g2,[%g1 + 0x18]
! enter Idle mode
ld [%o1 + 0x08],%g3
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AT697
System Clock
Overview
The AT697 clock system is mainly based on two main clock trees : the PCI clock and the
CPU clock. The following figure presents the clock system of the processor and its
distribution.
Figure 47. Clock Distribution
SDCLK
Memory
Control
Interrupt
Controller
Timers
PCI Core
GPI
PCI
Wrapper
Caches
Reg. File
CPU Core
PCI clock
Uarts
BYPASS
LFT
Uart Control Reg.
UACn
PLL
PDIV4
LOCK
Alternate
UART clock
CLK
PCI Clock
The PCI clock is dedicated to the PCI Interface. It is used in particular by the PCI wrap-
per that shares its activity between the two clock domains.
External Clock
The PCI interface and its associated wrapper can only be driven from an external clock.
The PCI clock shall be connected to the PCI_CLK pin of the PCI interface. This input
shall be driven at a frequency in the range of 0 up to 33MHz.
CPU Clock
The CPU clock is routed to the parts of the system concerned with operation of the
SPARC core. Examples of such modules are the CPU core itself, the register files... The
CPU clock is also used by the majority of the I/O modules like Timers, Memory control-
ler, Interrupt Controller, with the exception of the PCI Interface.
The CPU clock is driven either directly by an external oscillator or by the internal PLL.
External Clock
To drive the device directly from an external clock source, the CLK input shall be driven
by an external clock generator while the BYPASS pin is driven high. In that way, the
CPU clock is the direct representation of the clock applied to CLK.
When the external CPU clock source is selected, the clock input can be driven at a fre-
quency in the range of 0MHz up to 100MHz.
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PLL
Overview
The CPU clock can be issued from the internal PLL. This PLL contains a phase/fre-
quency detector, charge pump, voltage control oscillator, lock detector and divider.
Figure 48. PLL Block Diagram
LFT
CLK
cpu
clock
LOCK
Divider
The PLL implemented is configured by hardware to provide a cpu clock frequency four
times the frequency of the input clock.
PLL control
The PLL control is done by hardware through dedicated ports, including a bypass, a
clock input and a filter input.
The following table presents the assignement and functions of the PLL control signals.
Table 25. PLL ports description
Pin name
LFT
Function
External passive loop filter input
LOCK
CLK
Lock
Board clock input
Bypass
BYPASS
PLL filter
To ensure the functionality of the PLL, an external low pass filter shall be connected to
the filter input (LFT) of the PLL. Here is a presentation of the filter to setup on the LFT
pin.
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AT697
Figure 49. Low Pass Filter Connection
Pll
The optimal value for this filter are the following:
•
•
•
R1 = 100 ohms
C1 = 100nF
C2 = 10nF
+/- 10%
+/- 10%
+/- 10%
Operation
To drive the device from the internal PLL, the CLK input shall be driven by an external
clock generator while the BYPASS pin is driven low. In that way, the CPU clock fre-
quency is four time the frequency of the clock applied to CLK.
When the PLL based CPU clock source is selected, the clock input shall be driven at a
frequency in the range of 20MHz up to 25MHz.
Fault Tolerance & Clock
To prevent erroneous operations from single event transient (SET) errors and single
event upset (SEU), the AT697 processor is based on full triple modular redundancy
(TMR) architecture.
Figure 50. TMR structure
Such architecture is based on a fully triplicated clock distribution (CLK1, CLK2 and
CLK3). In that way, each one of the PCI clock and the cpu clock are build as three-clock
trees.
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Skew
To prevent the processor from corruption by single event transient (SET) phenomenon,
additional skew can be programmed on the clock trees. The two dedicated pins SKEW1
and SKEW0 are used to program the delay induced by the skew.
Here is a short description of the skew implementation :
Figure 51. CPU clock tree overview
SKEW[1:0]
BYPASS
PLL
cpu clock
CLK
i1
i2
CLK1 tree
i3
SKEW[1:0]
i1
CLK2 tree
i2
i3
D1
D2
D2 = D1
SKEW[1:0]
i1
i2
D3
D4
CLK3 tree
D4 = D3 = 2 * D1
i3
Three configuration of skew are available :
•
•
•
SKEW[1:0] = ’00’ : natural skew corresponding to the intrinsec routage of the chip
SKEW[1:0] = ’01’ : medium skew ‘artificially’ injected
SKEW[1:0] = ’10’ : maximum skew ‘artificially’ injected
The remaining configuration (SKEW[1:0] = ’11’) is reserved and must not be used at
application level.
Table 26. SKEW assignements
DELAY
SKEW[1:0]
‘00’
CLK1 -> CLK2
natural
CLK1 -> CLK3
natural
Comments
natural skew
medium skew
maximum skew
‘01’
D1
D3
‘10’
D1 + D2
D3 + D4
‘11’
Reserved
Use of a high level of skew improves the efficiency of SET prevention but leads to an
operating loss performance. Maximum speed is decreased and timings on the interfaces
are slower than with natural skew. Refer to the ’Electrical Characteristics’ section for
detailed timings at each skew.
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AT697
Package - MCGA 349
Mechanical Outlines
A2
A
A1
e
mm
inch
0,9
min
max
25,2
min
0,976
max
D/E
D1/E1
A1
A2
A
24,8
0,992
22,86
1,4
2,4
4,3
1,85
3,45
5,9
0,055
0,094
0,169
0,031
0,073
0,136
0,232
0,04
b
0,79
0,99
e
1,27
0,05
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Socket / Adapter
In order to support MCGA 349 package on evaluation board that may require exchange
of the chip, ATMEL had a dedicated socket developped by Adapters-Plus.
Socket reference
The reference of the socket for the MCGA349 package is CL349SA1912F.
Figure 52. CL349SA1912E socket
Top View
Side View
A direct link to information on this socket is available at: http://www.adapt-
plus.com/products/ic_sockets/datasheets/ds_MCGA_lockingskt.htm
Provider
The CL349SA1912F socket is provided by Adapters-Plus :
Adapters-Plus
15 W 8TH STREET STE B.
Tracy, Ca 95376 - USA
Phone: 209-839-0200
Fax: 209-839-0235
www.adapt-plus.com
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AT697
QFP256 package
Package Description
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4226G–AERO–05/09
Registers
Description
Table 27. Register legend
Address = 0x01010101
Bit Number
31 30 29 28 27 26 25 24 23 ... ... ... ...
9
8
7
6
5
4
3
2
1
0
field name
field
reserved
bit
access type
r=read access
w=write acces
r/w=read and write access
default value after reset
0
100
1
x = undefined or non affected by reset
Integer Unit Registers
Table 28. Processor State Register- PSR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
s
impl
ver
n
x
z
v
x
c
x
reserved
ec ef
pil
ps et
r/w
cwp
r
r
r/w
r/w
r
r
r/w
r/w
0001
0001
x
xxxxxx
0
x
xxxx
1
x
0
xxxxx
Bit Number
Mnemonic
Description
Implementation or class of implementations of the architecture.
31..28
impl
Identify one or more particular implementations or is a readable and writable state field whose
properties are implementation-dependent.
27..24
23
ver
n
indicates whether the ALU result was negative for the last instruction modifying icc field.
1 = negative
0 = not negative.
indicates whether the ALU result was zero for the last instruction modifying icc field.
22
21
20
z
v
c
1 = zero
0 = not zero.
indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s
complement notation for the last instruction that modified the icc field. 1 = overflow, 0 = no
overflow.
indicates whether a 2’s complement carry out (or borrow) occurred for the last instruction that
modified the icc field. Carry is set on addition if there is a carry out of bit 31. Carry is set on
subtraction if there is borrow into bit 31. 1 = carry, 0 = no carry.
determines whether the implementation-dependent oprocessor is enabled. If disabled, a
coprocessor instruction will trap. 1 = enabled, 0 = disabled. If an
13
ec
implementation does not support a coprocessor in ardware, PSR.EC should always read as 0
and writes to it should be ignored.
determines whether the FPU is enabled. If disabled, a floating-point instruction will trap. 1 =
enabled, 0 = disabled. If an implementation does not support a hardware FPU, PSR.EF should
always read as 0 and writes to it should be ignored.
12
ef
11..8
pil
identify the interrupt level above which the processor will accept an interrupt.
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AT697
Bit Number
Mnemonic
Description
determines whether the processor is in supervisor or user mode. 1 = supervisor mode, 0 = user
mode.
7
6
s
ps
contains the value of the S bit at the time of the most recent trap.
determines whether traps are enabled. A trap automatically resets ET to 0. When ET=0, an
interrupt request is ignored and an exception trap causes the IU to halt execution, which
typically results in a reset trap that resumes execution at address 0. 1 = traps enabled, 0 = traps
disabled.
5
et
comprise the current window pointer, a counter that identifies the current window into the r
registers. The hardware decrements the CWP on traps and SAVE instructions, and increments
it on RESTORE and RETT instructions (modulo NWINDOWS).
4..0
cwp
Table 29. Window Invalid Mask - WIM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
windows
reserved
7
6
5
4
0
3
0
2
1
0
r
r/w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
Bit
Mnemonic
Description
Indicated wether the window is a ‘valid’ or an ‘invalid’ one.
0 < n < 7
windows[n]
‘0’ : valid
‘1’ : invalid
The WIM can be read by the privileged RDWIM instruction and written by the WRWIM
instruction.
Table 30. Y Register - Y
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
y
r/w
xxxx xxxx
The Y register can be read and written with the RDY and WRY instructions.
Table 31. Trap Base Address - TBR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
tba
tt
r
reserved
r/w
r/w
x
0
0
0
0
85
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Bit Number
Mnemonic
Description
Trap Base Address
This field contains the most-significant 20 bits of the trap table address.
31..12
tba
Trap Type
11..4
tt
This eight-bit field is written by the hardware when a trap occurs, and retains its value until the
next trap. It provides an offset into the trap table.
The tba field is written by the WRTBR instruction. Use of WRTBR is don’t care for tt
field.
Table 32. Program Counters - PC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
address
0x0000 0000
The 32-bit PC contains the address of the instruction currently being executed by the IU.
When a trap occurs, the PC address is saved in the local register (l1). When returning
from trap, l1 value is copied back to PC.
Table 33. New Program Counters - nPC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
address
0x0000 0004
The nPC holds the address of the next instruction to be executed (assuming a trap does
not occur).
When a trap occurs, the nPC address is saved in the local register (l2). When returning
from trap, l2 value is copied back to nPC.
Table 34. Watch Point Address Registers
Address : %asr24, %asr26, %asr28, %asr30
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
waddr
if
r/w
r
r/w
0
xxxx xxxx
0
Bit
Mnemonic
Description
31..2
waddr
Defines the addresses range to be watched
86
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AT697
Bit
Mnemonic
Description
Enable hit generation on instruction fetch
0 = disabled
0
if
1 = enabled
These registers are accessed using the RDASR/WRASR instructions
Table 35. Watch Point Mask registers
Address :%asr25, %asr27, %asr29, %asr31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
wmask
dl ds
r/w
r/w r/w
xxxx xxxx
0
0
Bit
Mnemonic
Description
Defines which bits are to be compared to waddr.
0 = comparison disabled
31..2
wmask
1 = comparison enabled
Enable hit generation on data load
0 = disabled
1
0
dl
1 = enabled
Enable hit generation on data store
0 = disabled
ds
1 = enabled
These registers are accessed using the RDASR/WRASR instructions
Table 36. Register File Protection Control Register
Address :%asr16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
cnt
tcb
te di
r
r/w
r/w
x
r/w r/w
xxxx x
000
0
0
Bit
Mnemonic
Description
Error counter.
11..9
8..2
cnt
tcb
Incremented for each corrected error
Test checkbits
EDAC test enable
0 = disabled
1
te
1 = enabled
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Bit
Mnemonic
Description
Disable EDAC function
1 = disabled
0
di
0 = enabled
This register is accessed using the RDASR/WRASR instructions.
Table 37. Window Registers
Type
Name
Definition
i7
i6
return address
frame pointer
i5
incoming parameter register 5
incoming parameter register 4
incoming parameter register 3
incoming parameter register 2
incoming parameter register 1
incoming parameter register 0
local register 7
i4
in
i3
i2
i1
i0
l7
l6
local register 6
l5
local register 5
l4
local register 4
local
l3
local register 3
l2
nPC (for RETT)
l1
PC (for RETT)
l0
local register 0
o7
o6
o5
o4
o3
o2
o1
o0
temp
stack pointer
outgoing parameter register 5
outgoing parameter register 4
outgoing parameter register 3
outgoing parameter register 2
outgoing parameter register 1
outgoing parameter register 0
out
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AT697
Table 37. Window Registers
Type
Name
g7
Definition
global register 7
g6
global register 6
g5
global register 5
g4
global register 4
global
g3
global register 3
g2
global register 2
g1
global register 1
g0
global register 0 - always 0x00000000
Floating Point Unit
Registers
Table 38. FPU Status register - FSR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
tem
aexc
cexc
rd
ns
ver
ftt
fcc
r/w
xx
r/w
xx
r/w
r
r/w
xx
r
r
r/w
xx
r
r
r
00000
x
001
xxx
xxx
xxxxx
00000
Bit Number
Mnemonic
Description
Rounding Direction
31..30
rd
Defines the rounding direction used by the AT697 FPU during a floating-point arithmetic
operation.
Trap Enable Mask
tem field enables traps caused by FPops. These bits are ANDed with the bits of the cexc
(current exception field) to determine whether to force a floating-point exception to IU. All trap
enable fields correspond to the similarly named bit in the cexc field.
27..23
tem
0 = trap disabled
1 = trap enabled
Causes the FPU to produce implementation-defined results that may not correspond to
ANSI/IEEE Standard 754-1985. For instance, to obtain higher performance, implementations
may convert a subnormal floatingpoint operand or result to zero when NS is set.
22
ns
ver
ftt
Identify one or more particular implementations of the FPU architecture. For each SPARC IU
implementation there may be one or more FPU implementations, or none. This field identifies
the particular FPU implementation present.
19..17
16..14
Floating point trap type
Identify floating-point exception trap types.when floating point exception occurs, the ftt field
encodes the type of floating-point exception until an STFSR or another FPop is executed.
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Bit Number
Mnemonic
Description
Contain the FPU condition codes. These bits are updated by floating-point compare instructions
(FCMP and FCMPE). They are read and written by the STFSR and LDFSR instructions,
respectively. FBfcc bases its control transfer on this field.
11..10
fcc
Accumulate IEEE floating-point exceptions while fp_exception traps are disabled using the
TEM field. After an FPop completes, the TEM and cexc fields are logically anded together. If the
result is nonzero, an fp_exception trap is generated; otherwise, the new cexc field is or’d into
the aexc field. Thus, while traps are masked, exceptions are accumulated in the aexc field.
9..5
4..0
aexc
cexc
Indicate that one or more IEEE floating-point exceptions were generated by the most recently
executed FPop instruction. The absence of an exception causes the corresponding bit to be
cleared.
Trap Types
The ftt field can be read by the STFSR instruction. An LDFSR instruction does not affect
ftt field.
Table 39. Trap Type Definition
TT
Name
Description
0
none
No trap.
An IEEE_754_exception floating-point trap type indicates that a floating-point exception occurred that conforms
to the ANSI/IEEE Standard 754-1985. The exception type is encoded in the cexc field.
1
2
3
IEEE_exception
Unfinished_FPop
An unfinished_FPop indicates that an implementation’s FPU was unable to generate correct results or
exceptions
An unimplemented_FPop indicates that an implementation’s FPU decoded an FPop that it does not implement.
In this case, the cexc field is unchanged
unimplemented_FPop
A sequence_error indicates one of three abnormal error conditions in the FPU, all caused by erroneous
supervisor software:
- An attempt was made to execute a floating-point instruction when the FPU was not able to accept one. This
type of sequence_error arises from a logic error in supervisor software that has caused a previous floating-point
trap to be incompletely serviced (for example, the floating-point queue was not emptied after a previous floating-
point exception).
4
sequence_error
- An attempt was made to execute a STDFQ instruction when the floatingpoint deferred-trap queue (FQ) was
empty, that is, when FSR.qne = 0. (Note that generation of sequence_error is recommended, but not required in
this case)
A hardware_error indicates that the FPU detected a catastrophic internal error, such as an illegal state or a parity
error on an f register access. If a hardware_error occurs during execution of user code, it may not be possible to
recover sufficient state to continue execution of the user application.
5
6
hardware error
invalid register
An invalid_fp_register trap type indicates that one (or more) operands of an FPop are misaligned, that is, a
double-precision register number is not 0 mod 2, or a quadruple-precision register number is not 0 mod 4. It is
recommended that implementations generate an fp_exception trap with FSR.ftt = invalid_fp_register in this case,
but an implementation may choose not to generate a trap.
Floating Point Condition Code
Table 40. FCC Field Definition
FCC
Description
f rs1 = f rs2
f rs1 < f rs2
f rs1 > f rs2
0
1
2
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4226G–AERO–05/09
AT697
FCC
Description
f rs1 ? f rs2
3
indicates an unordered relation, which is true if either f rs1 or f rs2 is a signaling NaN or quiet
NaN
Note:
f rs1 and f rs2 correspond to the single, double, or quad values in the f registers specified
by an instruction’s rs1 and rs2 fields. Note that fcc is unchanged if FCMP or FCMPE gen-
erates an IEEE_exception trap.
Floating Point Exception Fields
The current and accrued exception fields and the trap enable mask assume the follow-
ing definitions of the floating-point exception conditions.
Table 41. Exception Fields
Aexc Mnemonic Cexc Mnemonic
Name
Description
An operand is improper for the operation to be performed. 1 = invalid operand, 0 = valid
operand(s).
nva
ofa
nvc
ofc
Invalid
Examples : 0 ÷ 0, ∞ − ∞ are invalid.
The rounded result would be larger in magnitude than the largest normalized number in the
specified format. 1 = overflow, 0 = no overflow.
Overflow
The rounded result is inexact and would be smaller in magnitude than the smallest
normalized number in the indicated format. 1 = underflow, 0 = no underflow. Underflow is
never indicated when the correct unrounded result is zero.
if UFM=0 : The ufc and ufa bits will be set if the correct unrounded result of an operation is
less in magnitude than the smallest normalized number and the correctly-rounded result is
inexact. These bits will be set if the correct unrounded result is less than the smallest
normalized number, but the correct rounded result is the smallest normalized number. nxc
and nxa are always set as well.
ufa
ufc
Underflow
if UFM=1 : An IEEE_exception trap will occur if the correct unrounded result of an operation
would be smaller than the smallest normalized number. A trap will occur if the correct
unrounded result would be smaller than the smallest normalized number, but the correct
rounded result would be the smallest normalized number.
X÷0, where X is subnormal or normalized.
Note that 0 ÷ 0 does not set the dzc bit.
1 = division-by-zero, 0 = no division-by-zero.
dza
nxa
dzc
nxc
Div_by_zero
Inexact
The rounded result of an operation differs from the infinitely precise correct result.
1 = inexact result, 0 = exact result.
Table 42. f registers - fx ( 0 < x < 31)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
fx
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Memory Interface
Registers
Table 43. Memory Configuration Register 1 - MCFG1
Address = 0x80000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
xx
r/w r/w r/w
r/w
r/w r/w
r/w
r/w
xx
r/w r/w
r/w
xx
r/w
1111
r/w
1111
xxx
x
x
x
xxx
x
x
xxxx
x
x
Bit Number
Mnemonic
Description
I/O bus width.
28:27
iowdh
Defines the data with of the I/O area (“00”=8, “01”=16, “10”=32).
Bus ready enable for I/O area
Bus error enable.
26
25
brdyn
bexcn
I/O waitstates.
23:20
19
iows
iop
Defines the number of waitstates during I/O accesses (“0000”=0, “0001”=1, “0010”=2,...,
“1111”=15).
I/O protection.
‘0’ : Read and write accesses to I/O area are disabled
‘1’ : Read and write accesses to I/O area are enabled.
Prom bank size (*)
17:14
prbsz
Used when in 8 bit PROM mode
Defines the size of PROM bank (“0000”=8 Kbyte, “0001”=16 Kbyte... “1111”=256 Mbyte).
Prom write enable.
If set, enables write cycles to the prom area.
11
prwen
prwdh
prwws
prrws
Prom width.
9:8
7:4
3:0
Defines the data with of the prom area (“00”=8, “01”=16, “10”=32).
Prom write waitstates.
Defines the number of waitstates during prom write cycles (“0000”=0, “0001”=2,... “1111”=30).
Prom read waitstates.
Defines the number of waitstates during prom read cycles (“0000”=0, “0001”=2,... “1111”=30).
During power-up, the prom width (bits [9:8]) are set with value on PIO[1:0] inputs. The
prom waitstates fields are set to 15 (maximum). External bus error and bus ready are
disabled. All other fields are undefined.
Note:
The last 25% of the prom bank size are used to store EDAC checksums when EDAC is
enabled in 8 bit mode.
Table 44. Memory Configuration Register 2 - MCFG2
Address = 0x80000004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w r/w
r/w
r/w r/w r/w
r/w
r/w
r/w
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Table 44. Memory Configuration Register 2 - MCFG2
Address = 0x80000004
x
x
xxx
x
xxx
xx
xx
Description
SDRAM refresh.
xxxx
x
x
xxxx
x
x
x
xx
xx
xx
Bit Number
Mnemonic
31
sdrref
If set, the SDRAM refresh will be enabled.
SDRAM tRP timing.
tRP will be equal to 2 or 3 system clocks (0/1).
30
trp
SDRAM tRFC timing.
tRFC will be equal to 3 + field-value system clocks.
29:27
trfc
SDRAM CAS delay.
26
sdrcas
sdrbs
Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMAND - REGISTER
command must be issued at the same time. Also sets RAS/CAS delay (tRCD).
SDRAM banks size.
Defines the banks size for SDRAM chip selects: “000”=4 Mbyte,
“001”=8 Mbyte,
“010”=16 Mbyte
....
25:23
“111”=512 Mbyte.
SDRAM column size.
“00”=256 when sdrbs = “111”
“01”=512 when sdrbs = “111”
“10”=1024 when sdrbs = “111”
22:21
20:19
sdrcls
“11”=4096 when sdrbs = “111”
“2048 otherwise“
SDRAM command.
Writing a non-zero value will generate an SDRAM command:
“01”=PRECHARGE,
sdrcmd
“10”=AUTO-REFRESH,
“11”=LOAD-COMMAND-REGISTER.
The field is reset after command has been executed.
SDRAM enable.
If set, the SDRAM controller will be enabled.
14
13
se
SRAM disable.
si
If set together with bit 14 (SDRAM enable), the static ram access will be disabled.
SRAM bank size.
12:9
rambs
Defines the size of each ram bank (“0000”=8 Kbyte, “0001”=16 Kbyte... “1111”=256 Mbyte).
Bus ready enable.
7
6
brdy
If set, will enable BRDYN for ram area
Read-modify-write.
rmw
Enable read-modify-write cycles on sub-word writes to 16- and 32-bit areas with common write
strobe (no byte write strobe).
SRAM bus width.
5:4
3:2
1:0
ramwdh
Defines the data with of the SRAMarea (“00”=8, “01”=16, “1X”= 32).
SRAM write waitstates.
ramwws
ramrws
Defines the number of waitstates during SRAM write cycles (“00”=0, “01”=1, “10”=2, “11”=3).
SRAM read waitstates.
Defines the number of waitstates during SRAM read cycles (“00”=0, “01”=1, “10”=2, “11”=3).
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4226G–AERO–05/09
Table 45. Memory Configuration Register 3 - MCFG3
Address = 0x80000008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rfc
me
wb
re pe
tcb
srcrv
rb
r
r/w
xx
r
r/w
r/w r/w r/w r/w
r/w
xxxx xxxx
11
1
xxx xxxx xxxx xxxx
x
x
x
x
Bit Number
Mnemonic
Description
Register file check bits.
31:30
rfc
Indicates how many checkbits are used for the register file (11=7 (EDAC))
Memory EDAC
27
me
Indicates if a memory EDAC is present
26:12
11
srcrv
wb
SDRAM refresh counter reload value.
EDAC diagnostic write bypass
EDAC diagnostic read bypass
10
rb
RAM EDAC enable.
Enable EDAC checking of the RAM area
9
8
re
PROM EDAC enable.
pe
Enable EDAC checking of the PROM area. At reset, this bit is initialised with the value of PIO[2]
Test checkbits.
7:0
tcb
This field replaces the normal checkbits during store cycles when WB is set. TCB is also loaded
with the memory checkbits during load cycles when RB is set.
The period between each AUTO-REFRESH command is calculated as follows:
tREFRESH = ((reload value) + 1) / SYSCLK
Table 46. Write Protection Register 1 - WPR1
Address = 0x8000001C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
en bp
tag[14:0]
mask[14:0]
r/w r/w
r/w
r/w
x
x
xx xxxx xxxx xxxx x
xxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
Enable.
31
30
en
If set, enables the write protect unit
Block protect
If set, selects block protect mode
bp
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Bit Number
Mnemonic
Description
Address tag
This field is compared against address(29:15)
29..15
tag
Address mask
this field contains the address mask
14..0
mask
Table 47. Write Protection Register 2 - WPR2
Address = 0x80000020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
en bp
r/w r/w
tag[14:0]
mask[14:0]
r/w
r/w
x
x
xx xxxx xxxx xxxx x
xxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
Enable.
31
30
en
If set, enables the write protect unit
Block protect
If set, selects block protect mode
bp
Address tag
This field is compared against address(29:15)
29..15
14..0
tag
mask
Address mask
this field contains the address mask
95
4226G–AERO–05/09
System Registers
Table 48. Product Configuration Register - PCR
Address = 0x80000024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
wtpnb
nwindows
icsz
ilsz
dcsz
dlsz
fpu
pci
wprt
r/w
x
r
r
r
r
r
r
r
r
r
r
r
r/w
x
r
r
r
r
1
1
100
0
00111
100
11
100
11
1
1
1
01
01
01
Bit Number
Mnemonic
Description
Debug support unit
“0”=disabled
30
dsu
“1”=present
SDRAM controller present
“0”=disabled
29
sdrctrl
“1”=present
28..26
25
wtpnt
imac
Number of implemented watchpoints (0 - 4)
UMAC/SMAC instruction implemented
Number of register windows.
24..20
19..17
nwindows
icsz
The implemented number of SPARC register windows - 1
Instruction cache size.
The size (in Kbytes) of the instruction cache.
Cache size = 2ICSZ.
Instruction cache line size.
The line size (in 32-bit words) of each line.
Line size = 2ILSZ.
16..15
14..12
11..10
ilsz
Data cache size.
The size (in kbytes) of the data cache.
Cache size = 2DCSZ.
dcsz
dlsz
Data cache line size.
The line size (in 32-bit words) of each line.
Line size = 2DLSZ.
9
8
divinst
mulinst
memstat
fpu
UDIV/SDIV instruction implemented
UMUL/SMUL instruction implemented
Memory status and failing address register present
FPU type
6
5..4
3..2
1..0
pci
PCI core type
wprt
Write protection type
Table 49. Fail Address Register - FAILAR
Address = 0x8000000C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
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AT697
Table 49. Fail Address Register - FAILAR
Address = 0x8000000C
fa
r
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
Failing Address
31:0
fa
This field contents the address of the access that triggered an error response. This register is
updated each time an error occurs in the internal bus.
Table 50. Fail Status Register - FAILSR
Address = 0x80000010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
ce ne rw
hmaster
r
hsize
r/w
r/w r/w
r
r
xxxxxxxxxxxxxxx
0
0
0
0
0
0
0
0
0
0
Bit Number
Mnemonic
Description
9
ce
Correctable error detected by EDAC.
New error.
8
ne
rw
Set when a new error occurred.
After an error, this bit has to be reset by software
Read/Write.
7
This bit is set if the failed access was a read cycle, otherwise it is cleared.
AHB master.
6...3
2..1
hmaster
hsize
This field contains the HMASTER[3:0] of the failed access.
Transfer Size.
This filed contains the HSIZE[2:0] of the failed transfer.
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4226G–AERO–05/09
Caches Register
Table 51. Cache Control Register - CCR
Address = 0x80000014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
drepl
irepl
dsets
isets
ds fd fi
cpc
cpte
ib ip dp
ite
ide
dte
dde
df if
dcs
ics
r
r
r
r
r/w r/w r/w
r
r
r/w
x
r
r
r/w
00
r/w
00
r/w
00
r/w
00
r/w r/w
r/w
xx
r/w
xx
11
11
01
11
x
0
0
10
xx
x
x
x
x
Bit Number
Mnemonic
Description
Data cache replacement policy
31.30
drepl
‘11’ - Least Recently Used (LRU)
Instruction cache replacement policy
‘11’ - Least Recently Used (LRU)
29..28
27..26
irepl
Data cache associativity
Number of sets in the data cache
dsets
‘01’ - 2 way associative
Instruction cache associativity
Number of sets in the instruction cache
25..24
isets
‘11’ - 4 way associative
Data cache snoop enable
If set, will enable data cache snooping.
23
22
21
ds
fd
fi
Flush data cache
If set, will flush the instruction cache. Always reads as zero.
Flush Instruction cache
If set, will flush the instruction cache. Always reads as zero.
Cache parity bits
20..19
cpc
Indicates how many parity bits are used to protect the caches
‘10’ =2 parity bits
Cache parity test bits
These bits are XOR’ed to the data and tag parity bits during diagnostic writes.
18..17
16
cpte
ib
Instruction burst fetch
This bit enables burst fill during instruction fetch.
Instruction cache flush pending
This bit is set when an instruction cache flush operation is in progress.
15
ip
Data cache flush pending
This bit is set when an data cache flush operation is in progress.
14
dp
ite
Instruction cache tag error counter
13..12
This filed is incremented every time an instruction cache tag parity error is detected.
Instruction cache data error counter
11.10
9..8
ide
dte
This field is incremented each time an instruction cache data sub-block parity error is detected.
Data cache tag error counter
This filed is incremented every time a data cache tag parity error is detected.
Data cache data error counter
7..6
dde
This field is incremented each time an instruction cache data sub-block parity error is detected
98
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4226G–AERO–05/09
AT697
Bit Number
Mnemonic
Description
Data Cache Freeze on Interrupt
If set, the data cache will automatically be frozen when an asynchronous interrupt is taken.
5
df
Instruction Cache Freeze on Interrupt
4
if
If set, the instruction cache will automatically be frozen when an asynchronous interrupt is
taken.
Data Cache state
Set and Indicates the current data cache state
3..2
dcs
‘X0’ = disabled
‘01‘ = frozen
‘11‘ = enabled
Instruction Cache state
Set and Indicates the current data cache state
‘X0’ = disabled
‘01’ = frozen
1..0
ics
‘11’ = enabled.
Power Down Register
Table 52. Idle Register - IDLE
Address = 0x80000018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
idle
w
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
Write only with any data. A write to this register followed by a load access will cause the system
to enter power down mode
31..0
idle
99
4226G–AERO–05/09
Timers Registers
Table 53. Timer 1 Counter Register - TIMC1
Address = 0x80000040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
tim1val
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
23..0
Mnemonic
Description
Timer 1 counter value
tim1val
A read access gives the decounting value of the scaler.
Table 54. Timer 1 Reload Register - TIMR1
Address = 0x80000044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
tim1rld
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
23..0
Mnemonic
Description
Timer 1 reload value
A write access programs the reload value of Timer 1 counter.
tim1rld
Table 55. Timer 1 Control Register - TIMCTR1
Address = 0x80000048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w
x
xxxx xxxx xxxx xxxx xxxx xxxx xxxx x
x
x
Bit Number
Mnemonic
Description
Load counter
2
ld1
when written with ‘one’, will load the timer reload register into the timer counter register. Always
reads as a ‘zero’.
Reload counter
1
0
rl1
If RL is set, then the counter will automatically be reloaded with the reload value after each
underflow.
Enable counter
enables the timer when set.
en1
100
AT697E
4226G–AERO–05/09
AT697
Table 56. Watchdog Register - WDG
Address = 0x8000004C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
wdc
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
23..0
Mnemonic
Description
Watchdog counter.
Fixes the watchdog ’Timeout’.
wdc
The ’Timeout’ is the time between the loading (or re-loading) and the watchdog interrupt.
’ResetTimeout’ is greater than ’Timeout’.
Note:
Reading wdc field gives the loading (or re-loading) value, not the effective count value.
Table 57. Timer 2 Counter Register - TIMC2
Address = 0x80000050
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
tim2val
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
23..0
Mnemonic
Description
Timer 2 counter value
tim2val
A read access gives the decounting value of the scaler.
Table 58. Timer 2 Reload Register - TIMR2
Address = 0x80000054
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
tim2rld
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
Timer 2 reload value
A write access programs the reload value of Timer 1 counter.
23..0
tim2rld
101
4226G–AERO–05/09
Table 59. Timer 2 Control Register - TIMCTR2
Address = 0x80000058
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w
x
xxxx xxxx xxxx xxxx xxxx xxxx xxxx x
x
x
Bit Number
Mnemonic
Description
Load counter
2
ld2
when written with ‘one’, will load the timer reload register into the timer coun-
ter register. Always reads as a ‘zero’.
Reload counter
1
0
rl2
If RL is set, then the counter will automatically be reloaded with the reload
value after each underflow.
Enable counter
enables the timer when set.
en2
Table 60. Prescaler Counter Register - SCAC
Address = 0x80000060
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
counter value
r/w
r/w
xxxx xxxx xxxx xxxx xxxx xxx
xx xxxx xxxx
Bit Number
Mnemonic
counter value
Description
prescaler counter value
9..0
A read access gives the decounting value of the prescaler.
Table 61. Prescaler Reload Register - SCAR
Address = 0x80000064
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
reload value
r/w
r/w
xxxx xxxx xxxx xxxx xxxx xxx
xx xxxx xxxx
102
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4226G–AERO–05/09
AT697
Bit Number
Mnemonic
reload value
Description
Prescaler reload value
9..0
A write access programs the reload value of the prescaler.
A read access gives the reload value of the prescaler.
103
4226G–AERO–05/09
UARTs Registers
Table 62. UART 1 Data Register - UAD1
Address = 0x80000070
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
rtd1
r/w
r/w
xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
7..0
rtd1
Received or Transmitted Data of UART1
rtd1 field has 2 meanings:
•
•
A write access enables the sending of the written 8-bit data on UART 1.
A read access provides the received 8-bit data on UART1.
Table 63. UART 1 Status Register - UAS1
Address = 0x80000074
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
fe pe ov br th ts dr
r/w
r/w
xxxx xxxx xxxx xxxx xxxx xxxx x
x
x
x
x
x
x
x
Bit Number
Mnemonic
Description
Framing error
Indicates that a framing error was detected.
6
fe
Parity error
indicates that a parity error was detected.
5
4
3
2
1
0
pe
ov
br
th
Overrun
Indicates that one or more character have been lost due to overrun.
Break received
Indicates that a BREAK has been received.
Transmitter hold register empty
Indicates that the transmitter hold register is empty.
Transmitter shift register empty
Indicates that the transmitter shift register is empty.
ts
Data ready
dr
Indicates that new data is available in the receiver holding register.
Table 64. UART 1 Control Register - UAC1
Address = 0x80000078
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
104
AT697E
4226G–AERO–05/09
AT697
Table 64. UART 1 Control Register - UAC1
Address = 0x80000078
reserved
ec lb fl pe ps ti
ri te re
r/w
r/w
xxxx xxxx xxxx xxxx xxxx xxx
x
x
x
x
x
x
x
x
x
Bit Number
Mnemonic
Description
External Clock
if set, the UART scaler will be clocked by PIO[3]
8
ec
lb
Loop back
If set, loop back mode will be enabled.
7
6
5
Flow control
If set, enables flow control using CTS/RTS.
fl
Parity enable
If set, enables parity generation and checking.
pe
Parity select
Selects parity polarity
“0” = even parity
“1” = odd parity
4
ps
Transmitter interrupt enable
If set, enables generation of transmitter interrupt.
3
2
1
0
ti
ri
Receiver interrupt enable
If set, enables generation of receiver interrupt.
Transmitter enable
If set, enables the transmitter.
te
re
Receiver enable
If set, enables the receiver.
Table 65. UART 1 Scaler Register - UASCA1
Address = 0x8000007C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
scaler value
r/w
r/w
xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx
Table 66. UART 2 Data Register - UAD2
Address = 0x80000080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
rtd2
r/w
105
4226G–AERO–05/09
Table 66. UART 2 Data Register - UAD2
Address = 0x80000080
xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx
Bit Number
Mnemonic
Description
7..0
rtd2
Received or Transmitted Data of UART2
rtd1 field has 2 meanings :
A write access enables the sending of the written 8-bit data on UART 2.
A read access provides the received 8-bit data on UART2.
Table 67. UART 2 Status Register - UAS2
Address 0x80000084
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
fe pe ov br th ts dr
r/w
r/w
xxxx xxxx xxxx xxxx xxxx xxxx x
x
x
x
x
x
x
x
Bit Number
Mnemonic
Description
Framing error
Indicates that a framing error was detected.
6
fe
Parity error
indicates that a parity error was detected.
5
4
3
2
1
0
pe
ov
br
th
Overrun
Indicates that one or more character have been lost due to overrun.
Break received
Indicates that a BREAK has been received.
Transmitter hold register empty
Indicates that the transmitter hold register is empty.
Transmitter shift register empty
Indicates that the transmitter shift register is empty.
ts
Data ready
dr
Indicates that new data is available in the receiver holding register.
Table 68. UART 2 Control Register - UAC2
Address = 0x80000088
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
ec lb fl pe ps ti
ri te re
r/w
106
AT697E
4226G–AERO–05/09
AT697
Table 68. UART 2 Control Register - UAC2
Address = 0x80000088
xxxx xxxx xxxx xxxx xxxx xxx
x
x
x
x
x
x
x
x
x
Bit Number
Mnemonic
Description
External Clock
if set, the UART scaler will be clocked by PIO[3]
8
ec
Loop back
If set, loop back mode will be enabled.
7
6
5
lb
fl
Flow control
If set, enables flow control using CTS/RTS.
Parity enable
If set, enables parity generation and checking.
pe
Parity select
Selects parity polarity
“0” = even parity
“1” = odd parity
4
ps
Transmitter interrupt enable
If set, enables generation of transmitter interrupt.
3
2
1
0
ti
ri
Receiver interrupt enable
If set, enables generation of receiver interrupt.
Transmitter enable
If set, enables the transmitter.
te
re
Receiver enable
If set, enables the receiver.
Table 69. UART 2 Scaler Register - UASCA2
Address = 0x8000008C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
scaler value
r/w
r/w
xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx
107
4226G–AERO–05/09
Interrupt Registers
Table 70. Interrupt Mask and Priority Register - ITMP
Address = 0x80000090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
imask[15:1]
ilevel[15:1]
r/w
r/w
x
r/w
xxxx xxxx xxxx xxx
r/w
x
xxxx xxxx xxxx xxx
Bit Number
Mnemonic
Description
Interrupt level
31..17
ilevel[15:1]
indicates whether an interrupt belongs to priority level 1 (ILEVEL[n]=1) or level 0 (ILEVEL[n]=0).
Interrupt mask
indicates whether an interrupt is masked or enabled
‘0’ = masked
‘1’ = enabled
15..1
imask[15:1]
Table 71. Interrupt Pending Register - ITP
Address = 0x80000094
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ipend[15:1]
reserved
r/w
r
r/w
x
xxxx xxxx xxxx xxxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Number
Mnemonic
Description
Interrupt pending
indicates whether an interrupt is pending
“1” = interrupt pending
15..1
ipend[15:1]
“0” = interrupt not pending
When the IU acknowledges the interrupt, the corresponding pending bit is automatically
cleared.
Table 72. Interrupt Force Register - ITF
Address = 0x80000098
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
iforce[15:1]
reserved
r/w
r/w
r/w
x
xxxx xxxx xxxx xxxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
108
AT697E
4226G–AERO–05/09
AT697
Bit Number
Mnemonic
Description
Interrupt force
indicates whether an interrupt is being forced
“1” = interrupt forced
15..1
iforce[15:1]
“0” = interrupt not forced
Interrupt can be forced by setting a bit in the interrupt force register. IU acknowledge-
ment will clear the force bit.
Table 73. Interrupt Clear Register - ITC
Address = 0x8000009C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
iclear[15:1]
reserved
r/w
r
r/w
x
xxxx xxxx xxxx xxxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Number
Mnemonic
Description
iclear[15:1]
Interrupt clear
If written with a ‘1’, will clear the corresponding bit(s) in the interrupt pending register.
A read returns zero.
109
4226G–AERO–05/09
General Purpose
Interface Registers
Table 74. I/O Port Data Register - IODAT
Address = 0x800000A0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
meddat
lowdat
iodata
r/w
r/w
xxxx xxxx
xxxx xxxx
xxxx xxxx xxxx xxxx
Bit Number
15..0
Mnemonic
Description
I/O port data
iodata
when read, returns the current value of the I/O port;
when written, value is driven on the I/O port signals (if enabled as Output )
Table 75. I/O Port Direction Register - IODIR
Address = 0x800000A4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
iodir[15:0]
r/w
r/w r/w
r/w
xxxx xxxx xxxx xx
xx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
17
16
meddir
lowddir
Defines the direction of D[15..8]
Defines the direction of D[7..0]
I/O port direction
Defines the direction of I/O ports 15 - 0.
‘1’ = output
15..0
iodir
‘0’ = input
Table 76. I/O Port Interrupt Register - IOIT
Address = 0x800000A8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
isel2
isel1
isel0
isel3
r/w r/w r/w
r/w
r/w r/w r/w
r/w
r/w r/w r/w
r/w
r/w r/w r/w
r/w
0
x
x
x xxxx
0
x
x
x xxxx
0
x
x
x xxxx
0
x
x
x xxxx
110
AT697E
4226G–AERO–05/09
AT697
Bit Number
Mnemonic
Description
Enable.
31
en3
If set, the corresponding interrupt will be enabled, otherwise it will be masked.
Level/edge triggered.
If set, the interrupt will be edge-triggered, otherwise level sensitive.
30
29
le3
pl3
Polarity
If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be
active low (or edge-triggered on negative edge).
I/O port select.
28..24
23
isel3
en2
le2
The value of this field defines which I/O port (0 - 31) should generate parallel I/O port interrupt 3.
Enable.
If set, the corresponding interrupt will be enabled, otherwise it will be masked.
Level/edge triggered.
If set, the interrupt will be edge-triggered, otherwise level sensitive.
22
Polarity
21
pl2
If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be
active low (or edge-triggered on negative edge).
I/O port select.
20..16
15
isel2
en1
le1
The value of this field defines which I/O port (0 - 31) should generate parallel I/O port interrupt 2.
Enable.
If set, the corresponding interrupt will be enabled, otherwise it will be masked.
Level/edge triggered.
If set, the interrupt will be edge-triggered, otherwise level sensitive.
14
Polarity
13
pl1
If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be
active low (or edge-triggered on negative edge).
I/O port select.
12..8
isel1
en0
le0
The value of this field defines which I/O port (0 - 31) should generate parallel I/O port interrupt 3.
Enable.
7
6
If set, the corresponding interrupt will be enabled, otherwise it will be masked.
Level/edge triggered.
If set, the interrupt will be edge-triggered, otherwise level sensitive.
Polarity
5
pl0
If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be
active low (or edge-triggered on negative edge).
I/O port select.
4..0
isel0
The value of this field defines which I/O port (0 - 31) should generate parallel I/O port interrupt 2.
111
4226G–AERO–05/09
PCI Registers
Table 77. PCI Device Identification Register 1 - PCIID1
Address = 0x80000100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
device id
vendor id
r
r
0x1202
0x1438
Bit Number
Mnemonic
Description
This field identifies the particular device. This identifier is allocated by the vendor.
31..16
device id
This field identifies the manufacturer of the device. Valid vendor identifiers are allocated by the
PCI SIG to ensure uniqueness. 0FFFFh is an invalid value for Vendor ID.
15..0
vendor id
Table 78. PCI Status - Command Register - PCISC
Address = 0x80000104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
rr rr rr rr rr
r
rr
0
r
r
r
r
r
r
r/w r/w r/w
r
r/w
0
r
r/w
0
r
r/w r/w r/w
0
0
0
0
0
01
1
0
0
0
0
0x0000 0000
0
0
0
0
0
0
0
0
0
Note:
1. rr = Read and Reset by writing 1
Bit Number
Mnemonic
Description
Parity error detected.
31
30
29
28
27
stat15
This bit must be set by the device whenever it detects a parity error, even if parity error handling
is disabled (as controlled by bit 6 in the Command register).
SERR asserted.
stat14
stat13
stat12
stat11
This bit must be set whenever the device asserts SERR*. Devices who will never assert SERR*
do not need to implement this bit.
Master has terminated master abort.
This bit must be set by a master device whenever its transaction except for Special Cycle) is
terminated with Master-Abort. All master devices must implement this bit.
Master has terminated target abort
This bit must be set by a master device whenever its transaction is terminated with Target-
Abort. All master devices must implement this bit.
Target signal target abort.
This bit must be set by a target device whenever it terminates a transaction with Target-Abort.
Devices that will never signal Target-Abort do not need to implement this bit.
Devsel timing.
These bits encode the timing of DEVSEL*. Three allowable timings for assertion of DEVSEL*
are specified. These are encoded as 00 for fast, 01 for medium, and 10 for slow (11b is
reserved). These bits are read-only and must indicate the slowest time that a device asserts
DEVSEL* for any bus command except Configuration Read and Configuration Write.
26..25
stat10_9
112
AT697E
4226G–AERO–05/09
AT697
Bit Number
Mnemonic
Description
Master received/asserted PERR
This bit is only implemented by bus masters. It is set when three conditions are met:
1) the bus agent asserted PERR* itself (on a read) or observed PERR* asserted (on a
24
stat8
write);
2) the agent setting the bit acted as the bus master for the operation in which the error
occurred;
3) the Parity Error Response bit (Command register) is set.
Target supports fast back2back
This optional read-only bit indicates whether or not the target is capable of accepting fast back-
to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if
the device can accept these transactions and must be set to 0 otherwise.
23
22
21
stat7
stat6
stat5
User definable features
66 MHz capabality
This optional read-only bit indicates whether or not this device is capable of running at 66 MHz
as defined in Chapter 7. A value of zero indicates 33 MHz. A value of 1 indicates that the device
is 66 MHz capable
Power management capability.
This optional read-only bit indicates whether or not this device implements the pointer for a New
Capabilities linked list at offset 34h. A value of zero indicates that no New Capabilities linked list
is available. A value of one indicates that the value read at offset 34h is a pointer in
Configuration Space to a linked list of new capabilities.
20
10
stat4
Interrupt command.
This bit disables the device/function from asserting INTx*. A value of 0 enables the assertion of
its INTx* signal. A value of 1 disables the assertion of its INTx* signal. This bit’s state after
PCI_RST* is 0.
com10
Master can generate fast back2back.
This optional read/write bit controls whether or not a master can do fast back-to-back
transactions to different devices. Initialization software will set the bit if all targets are fast back-
to-back capable. A value of 1 means the master is allowed to generate fast back-to-back
transactions to different agents. A value of 0 means fast back-to-back transactions are only
allowed to the same agent. This bit's state after PCI_RST* is 0.
9
com9
Enable SERR driver
-This bit is an enable bit for the SERR* driver. A value of 0 disables the SERR* driver. A
value of 1 enables the SERR* driver. This bit's state after PCI_RST* is 0. All devices that have
an SERR* pin must implement this bit. Address parity errors are reported only if this bit and bit
6 are 1.
8
7
com8
com7
Address/Data stepping on PCI bus
Enable Parity Check
This bit controls the device's response to parity errors. When the bitis set, the device must take
its normal action when a parity error is detected. When the bit is 0, the device sets its Detected
Parity Error status bit (bit 15 in the Status register) when an error is detected, but does not
assert PERR* and continues normal operation. This bit's state after PCI_RST* is 0. Devices
that check parity must implement this bit. Devices are still required to generate parity even if
parity checking is disabled.
6
com6
VGA palette snooping
This bit controls how VGA compatible and graphics devices handle accesses to VGA palette
registers. When this bit is 1, palette snooping is enabled (i.e., the device does not respond to
palette register writes and snoops the data). When the bit is 0, the device should treat palette
write accesses like all other accesses. VGA compatible devices should implement this bit.
5
4
com5
com4
Enable memory write and invalidate. This is an enable bit for using the Memory Write and
Invalidate command. When this bit is 1, masters may generate the command. When it is 0,
Memory Write must be used instead. State after PCI_RST* is 0. This bit must be implemented
by master devices that can generate the Memory Write and Invalidate command.
113
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Bit Number
Mnemonic
Description
Enable special cycles
Controls a device's action on Special Cycle operations. A value of 0 causes the device to ignore
all Special Cycle operations. A value of 1 allows the device to monitor Special Cycle operations.
State after PCI_RST* is 0.
3
com3
Enable PCI master
Controls a device's ability to act as a master on the PCI bus. A value of 0 disables the device
from generating PCI accesses. A value of 1 allows the device to behave as a bus master. State
after PCI_RST* is 0.
2
1
0
com2
com1
com1
Enable target memory command response
Controls a device's response to Memory Space accesses. A value of 0 disables the device
response. A value of 1 allows the device to respond to Memory Space accesses. State after
PCI_RST* is 0.
Enable target IO command response
Controls a device's response to I/O Space accesses. A value of 0 disables the device
response. A value of 1 allows the device to respond to I/O Space accesses. State after
PCI_RST* is 0.
Table 79. PCI Device Identification 2 - PCIID2
Address = 0x80000108
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
class code
revision id
r
r
0xB
0x01
Bit Number
Mnemonic
Description
The Class Code register is read-only and is used to identify the generic function of the device
and, in some cases, a specific register-level programming interface. The register is broken into
three byte-size fields. The upper byte (at offset 0Bh) is a base class code which broadly
classifies the type of function the device performs. The middle byte (at offset 0Ah) is a sub-
class code which identifies more specifically the function of the device. The lower byte (at offset
09h) identifies a specific register-level programming interface (if any) so that device
independent software can interact with the device.
31..8
class code
This register specifies a device specific revision identifier. The value is chosen by the vendor.
Zero is an acceptable value. This field should be viewed as a vendor defined extension to the
Device ID.
7..0
revision id
Table 80. Bist, Header type, Latency, Cache line size Register - PCIBHLC
Address = 0x8000010C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
bist
header type
latency timer
cache line size
r/w
r/w
r/w
r/w
0x00
0x00
0x00
0x00
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Bit Number
Mnemonic
Description
bist7 : Return 1 if device supports BIST. Return 0 if the device is not BIST capable.
bist6 : Write a 1 to invoke BIST. Device resets the bit when BIST is complete. Software should
fail the device if BIST is not complete after 2 seconds.
31..24
bist
bist[3..0] : A value of 0 means the device has passed its test. Non-zero values mean the device
failed. Device-specific failure codes can be encoded in the non-zero value.
header 7 : multi-function device
“0” : device is single function
“1” : device is multi-function
23..16
header type
header[6..0] : header second part layout
15..8
7..0
latency timer
this field specifies the value for latency timer in PCI bus clock unit
Specifies the cache line size
cache line size
Table 81. Memory Base Address Register 1 - MBAR1
Address = 0x80000110
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
base address
r/w
r
r
r
r
r
0x00
0x0000 0
1
0
0
0
Bit Number
Mnemonic
Description
31..4
base address
Prefetchable
3
pref
type
indicates there are no side effects on reads. The device returns all bytes on reads regardless of
the byte enables.
“00” Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory
Space.
2..1
0
“10” Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space.
“11” & “01” Reserved
msi
“0” : Indicates that base address mapes Memory Space
115
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Table 82. Memory Base Address Register 2 - MBAR2
Address = 0x80000114
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
base address
r/w
r
r
r
r
r
0x00
0x0000 0
1
0
0
0
Bit Number
Mnemonic
Description
31..4
base address
Prefetchable
3
pref
type
indicates there are no side effects on reads. The device returns all bytes on reads regardless of
the byte enables.
“00” Base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory
Space.
2..1
0
“10” Base register is 64 bits wide and can be mapped anywhere in the 64-bit address space.
“11” & “01” Reserved
msi
“0” : Indicates that base address mapes Memory Space
Table 83. IO Base Address Register 3 - IOBAR3
Address = 0x80000118
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
io base address
r/w
r
r
r
0x000000
0x00
0
1
Bit Number
Mnemonic
base address
msi
Description
31..2
0
“1” : Indicates that base address mapes I/O Space
116
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AT697
Table 84. Subsystem Identification Register - PCISID
Address = 0x8000012C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
subsystem id
svi
r
r
0x1
0x1438
Bit Number
31..16
Mnemonic
Description
subsystem id
sid
svi
subsystem vendor id
15..0
Table 85. PCI Capabilities Pointer Register - PCICP
Address = 0x80000134
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
pointer
r
r
0x0000 00
0xDC
Bit Number
Mnemonic
Description
index for the extended capabilities registers
7..0
pointer
Table 86. PCI Latency Interrupt Register - PCILI
Address = 0x8000013C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
max_lat
min_gnt
int_pin
int_line
r/w
0
r/w
0
r
r/w
0
0
Bit Number
Mnemonic
Description
maxlat field specifies how often the processor need to gain access to the
PCI bus. Units are 0.25 micosecond
31:24
23:16
15:8
7:0
maxlat
mingnt
intpin
intlin
min_gnt identifies the length of burst period, assuming a 33MHz clock. Units
are 0.25 micosecond
indicates which interrupt pin the processor uses - Always 0 due to absence
of PCI interrupt management.
Indicates the interrupt line register to which the core is connected to. -
Always 0 due to absence of PCI interrupt management.
117
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Table 87. PCI Retry _trdy - PCIRT
Address = 0x80000140
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
retry
trdy
r/w
r/w
0x80
0
Bit Number
0
Description
0x80
Mnemonic
Indicates the number of retry the core will performe when configured as
master
15:8
7:0
retry
trdy
Indicates the number of PCI clock the processor configured as master will
wait for TRDY
Table 88. PCI Configuration Write Register - PCICW
Address = 0x80000144
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
ben
r/w
r/w
0x0000 000
0x0
Bit Number
Mnemonic
Description
Byte enables for writes to the PCI core configuration space
3..0
ben
‘0’ = enabled
‘1’ = disabled
Each of the 4 bits is assigned to one 8-bit lane.
•
•
•
•
bit ben[3] is applied to Byte 3, the most significant byte (MSB)
bit ben[2] is applied to Byte 2
bit ben[1] is applied to Byte 1
bit ben[0] is applied to Byte 0, the less significant byte (LSB)
Table 89. PCI Initiator Start Address - PCISA
Address = 0x80000148
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
start address
r/w
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
118
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AT697
Bit Number
Mnemonic
Description
31..0
start address
PCI start address for PCI initiator transactions in APB and DMA mode.
Table 90. PCI Initiator Write Register - PCIIW
Address = 0x8000014C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
ben
r/w
r/w
0x0000 000
0x0
Bit Number
Mnemonic
Description
Byte enables for writes to the PCI core configuration space
3..0
ben
‘0’ = enabled
‘1’ = disabled
Each of the 4 bits is assigned to one 8-bit lane.
•
•
•
•
bit ben[3] is applied to Byte 3, the most significant byte (MSB)
bit ben[2] is applied to Byte 2
bit ben[1] is applied to Byte 1
bit ben[0] is applied to Byte 0, the less significant byte (LSB)
Table 91. PCI DMA configuration Register - PCIDMA
address = 0x80000150
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
com
wdcnt
r/w
r/w
0x0
r/w
0x0000 0
0
0x00
Bit Number
Mnemonic
Description
Use back2back-mode.
Can be written to 1, if this transaction is to the same target, as the last one.
12
b2b
Note: works only, if the core is enabled for back2back mode.
11..8
7..0
com
PCI command to be used in DMA mode.
Word count.
Minimum number of words for the burst.
wdcnt
119
4226G–AERO–05/09
Table 92. PCI Initiator Status Register - PCIIS
address = 0x8000015C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
dmas
act xff xfe rfe
ss
r
r/w
r
r
r
r
r
0x0000 0
0x0
0
0
1
1
0x0
Bit Number
Mnemonic
Description
11..8
dmas
DMA state
PCI core active
1 = active
7
act
0 = inactive
6
5
ff
If set 1, the transmitter fifo is full
If set 1, the transmitter fifo is empty
If set 1, the receiver fifo is empty
Slave status
xfe
rfe
ss
4
3..0
Table 93. PCI Initiator Configuration - PCIIC
Address = 0x80000158
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w
01
r/w
00
r/w r/w r/w r/w
0x0000 00
0
0
0
0
Bit Number
Mnemonic
Description
Specifies the two most significant bits of the command used by AHB slave interface.
‘00’ = IO write
7.6
cmd
‘01’ = memory read/write
‘10’ = configuration read/write
‘11’ = mem-read-line/write-invalidate
Perr retry enable
If set make target generate a retry on read with parity error
3
2
perr
Double word write
‘1’ = executes double word write as one 2 word burst
‘0’ = executes double word write as bursts of undefined length
dww
Double word read
1
dwr
‘1’ = executes a 2 word burst read
‘0’ = executes two single reads
120
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AT697
Bit Number
Mnemonic
Description
PCI command source mode
‘1’ = AHB slave - DMA mode
‘0’ = APB mode
0
mod
Table 94. PCI Target Page Address Register - PCITPA
Address = 0x8000015C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
tpa1
reserved
tpa2
reserved
r/w
r/w
r/w
r/w
0x40
0x00
0x90
0x00
Bit Number
Mnemonic
Description
Target page address
31..24
15..8
tpa1
defines the 8 most significant bits of the 16 MByte memory page on which PCI addresses are
mapped
Target page address
defines the 8 most significant bits for the second memory BAR.
tpa2
Table 95. PCI Target Status-Command Register - PCITSC
Address = 0x80000160
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
0x0000 00
0
0
1
1
0
0
0
0
Bit Number
Mnemonic
Description
Reception Fifo parity error
7
errmem
‘0’ = Do not save data with parity error
‘1’ = Data with parity error is saved to memory
TXMT Fifo full
‘1’ = force transmistion to abort
6
5
xff
xfe
rfe
TXMT Fifo empty
‘1’ = flushes TXMT Fifo
TRCV Fifo empty
‘1’ = flushes TRCV Fifo
4
Target AHB master state
‘1111’ = reset the state machine
3..0
tms
121
4226G–AERO–05/09
Table 96. PCI Interrupt Enable Register - PCIITE
Address = 0x80000164
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w r/w r/w r/w r/w r/w r/w r/w
0x0000 00
0
0
0
0
0
0
0
0
Bit Number
Mnemonic
Description
DMA end of transfer
‘0’ = disable
7
dmaer
‘1’ = enable
Initiator error
‘0’ = disable
‘1’ = enable
6
5
4
3
2
1
0
imier
cmfer
imper
tier
PCI core error
‘0’ = disable
‘1’ = enable
Initiator Parity error
‘0’ = disable
‘1’ = enable
Target error
‘0’ = disable
‘1’ = enable
Target byte enable error
‘0’ = disable
‘1’ = enable
tbeer
tper
Target parity error
‘0’ = disable
‘1’ = enable
System error asserted on PCI bus
‘0’ = disable
syser
‘1’ = enable
Table 97. PCI Interrupt Pending Register - PCIITP(1)
Address = 0x80000168
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w r/w r/w r/w r/w r/w r/w r/w
0x0000 00
0
0
0
0
0
0
0
0
122
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Bit Number
Mnemonic
Description
DMA end of transfer
7
dmaer
‘0’ = not pending
‘1’ = pending
Initiator error
6
5
4
3
2
1
0
imier
cmfer
imper
tier
‘0’ = not pending
‘1’ = pending
PCI core error
‘0’ = not pending
‘1’ = pending
Initiator Parity error
‘0’ = not pending
‘1’ = pending
Target error
‘0’ = not pending
‘1’ = pending
Target byte enable error
‘0’ = not pending
‘1’ = pending
tbeer
tper
Target parity error
‘0’ = not pending
‘1’ = pending
System error asserted on PCI bus
‘0’ = not pending
syser
‘1’ = pending
Note:
1. Bits are cleared when written with a 1. Writing a 0 to the register has no effect.
Table 98. PCI Interrupt Force Register - PCIITF
Address = 0x8000016C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
r/w
r/w r/w r/w r/w r/w r/w r/w r/w
0x0000 00
0
0
0
0
0
0
0
0
Bit Number
Mnemonic
Description
DMA end of transfer
‘0’ = not forced
‘1’ = forced
7
dmaer
Initiator error
‘0’ = not forced
‘1’ = forced
6
5
imier
PCI core error
‘0’ = not forced
‘1’ = forced
cmfer
123
4226G–AERO–05/09
Bit Number
Mnemonic
Description
Initiator Parity error
‘0’ = not forced
‘1’ = forced
4
imper
Target error
‘0’ = not forced
‘1’ = forced
3
2
1
0
tier
tbeer
tper
Target byte enable error
‘0’ = not forced
‘1’ = forced
Target parity error
‘0’ = not forced
‘1’ = forced
System error asserted on PCI bus
‘0’ = not forced
syser
‘1’ = forced
Table 99. PCI Data Register - PCID
Address = 0x80000170
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
dat
r/w
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
31..0
dat
data writen/read to/from Fifo
Table 100. PCI Burst End Register - PCIBE
Address = 0x80000174
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
dat
r/w
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
31..0
dat
Last data of a burst in APB mode
124
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AT697
Table 101. PCI DMA Address Register - PCIDMAA
Address = 0x80000178
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
addr
r/w
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Bit Number
Mnemonic
Description
31..0
addr
Defines the start address of a DMA transaction
Table 102. PCI Arbiter Register - PCIA
Address = 0x80000280
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
p3 p2 p1 p0
r
r
r/w r/w r/w
0x0000 000
1
1
1
1
Bit Number
Mnemonic
Description
3
2
1
0
p3
p2
p1
p0
Round robin level for agent 3
Round robin level for agent 2
Round robin level for agent 1
Round robin level for agent 0
DSU Registers
Table 103. Trace Buffer Control Register - TBC
Address = 0x9000004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
ta ti reserved
AHB index
reserved
Inst Index
r/w
r/w r/w
r/w
r/w
r/w
r/w
000000
000
000
Bit Number
Mnemonic
Description
25
24
ta
ti
Trace AHB enable
Trace instruction enable
20..12
AHB Index
AHB trace index counter
125
4226G–AERO–05/09
Bit Number
Mnemonic
Description
8..0
Inst Index
Instruction trace index counter
Table 104. DSU Control Register - DSUC
Address = 0x90000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
dcnt
re dr lr ss pe ee eb dm de bz bx bd bn bs bw be ft bt dm te
read only
Bit Number
Mnemonic
Description
28..20
dcnt
Trace buffer delay counter
Reset error mode
if set, will clear the error mode in the processor.
19
18
re
dr
Debug mode response
If set, the DSU communication link will send a response word when
the processor enters debug mode
Link response
17
16
15
lr
If set, the DSU communication link will send a response word after
AHB transfer.
Single step
ss
pe
If set, the processor will execute one instruction and the return to
debug mode
Processor error mode
returns ‘1’ on read when processor is in error mode
else return ‘0’.
14
13
ee
eb
value of the external DSUEN signal (read-only)
value of the external DSUBRE signal (read-only)
Debug mode
12
dm
Indicates when the processor has entered debug mode (read-only).
Delay counter enable
If set, the trace buffer delay counter will decrement for each stored
trace. This bit is set automatically when an DSU breakpoint is hit
and the delay counter is not equal to zero.
11
de
Break on error traps
If set, will force the processor into debug mode on all except the
following traps: priviledged_instruction, fpu_disabled,
window_overflow, window_underflow, asynchronous_interrupt,
ticc_trap.
10
9
bz
bx
Break on trap
If set, will force the processor into debug mode when any trap
occurs.
126
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Bit Number
Mnemonic
Description
Break on DSU breakpoint
8
bd
If set, will force the processor to debug mode when an DSU
breakpoint is hit.
Break now
7
bn
Force processor into debug mode. If cleared, the processor will
resume execution.
Break on S/W breakpoint
6
5
4
bs
bw
be
If set, debug mode will be forced when an breakpoint instruction (ta
1) is executed
Break on IU watchpoint
If set, debug mode will be forced on a IU watchpoint (trap 0xb).
Break on error (BE) - if set, will force the processor to debug mode
when the processor would have entered error condition (trap in
trap).
Freeze timers
3
2
1
0
ft
bt
If set, the scaler in the LEON timer unit will be stopped during debug
mode to preserve the time for the software application.
Break on trace
If set, will generate a DSU break condition on trace freeze.
Delay counter mode (DM). In mixed tracing mode, setting this bit
will cause the delay counter to decrement on AHB traces. If reset,
the delay counter will decrement on instruction traces
dm
te
Trace enable.
Enables the trace buffer.
Table 105. DSU UART Status Register - DSUUS
Address = 0x800000C4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
fe
ov
th ts dr
r/w
r
r/w
x
r
r/w
x
r
r
r
xxxx xxxx xxxx xxxx xxxx xxxx x
0
0
0
0
0
Bit Number
Mnemonic
Description
Framing error
Indicates that a framing error was detected.
6
fe
Overrun
4
2
1
0
ov
th
ts
Indicates that one or more character have been lost due to overrun.
Transmitter hold register empty
Indicates that the transmitter hold register is empty.
Transmitter shift register empty
Indicates that the transmitter shift register is empty.
Data ready
dr
Indicates that new data is available in the receiver holding register.
127
4226G–AERO–05/09
Table 106. DSU Trap Register - DTR
Address = 0x9008001C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
em
trap type
0000
Bit Mnemonic
Description
Error Mode.
em
Set if the trap would have cause the processor to enter error mode
trap type
8_bit Sparc trap type
Table 107. Break Address Register 1 - BAD1
Address = 0x90000010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BADD
ex
Bit mnemonic
Description
Enables break on executed instruction
ex
Table 108. Break Mask Register 1 - BMA1
Address = 0x90000014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BMA
ld st
Bit mnemonic
Description
ex
ld
Enables break on executed instruction
Enables break on AHB load
st
Enables break on AHB write
Table 109. Break Address Register 2- BAD2
Address = 0x90000018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BADD
ex
Bit mnemonic
Description
Enables break on executed instruction
ex
128
AT697E
4226G–AERO–05/09
AT697
Table 110. Break Mask Register - BMA2
Address = 0x9000001C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BMA
ld st
Bit mnemonic
Description
ex
ld
Enables break on executed instruction
Enables break on AHB load
st
Enables break on AHB write
Table 111. DSU UART Control Register - DSUUC
Address = 0x800000C8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
bl re
r/w
r
r/w
x
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0
Bit Number
Mnemonic
Description
Baud rate locked
Is automatically set when the baud rate is locked.
1
bl
Receiver enable
If set, enables both the transmitter and receiver.
0
re
129
4226G–AERO–05/09
Table 112. DSU UART Scaler Reload Register - DSUUS
Address = 0x800000CC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
reserved
scaler reload value
r/w
r/w
xxxx xxxx xxxx xxxx xx
xx xxxx xxxx xxxx
Note:
1. The best scaler value for manually programming the baudrate can be calculated as follows:
sysclk × 10
---------------------------------
– 5
baudrate × 8
------------------------------------------
scaler =
10
130
AT697E
4226G–AERO–05/09
AT697
Electrical Characteristics
Electrical Characteristics for this product have not yet been finalized. Please consider all values
listed here as preliminary and non contractual
Absolute Maximum Ratings
Operating Temperature .....................................................................-55 °C to +125 °C
Storage Temperature ........................................................................-65 °C to +150 °C
Voltage on VDD with respect to Ground ..............................................-0.5 V to + 2.0 V
Voltage on VCC with respect to Ground ..............................................-0.5 V to + 4.0 V
DC current VCC (VDD) and VSS Pins .............................................................200 mA
Input Voltage on I/O pins with respect to Ground .....................................-0.5 V to +4 V
DC current per I/O pins....................................................................................40 mA
ESD ............................................................................................................... 250 V
Notes: 1. Stresses at or above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Characteristics
Table 113. DC characteristics
Symbol
Parameter
Min
1.65
3
Typ
1.8
3.3
Max
1.95
3.6
Unit
V
Test Conditions
VDD
VCC
Core Power Supply
I/O Power Supply Voltage
V
IILpu
Low Level Input Pull-up Current
High Level Input Pull-downCurrent
Low Level Input Leakage Current
High Level Input Leakage Current
High Impedance Current
100
100
-1
500
500
1
uA
uA
uA
uA
uA
V
Vin = VSS
Vin = VCC (max)
Vin = VSS
IIHpd
IIL
IIH
-1
1
Vin = VCC (max)
Vin = VSS or VCC (max)
IOZ
100
500
0.8
VIL TTL
VIL CMOS
VIH TTL
VIH CMOS
Low Level Input Voltage
30%VCC
V
2
V
High Level Input Voltage
Low Level Output Voltage
70%VCC
V
VCC = VCC(min)
VOL
VOL pci
VOH
0.4
V
V
V
IOL = 2, 4, 8, 16mA
Low Level Output Voltage
for PCI buffers
VCC = VCC(min)
IOL = 1.5mA
0.1 VCC
VCC = VCC(min)
High Level Output Voltage
VCC - 0.4
IOH = 2, 4, 8, 16mA
131
4226G–AERO–05/09
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
High Level Output Voltage
for PCI buffers
VCC = VCC(min)
IOH = 0.5mA
VOH pci
0.9 VCC
V
VCC = VCC(max)
no clock active
ICCSb
Standby Current
5
mA
Power “On/Off”
Sequence
The AT697E is based on the Atmel 0.18 µm CMOS process. As VDD (1.8V) and VCC
(3.3V) power supplies are electrically isolated, there is no specified sequence in which
the power rails may be activated or deactivated.
Power Consumption
The power dissipation is the sum of three basic contributions : P = Pcore + Pio + Ppci
•
•
Pcore represents the contribute due to the internal activity.
Pio represents the contribute due to the IO pads and output load current, except the
PCI bus.
•
Ppci represents the contribute due to the PCI pads and output load current.
The following table gives the estimated current consumption for different conditions. The
values are coming from estimation and calculation and not from real measurement.
Table 114. Power Dissipation
Mode
Typical conditions
Worst Conditions
P Core
P I/O
P PCI
P Core
P I/O
P PCI
(1.8V) in W
(3.3V) in W
(3.3V) in W
(1.8V) in W
(3.3V) in W
(3.3V) in W
Operating
(100MHz)
0.6
0.2
0.1
0.8
0.3
0.2
Typical conditions : 25°C, 1.8V core, 3.3V I/O, High I/O and core activity
Worst conditions : 125°C, 1.95 V core, 3.6V I/O; High I/O and core activity
In idle mode (100 MHz external clock), the core power consumption is 0.5W in typical
conditions and 0.7W in worst case conditions.
Decoupling capacitance Two main frequencies are involved in the AT697 processor environment :
•
33MHz from the PCI interface
•
100MHz from the master clock of the processor (either from PLL or directly from
resonator input)
The following hypothesis is taken for the calculation of the decoupling capacitance :
•
•
1.5nH is issued from the connection of the capacitor to the PCB
1.5nH is issued from the capacitor intrinsic inductance
132
AT697E
4226G–AERO–05/09
AT697
Figure 53. Capacitor description
1.5nH
0.75nH
0.75nH
capacitor
PCB
This hypothesis corresponds to a capacitor connected to two micro-vias on a PCB.
The filter defined by the self and the decoupling capacitor shall be able to filter the characteristic
frequencies of the application. Each frequency to filtre is defined by :
1
------------------
fc =
·
·
2π LC
•
•
L : the inductance equivalent to the global inductance on the VSS/VDD (VSS/VCC)
line.
C : the decoupling capacitance.
For a processor running at 100MHz with a PCI interface at a characteristic frequency of 33MHz
and considering that power supply pins ar grouped by multiple of four, the decoupling capaci-
tance to set are :
•
•
33nF for 33MHz decoupling
3nF for 100MHz decoupling
Capacitance Rating
Parameter
CIN
Description
MAX
5pF
5pF
7pF
7pF
Standard Input Capacitance
Standard Input/Output Capacitance
PCI Input Capacitance
CIO
CINp
CIOp
PCI Input/Output Capacitance
133
4226G–AERO–05/09
AC Characteristics
The AT697 processor implements a single event transient protection mechanism. The
influence of this protection is reflected by the timing figures presented in the following
tables.
The following tables show the timing figures for the skew condition natural and
maximum.
Natural Skew
Test Conditions
•
•
•
Natural Skew
Temperature range : -55°C to 125°C
Voltage range :
–
–
I/O: 3,3V +/- 0,30V
Core: 1,8V +/- 0,15V
•
•
Clock frequency : 100MHz
Output load : 30pF
Table 115. AC Characteristics - Natural Skew
Min
(ns)
Max
Reference edge
Parameter
t1
(ns)
Comment
CLK Period with PLL disable
CLK Period with PLL enable
CLK Low and High pulse width - PLL disabled
CLK Low and High pulse width - PLL enabled
SDCLK Period
(‘+’ for rising edge)
10
40
4.5
18
10
2
t1_p
t2
50
t2_p
t3
t4
7
SDCLK output delay - PLL disabled
PLL setup time
CLK
t5
1.107
t6
1*t3
1.5
2
Reset Pulse Width
t10
t11
7
9
A[27:0] output delay
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
D[31:0] and CB[7:0] output delay
D[31:0] and CB[7:0] setup time
D[31:0] and CB[7:0] hold time during load/fetch
D[31:0] and CB[7:0] hold time during write
OE*, READ and WRITE* output delay
ROMS*[1:0] output delay
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
4.5
0
2
9
7
2
2
6.5
9,5
6
2
RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay
IOS* output delay
2
4
BRDY* setup time
0
BRDY* hold time
3
9
SDCAS* output delay
134
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4226G–AERO–05/09
AT697
Min
(ns)
Max
(ns)
Reference edge
Parameter
t22
Comment
SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay
BEXC* setup time
(‘+’ for rising edge)
2
4
8,5
SDCLK +
t23
SDCLK +
t24
0
BEXC* hold time
SDCLK +
t25
2.5
4.5
0
10
PIO[15:0] output delay
SDCLK +
t26
PIO[15:0] setup time
SDCLK +
t27
PIO[15:0] hold time during load
PIO[15:0] hold time during write
PCI_CLK Period
SDCLK +
t28
2.5
33
14.5
4
SDCLK +
t101
t102
t110
t111
t112
t113
t114
t115
PCI_CLK Low and High pulse width
A/D[31:0] and C/BE[3:0] output delay
A/D[31:0] and C/BE[3:0] setup time
A/D[31:0] and C/BE[3:0] hold time
FRAME*, PAR, PERR*, SERR*, STOP* and DEVSEL* output delay
IRDY* and TRDY* output delay
REQ* output delay
12
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
6
0
4
11
11
12
4
4
FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL*
setup time
t116
7
PCI_CLK +
t117
t118
7
6
IRDY* and TRDY* setup time
GNT* setup time
PCI_CLK +
PCI_CLK +
FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL*
hold time
t119
0
PCI_CLK +
t120
t121
0
0
IRDY* and TRDY* hold time
GNT* hold time
PCI_CLK +
PCI_CLK +
135
4226G–AERO–05/09
Maximum Skew
Test Conditions
•
•
•
Maximum Skew Programmed
Temperature range : -55°C to 125°C
Voltage range :
–
–
I/O: 3,3V +/- 0,30V
Core: 1,8V +/- 0,15V
•
•
Clock frequency : 83MHz
Output load : 30pF
Table 116. AC Characteristics - Maximum Skew
Min
(ns)
Max
Reference edge
Parameter
t1
(ns)
Comment
CLK Period with PLL disable
CLK Period with PLL enable
CLK Low and High pulse width - PLL disabled
CLK Low and High pulse width - PLL enabled
SDCLK Period
(‘+’ for rising edge)
12
48
5.4
21
12
2
t1_p
t2
50
t2_p
t3
t4
7
SDCLK output delay - PLL disabled
PLL setup time
CLK
t5
1.107
t6
1* t3
1.5
2
Reset Pulse Width
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
8
A[27:0] output delay
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
SDCLK +
11
D[31:0] and CB[7:0] output delay
D[31:0] and CB[7:0] setup time
D[31:0] and CB[7:0] hold time
D[31:0] and CB[7:0] hold time during write
OE*, READ and WRITE* output delay
ROMS*[1:0] output delay
4.5
0
2
11
8.5
8
2
2
2
10
8
RAMS*[4:0], RAMOE*[4:0] and RWE*[3:0] output delay
IOS* output delay
2
3
BRDY* setup time
0
BRDY* hold time
3
10
SDCAS* output delay
2
9.5
SDCS*[1:0], SDRAS*, SDWE* and SDDQM*[3:0] output delay
BEXC* setup time
4
0
BEXC* hold time
2.5
4.5
11
PIO[15:0] output delay
PIO[15:0] setup time
136
AT697E
4226G–AERO–05/09
AT697
Min
(ns)
Max
(ns)
Reference edge
Parameter
t27
Comment
PIO[15:0] hold time
(‘+’ for rising edge)
0
2.5
33
14.5
4
SDCLK +
t28
PIO[15:0] hold time during write
PCI_CLK period
SDCLK +
t101
t102
t110
PCI_CLK low and high pulse width
A/D[31:0] and C/BE[3:0] output delay
A/D[31:0] and C/BE[3:0] setup time
A/D[31:0] and C/BE[3:0] hold time
FRAME*, PAR, PERR*, SERR*, STOP* and DEVSEL* output delay
IRDY* and TRDY* output delay
REQ* output delay
13
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
PCI_CLK +
t111
6
t112
1
t113
4
12
12.5
13
t114
4
t115
4
FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL*
setup time
t116
7.5
PCI_CLK +
t117
t118
7.5
6
IRDY* and TRDY* setup time
GNT* setup time
PCI_CLK +
PCI_CLK +
FRAME*, LOCK*, PAR, PERR*, SERR*, IDSEL*, STOP* and DEVSEL*
hold time
t119
0.5
PCI_CLK +
t120
t121
0.5
0.5
IRDY* and TRDY* hold time
GNT* hold time
PCI_CLK +
PCI_CLK +
137
4226G–AERO–05/09
Timing Derating
Depending on the capacitance load on each pin, the timing figures change. The follow-
ing figures summarize the timing derating versus the load capacitance.
Figure 54. Timing derating (1/2)
A[27:0]
Timing Derating
8
6
4
2
0
-2
Load (pF)
CB[7:0]
Timing Derating
D[31:0]
8
6
4
c
2
0
-2
Load (pF)
DSUACT
Timing Derating
DSUTX
30
20
10
0
-10
Load (pF)
138
AT697E
4226G–AERO–05/09
AT697
Figure 55. Timing derating (2/2)
Timing Derating
RAMS[4:0]*
15
10
5
RAMOE[4:0]*
SDDQM[3:0]
SDCAS*
SDRAS
SDWE*
SDCS[1:0]*
RAMS[4:0]*
RAMOE[4:0]*
SDDQM[3:0]
SDCAS*
0
SDRAS
SDWE*
-5
SDCS[1:0]*
Load (pF)
Timing Derating
4
3
RWE[3:0]*
ROMS[1:0]*
IOS*
2
OE*
1
READ
0
WRITE*
-1
Load (pF)
PIO[15:0]
Timing Derating
15
10
5
0
-5
Load (pF)
139
4226G–AERO–05/09
Timing Diagrams
Diagram List
•
•
•
Reset Sequence
Clock Input without PLL
Clock Input with PLL
•
•
•
Fetch, Read and Write from/to 32-bit PROM - 0 Waitstate
Fetch, Read and Write from/to 32-bit PROM - n Waitstates
Fetch, Read and Write from/to 32-bit PROM - n Waitstates + BRDY*
•
•
•
•
•
Fetch from 8-bit PROM with EDAC disabled - n Waitstates
Word Write to 8-bit PROM with EDAC disabled - n Waitstates
Byte and Half Word Write to 8-bit PROM with EDAC disabled - n Waitstates
Fetch from 8-bit PROM with EDAC enabled - n Waitstates
Fetch from 16-bit PROM - n Waitstates
•
•
Fetch, Read and Write from/to 32-bit SRAM - 0 Waitstate
Fetch, Read and Write from/to 32-bit SRAM - n Waitstates
•
•
Burst of fetches and Write from/to 32-bit SRAM - 0 Waitstate
Burst of fetches and Write from/to 32-bit SRAM - n Waitstates
•
•
SDRAM Read (or Fetch) with Precharge ; CL = 3
SDRAM Write with Precharge ; CL = 3
•
•
•
Fetch from ROM, Read and Write from/to 32-bit I/O - 0 Waitstate
Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates
Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates + BRDY*
140
AT697E
4226G–AERO–05/09
AT697
Figure 56. Reset Sequence
t3
SDCLK
t6
RESET*
Figure 57. Clock Input without PLL
t1
t2
t2
CLK
t4
t4
t4
t4
t4
t4
SDCLK
BYPASS
LOCK
Figure 58. Clock Input with PLL
t1_p
t2_p
t2_p
CLK
t3
SDCLK
t5
PLOCK
BYPASS
PDIV4
VCC
141
4226G–AERO–05/09
Figure 59. Fetch, Read and Write from 32-bit PROM - 0 Waitstate
Fetch Inst 0
Load Data
Fetch Inst 1
Write Data
SYSCLK
A[27:0]
ROMS0*
OE*
t10
t16
t15
t10
t16
t15
t10
t16
t15
t10
t16
Inst Addr 0
Data Addr 0
Inst Addr 1
Data Addr 1
t16
t15
t16
t16
t15
t16
t15
t15
t15
t11
t15
WRITE*
READ
t15
t15
t15
t15
t15
t13
t13
t13
t12
t12
t12
t14
t14
D[31:0]
CB[7:0]
Inst 0
Data
Inst 1
WData
t13
t13
t13
t12
t12
CB
t12
t11
WCB
CB In
CB In
Figure 60. Fetch, Read and Write from 32-bit PROM - n Waitstates
Fetch Inst 0
Load Data
n WS
Fetch Inst 1
n WS
Write Data
n WS
n WS
t3
SYSCLK
A[27:0]
ROMS0*
OE*
t10
t16
t15
t10
t16
t15
t10
t16
t15
t10
t16
Inst Adr 0
Data Addr 1
Inst Adr 1
Data Addr 2
t16
t15
t16
t15
t16
t15
t16
t15
t15
WRITE*
READ
t15
t15
t15
t15
t15
t15
t13
t13
t13
t12
Inst
t12
Dat
t12
Inst
t11
t11
t14
t14
D[31:0]
WDat
WCB
t13
t13
t13
t12
CB
t12
CB
t12
CB
CB[7:0]
142
AT697E
4226G–AERO–05/09
AT697
Figure 61. Fetch, Read and Write from 32-bit PROM - n Waitstates + BRDY*
Fetch Inst 0
n WS
Load Data
n WS
Fetch Inst 1
n WS
brdy
brdy
brdy
SYSCLK
A[27:0]
ROMS0*
OE*
t10
t16
t15
t10
t16
t15
t10
t16
t15
t10
InsAddr 0
DatAddr 1
InsAddr 1
t16
t15
t16
t15
t16
t15
t16
WRITE*
READ
t15
t15
t15
t15
t15
t15
t20
t19
t20
t19
t20
t19
BRDY*
D[31:0]
CB[7:0]
t13
t13
t13
t13
t12
Inst
t12
t12
Inst
Data
t13
t13
t12
CB
t12
CB
t12
CB
Figure 62. Fetch from 8-bit PROM with EDAC disabled - n Waitstates
Fetch Inst 0
Fetch Inst 1
n WS
Fetch Inst 2
n WS
Fetch Inst 3
n WS
n WS
t3
SYSCLK
A[27:0]
t10
t10
t16
t15
t10
t16
t15
t10
t16
t15
Inst Adr 0
Inst Adr 1
Inst Adr 2
Inst Adr 3
t16
t15
t16
t15
t16
t15
t16
t15
t16
t15
ROMS0*
OE*
WRITE*
t15
t15
t15
t15
t15
t15
t15
t15
READ
t13
t13
t13
t13
t12
Inst
t12
Inst
t12
Inst
t12
Inst
D[31:0]
143
4226G–AERO–05/09
Figure 63. Word Write to 8-bit PROM with EDAC disabled - n Waitstates
Store Byte 0
Store Byte 1
n WS
Store Byte 2
n WS
Store Byte 3
n WS
n WS
t3
SYSCLK
A[27:0]
t10
t16
t10
t16
t10
t16
t10
t16
Addr Bye0
Addr Bte1
Addr Bte2
Addr Bte3
t16
t15
t16
t15
t16
t15
t16
t15
ROMS0*
OE*
t15
t15
t15
t15
WRITE*
READ
t11
t14
t11
t14
t11
t14
t11
t14
D[31:24]
Byte 0
Byte 1
Byte 2
Byte 3
Figure 64. Byte and Half Word Write to 8-bit PROM with EDAC disabled - n Waitstates
Store By te
Ram Fetch
n WS
Store Half Word By te0
n WS
Store Half Word By te1
n WS
n WS
t3
SYSCLK
A[27:0]
RAMS0*
RAMOE0*
ROMS0*
OE*
t10
t10
t17
t17
t10
t10
By te Adr
Inst Adr 1
Inst Adr 2
Inst Adr 3
t17
t17
t16
t16
t15
t16
t16
t15
t16
t16
t15
t15
t15
t15
t15
t15
t15
t15
WRITE*
READ
t13
t11
t14
t12
Inst
t11
HW - Bte 0
t14
t11
HW - Bte 1
t14
By
D[31:24]
D[23:0]
Inst
144
AT697E
4226G–AERO–05/09
AT697
Figure 65. Fetch from 8-bit PROM with EDAC enabled - n Waitstates
Fetch Inst 0
Fetch Inst 1
n WS
Fetch Inst 2
n WS
Fetch Inst Byte3
n WS
Load Checkbit
n WS
t3
SYSCLK
A[27:0]
t10
t16
t14
t10
t16 t16
t14 t14
t10
t16 t16
t14 t14
t10
t10
t16 t16
t14 t14
Inst Adr 0
Inst Adr 1
Inst Adr 2
Inst Adr 3
CB Adr
t16 t16
t14 t14
t16
t14
ROMS0*
OE*
WRITE*
t14
t14 t14
t13
t14 t14
t13
t14 t14
t13
t14 t14
t13
t14
READ
t13
t12
CB
t12
t12
t12
t12
D[31:24]
Ins
Ins
Ins
Ins
Figure 66. Fetch from 16-bit PROM - n Waitstates
Fetch Inst 0
Fetch Inst 1
n WS
t3
n WS
SYSCLK
A[27:0]
t10
t10
t16
t14
Inst Add0
Inst Add1
t16
t14
t16
t14
t16
t14
ROMS0*
OE*
WRITE*
t14
t14
t14
t14
READ
t13
t12
Inst HW0
t13
t12
Inst HW1
D[31:16]
145
4226G–AERO–05/09
Figure 67. Fetch, Read and Write from/to 32-bit SRAM - 0 Waitstate
Fetch Inst 0
Load Data
Fetch Inst 1
Write Data
SYSCLK
A[27:0]
t10
t17
t17
t10
t17
t17
t10
t17
t17
t10
t17
Inst Addr 0
Data Addr 1
Inst Addr 1
Data Addr 2
t17
t17
t17
t17
t17
t17
RAMS0*
RAMOE0*
RWE[3:0]*
t17
t17
t11
t17
t14
t14
t13
t13
t13
t12
t12
t12
D[31:0]
CB[7:0]
Inst 0
Data
Inst 1
WData
t13
t13
t13
t12
t12
CB
t12
t11
WCB
CB In
CB In
Figure 68. Fetch, Read and Write from/to 32-bit SRAM - n Waitstates
Fetch Inst 0
Load Data
n WS
Fetch Inst 1
n WS
Write Data
n WS
n WS
t3
SYSCLK
A[27:0]
t10
t17
t17
t10
t17
t17
t10
t17
t17
t10
t17
Inst Adr 0
Data Addr 1
Inst Adr 1
Data Addr 2
t17
t17
t17
t17
t17
t17
t17
RAMS0*
RAMOE0*
RWE[3:0]*
t17
t17
t14
t14
t13
t13
t13
t12
Inst
t12
Dat
t12
Inst
t11
t11
D[31:0]
CB[7:0]
WDat
WCB
t13
t13
t13
t12
CB
t12
CB
t12
CB
146
AT697E
4226G–AERO–05/09
AT697
Figure 69. Burst of RAM Fetches and RAM Write Sequence - 0 Waitstate
Fetch Inst 0
Load Data
Fetch Inst 1
Write Data
SYSCLK
A[27:0]
t10
t17
t17
t10
t10
t10
t17
Inst Addr 0
Data Addr 0
Inst Addr 1
Data Addr 1
t17
t17
t17
RAMS0*
RAMOE0*
RWE[3:0]*
t17
t11
t17
t14
t14
t13
t13
t13
t13
t13
t12
t12
t12
D[31:0]
CB[7:0]
Inst 0
Data
Inst 1
WData
t13
t12
t12
CB
t12
t11
WCB
CB In
CB In
Figure 70. Burst of RAM Fetches and RAM Write Sequence - n Waitstates
Fetch Inst 0
Load Data
n WS
Fetch Inst 1
n WS
Write Data
n WS
n WS
t3
SYSCLK
A[27:0]
t10
t17
t17
t10
t10
t10
t17
Inst Adr 0
Data Addr 1
Inst Adr 1
Data Addr 2
t17
t17
t17
RAMS0*
RAMOE0*
RWE[3:0]*
t17
t17
t14
t14
t13
t13
t13
t13
t13
t12
Inst
t12
Dat
t12
Inst
t11
t11
D[31:0]
CB[7:0]
WDat
WCB
t13
t12
CB
t12
CB
t12
CB
147
4226G–AERO–05/09
Figure 71. SDRAM Read (or Fetch) with Precharge - Burst length = 1; CL = 3
1
2
3
4
5
6
7
8
9
10
11
12
13
trp
14
15
1
Trcd
tcas
Tras
Activate
Read
precharge
activate
SDCLK
Memory- A[16:15]
A[14:2]
t10
ba
t10
ba
t10
ba
t10
ba
t10
t10
co
t10
row
row
t22
t22
t22
t22
t22
t22
t22
t22
t22
t22
t22
SDCS*
SDRAS*
t22
t22
t22
t21
t21
SDCAS*
t22
t22
t22
t22
SDWE*
t22
SDDQM[3:0]*
D[31:0]
t12
t12
d1
148
AT697E
4226G–AERO–05/09
AT697
Figure 72. SDRAM Write with Precharge - Burst length = 1; CL = 3
1
2
3
4
5
6
7
8
9
10
11
12
13
trp
14
15
1
trc
Tras
Trcd
tcas
tdpl
Activate
Write
precharge
activate
SDCLK
Memory- A[16:15]
A[14:2]
t10
ba
ba
co
ba
ba
t10
row
row
t22
t22
t22
t22
t22
t22
t22
t22
t22
t22
SDCS*
SDRAS*
SDCAS*
t22
t22
t22
t22
t21
t22
t21
t22
t22
22
t22
22
SDWE*
SDDQM[3:0]*
D[31:0]
22
t11
d1
149
4226G–AERO–05/09
Figure 73. Fetch from ROM, Read and Write from/to 32-bit I/O - 0 Waitstate
Fetch Inst 0
Load Data
Fetch Inst 1
Write Data
SYSCLK
A[27:0]
ROMS0*
IOS*
t10
t16
t10
t10
t16
t10
Inst Addr 0
Data Addr 1
Inst Addr 1
Data Addr 2
t16
t15
t15
t16
t15
t15
t18
t18
t18
t18
t15
t15
t15
t15
t15
t15
t15
OE*
t15
t15
t14
WRITE*
READ
t15
t13
t13
t13
t12
t12
t12
t11
WData
D[31:0]
Inst 0
Data
Inst 1
Figure 74. Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates
Fetch Inst 0
Load Data
n WS
Fetch Inst 1
n WS
Write Data
n WS
n WS
t3
SYSCLK
A[27:0]
ROMS0*
IOS*
t10
t10
t10
t16
t10
Inst Adr 0
Data Adr 1
Inst Adr 1
Data Adr 2
t16
t15
t15
t16
t16
t15
t15
t18
t18
t15
t18
t18
t15
t15
t15
t15
t15
t15
OE*
t15
t15
WRITE*
READ
t15
t13
t13
t13
t12
Inst
t12
Data
t12
Inst
t11
t14
D[31:0]
WDat
150
AT697E
4226G–AERO–05/09
AT697
Figure 75. Fetch from ROM, Read and Write from/to 32-bit I/O - n Waitstates + BRDY*
Fetch Inst 0
n WS
Load Data
n WS
Fetch Inst 1
n WS
Write Data
n WS
brdy
brdy
brdy
brdy
SYSCLK
A[27:0]
ROMS0*
IOS*
t10
t16
t10
t10
t16
t10
InsAddr 0
DaAddr 1
InsAddr 1
DaAddr 2
t16
t15
t15
t16
t15
t15
t18
t18
t15
t18
t18
t15
t15
t15
t15
t15
t15
OE*
t15
t15
WRITE*
READ
t15
t20
t19
t20
t19
t20
t19
t20
t19
BRDY*
D[31:0]
t13
t13
t13
t12
Inst
t12
Dat
t12
Inst
t11
t14
Wata
151
4226G–AERO–05/09
Ordering
Information
Table 117. Possible Order Entries
Supply Voltage
(core / IOs)
Temperature
Range
Maximum Speed
(MHz)
Part-Number
Packaging
MCGA349
MCGA349
MCGA349
MQFP256
MQFP256
MQFP256
Quality Flow
AT697E-2H-E
1.8V / 3.3V
1.8V / 3.3V
1.8V / 3.3V
1.8V / 3.3V
1.8V / 3.3V
1.8V / 3.3V
+25°C
100
100
100
100
100
100
Engineering Samples
QMLQ
5962-0722401QXB
AT697E-2H-SV
AT697E-KG-E
AT697E-KG-MQ
AT697E-KG-SV
-55°C ; +125°C
-55°C ; +125°C
+25°C
Space level B
Engineering Samples
Military Level B
Space level B
-55°C ; +125°C
-55°C ; +125°C
Datasheet Revision History
Changes from
Rev. C 08/05 to Rev. D 02/06
1. Update of electrical characteristics and timing diagrams.
Rev. D 02/06 to
Rev. E 09/06
1. Timing chronograms review for IO space and ROM space.
2. Update of electrical characteristics and timing diagrams.
Rev. F 02/09
1. Add MQFP256 pinout
2. Part number modification
152
AT697
4226G–AERO–05/09
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