AT49LV3218T-90CJ_技术文档

Features

• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

• Access Time – 85 ns

• Sector Erase Architecture

– Sixty-three 32K Word (64K Byte) Sectors with Individual Write Lockout

– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout

• Fast Word Program Time – 15 µs

• Fast Sector Erase Time – 200 ms

• Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word and Fifteen 32K Word Sectors

Memory Plane B: Forty-eight 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low-power Operation

32-megabit

(2M x 16/4M x 8)

3-volt Only

– 25 mA Active

– 10 µA Standby

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• RESET Input for Device Initialization

• Sector Lockdown Support

Flash Memory

• TSOP and CBGA Package Options

• Top or Bottom Boot Block Configuration Available

• 128-bit Protection Register

AT49BV3218

AT49BV3218T

AT49LV3218

AT49LV3218T

Not Recommended

for New Design

Use AT49BV/LV320(T)

Description

The AT49BV/LV3218(T) is a 2.65- to 3.3-volt (BV)/3.0V to 3.6V (LV) 32-megabit Flash

memory organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits

each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The

memory is divided into 71 sectors for erase operations. The device is offered in 48-

lead TSOP and 48-ball CBGA packages. The device has CE and OE control signals to

avoid any bus contention. This device can be read or reprogrammed using a single

2.65V power supply, making it ideally suited for in-system programming.

or AT49BV/LV321(T)

Contact Atmel to discuss

the latest design in trends

and options

Pin Configurations

Pin Name

A0 - A20

CE

Function

Addresses

Chip Enable

OE

Output Enable

WE

Write Enable

RESET

RDY/BUSY

VPP

Reset

READY/BUSY Output

Optional Power Supply

I/O0 - I/O14

I/O15 (A-1)

BYTE

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

NC

Rev. 2452F–FLASH–10/02

1

TSOP Top View

CBGA Top View

Type 1

2

3

4

5

6

1

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

BYTE

GND

I/O15/A-1

I/O7

A

B

C

D

E

F

3

A7 RDY/BUSY

A9

A8

A13

A12

A3

A4

WE

RESET

VPP*

A19

4

5

6

I/O14

I/O6

A17

A6

NC*

A18

7

A8

8

I/O13

I/O5

A2

A10

A11

I/O7

I/O14

A14

A19

A20

WE

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

A5

A20

A15

A1

RESET

VPP*

NC*

RDY/BUSY

A18

A17

A7

VCC

I/O11

I/O3

I/O0

I/O8

I/O9

I/O1

I/O2

I/O10

I/O11

I/O3

A16

A0

I/O5

I/O10

I/O2

I/O9

CE

OE

VSS

I/O12

VCC

I/O4

BYTE

I/O1

G

H

A6

I/O8

I/O13 I/O15/A-1

A5

I/O0

A4

OE

A3

GND

CE

I/O6

VSS

A2

A1

A0

Note:

*Either pin 13 or pin 14 (TSOP package) or ball B3 or ball C4 (CBGA package) can be connected to V_PPor both pins can be

unconnected.

The device powers on in the read mode. Command sequences are used to place the

device in other operation modes such as program and erase. The device has the capa-

bility to protect the data in any sector (see Sector Lockdown section).

The device is segmented into two memory planes. Reads from memory plane B may be

performed even while program or erase functions are being executed in memory plane

A and vice versa. This operation allows improved system performance by not requiring

the system to wait for a program or erase operation to complete before a read is per-

formed. To further increase the flexibility of the device, it contains an Erase Suspend

feature. This feature will put the erase on hold for any amount of time and let the user

read data from or program data to any of the remaining sectors within the same memory

plane. There is no reason to suspend the erase operation if the data to be read is in the

other memory plane. The end of a program or an erase cycle is detected by the

Ready/Busy pin, Data Polling or by the toggle bit.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the

requirement of entering the three-byte program sequence is offered to further improve

programming time. After entering the six-byte code, only single pulses on the write con-

trol lines are required for writing into the device. This mode (Single Pulse Byte/Word

Program) is exited by powering down the device, or by pulsing the RESET pin low for a

minimum of 500 ns and then bringing it back to V_CC. Erase and Erase Suspend/Resume

commands will not work while in this mode; if entered they will result in data being pro-

grammed into the device. It is not recommended that the six-byte code reside in the

software of the final product but only exist in external programming code.

The BYTE pin controls whether the device data I/O pins operate in the byte or word con-

figuration. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0 -

I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the

device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and con-

trolled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is

used as an input for the LSB (A-1) address function.

2

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A20

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

REGISTER

OE

RESET

BYTE

ADDRESS

LATCH

DATA

RDY/BUSY

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VPP

VOLTAGE SWITCH

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

PLANE B

SECTORS

PLANE A SECTORS

3

2452F–FLASH–10/02

Device

Operation

READ: The AT49BV/LV3218(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for

the command codes). The command sequences are written by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of

CE or WE. Standard microprocessor write timings are used. The address locations used in the

command sequences are not affected by entering the command sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t_EC

.

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sec-

tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t_SEC. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t_BPcycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle.

4

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write protected

region is optional to the user.

At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see Software Product Identification Entry and Exit sections) a read from address loca-

tion 00002H within a sector will show if programming the sector is locked down. If the data on

I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown

feature has been enabled and the sector cannot be programmed. The software product identi-

fication exit code should be used to return to standard operation.

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to

interrupt a sector erase operation and then program or read data from a different sector within

the same plane. Since this device has a dual-plane architecture, there is no need to use the

Erase Suspend feature while erasing a sector when you want to read data from a sector in the

other plane. After the Erase Suspend command is given, the device requires a maximum time

of 15 µs to suspend the erase operation. After the erase operation has been suspended, the

plane that contains the suspended sector enters the erase-suspend-read mode. The system

can then read data or program data to any other sector within the device. An address is not

required during the Erase Suspend command. During a sector erase suspend, another sector

cannot be erased. To resume the sector erase operation, the system must write the Erase

Resume command. The Erase Resume command is a one-bus cycle command, which does

require the plane address (determined by A20 - A19). The device also supports an erase sus-

pend during a complete chip erase. While the chip erase is suspended, the user can read from

any sector within the memory that is protected. The command sequence for a chip erase sus-

pend and a sector erase suspend are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” on page 13 (for hardware operation) or “Software Product

Identification Entry/Exit” on page 20. The manufacturer and device codes are the same for

both modes.

128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used

for security purposes in system design. The protection register is divided into two 64-bit

blocks. The two blocks are designated as block A and block B. The data in block A is non-

changeable and is programmed at the factory with a unique number. The data in block B is

programmed by the user and can be locked out such that data in the block cannot be repro-

grammed. To program block B in the protection register, the four-bus cycle Program

Protection Register command must be used as shown in the Command Definition table on

page 7. To lock out block B, the four-bus cycle Lock Protection Register command must be

used as shown in the Command Definition table. Data bit D1 must be zero during the fourth

5

2452F–FLASH–10/02

bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Pro-

tection Register Addressing Table” on page 8 for the address locations in the protection

register. To read the protection register, the Product ID Entry command is given followed by a

normal read operation from an address within the protection register. After reading the protec-

tion register, the Product ID Exit command must be given prior to performing any other

operation.

DATA POLLING: The AT49BV/LV3218(T) features Data Polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte/word loaded will result

in the complement of the loaded data on I/O7. Once the program cycle has been completed,

true data is valid on all outputs and the next cycle may begin. During a chip or sector erase

operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device. Data Polling may begin at any

time during the program cycle. Please see “Status Bit Table” on page 21 for more details.

TOGGLE BIT: In addition to Data Polling, the AT49BV/LV3218(T) provides another method

for determining the end of a program or erase cycle. During a program or erase operation,

successive attempts to read data from the same memory plane will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling and

valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle

bit that is available on I/O6. While a sector is erase suspended, a read or a program operation

from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on

page 21 for more details.

RDY/BUSY: An open-drain Ready/Busy output pin provides another method of detecting the

end of a program or erase operation. RDY/BUSY is actively pulled low during the internal pro-

gram and erase cycles and is released at the completion of the cycle. The open-drain

connection allows for OR-tying of several devices to the same RDY/BUSY line.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against

inadvertent programs to the AT49BV/LV3218(T) in the following ways: (a) V_CCsense: if V_CCis

below 1.8V (typical), the program function is inhibited. (b) V_CCpower-on delay: once V_CChas

reached the V_CCsense level, the device will automatically time out 10 ms (typical) before pro-

gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will

not initiate a program cycle.

INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and

control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the

operation of the device. The I/O lines can only be driven from 0 to V_CC+ 0.6V.

6

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Command Definition in Hex⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles

Addr

555

Data

D_OUT

AA

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

1

6

4

Chip Erase

AAA⁽²⁾

AAA

55

555

80

A0

555

AA

D_IN

AAA

55

555

SA⁽³⁾⁽⁴⁾

10

30

Sector Erase

555

AA

Byte/Word Program

555

AA

AAA

Addr

Enter Single Pulse

Program Mode

6

1

555

AA

D_IN

AAA

55

555

80

555

AA

AAA

55

555

A0

60

Single Pulse

Byte/Word Program

Addr

Sector Lockdown

Erase Suspend

Erase Resume

6

1

3

1

555

XXX

PA⁽⁵⁾

555

AA

B0

30

AAA

55

555

80

555

AA

SA⁽³⁾⁽⁴⁾

Product ID Entry

Product ID Exit⁽⁶⁾

AA

F0

AAA

55

555

90

F0

555

XXX

Program Protection

Register

4

555

AA

AAA

55

555

C0

90

Addr

080

80

D_IN

X0

Lock Protection

Register - Block B

Status of Block B

Protection

(7)

D_OUT

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.

The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are Don’t Care

in the word mode. Address A20 through A11 and A-1 are Don’t Care in the byte mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 9 -12

for details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power

cycled.

5. PA is the plane address (A20 - A19).

6. Either one of the Product ID Exit commands can be used.

7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V_CC+ 0.6V

Voltage on OE and V_PP

with Respect to Ground ...................................-0.6V to +13.0V

7

2452F–FLASH–10/02

Protection Register Addressing Table

Word

Use

Factory

User

Block

A7

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

1

0

1

2

3

4

5

6

7

A

B

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

User

1

0

1

0

User

1

0

1

User

1

0

1

0

Note:

1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A20 - A8 = 0.

8

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

AT49BV/LV3218 – Sector Address Table

x8

x16

Plane

A

B

Sector

SA0

Size (Bytes/Words)

8K/4K

Address Range (A20 - A-1)

Address Range (A20 - A0)

000000 - 001FFF

002000 - 003FFF

004000 - 005FFF

006000 - 007FFF

008000 - 009FFF

00A000 - 00BFFF

00C000 - 00DFFF

00E000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

00000 - 00FFF

01000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 04FFF

05000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

SA1

8K/4K

SA2

8K/4K

SA3

8K/4K

SA4

8K/4K

SA5

8K/4K

SA6

8K/4K

SA7

8K/4K

SA8

64K/32K

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

9

2452F–FLASH–10/02

AT49BV/LV3218 – Sector Address Table (Continued)

x8

x16

Plane

B

Sector

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Size (Bytes/Words)

64K/32K

Address Range (A20 - A-1)

1E0000 - 1EFFFF

1F0000 - 1FFFFF

200000 - 20FFFF

210000 - 21FFFF

220000 - 22FFFF

230000 - 23FFFF

240000 - 24FFFF

250000 - 25FFFF

260000 - 26FFFF

270000 - 27FFFF

280000 - 28FFFF

290000 - 29FFFF

2A0000 - 2AFFFF

2B0000 - 2BFFFF

2C0000 - 2CFFFF

2D0000 - 2DFFFF

2E0000 - 2EFFFF

2F0000 - 2FFFFF

300000 - 30FFFF

310000 - 31FFFF

320000 - 32FFFF

330000 - 33FFFF

340000 - 34FFFF

350000 - 35FFFF

360000 - 36FFFF

370000 - 37FFFF

380000 - 38FFFF

390000 - 39FFFF

3A0000 - 3AFFFF

3B0000 - 3BFFFF

3C0000 - 3CFFFF

3D0000 - 3DFFFF

3E0000 - 3EFFFF

3F0000 - 3FFFFF

Address Range (A20 - A0)

F0000 - F7FFF

F8000 - FFFFF

100000 - 107FFF

108000 - 10FFFF

110000 - 117FFF

118000 - 11FFFF

120000 - 127FFF

128000 - 12FFFF

130000 - 137FFF

138000 - 13FFFF

140000 - 147FFF

148000 - 14FFFF

150000 - 157FFF

158000 - 15FFFF

160000 - 167FFF

168000 - 16FFFF

170000 - 177FFF

178000 - 17FFFF

180000 - 187FFF

188000 - 18FFFF

190000 - 197FFF

198000 - 19FFFF

1A0000 - 1A7FFF

1A8000 - 1AFFFF

1B0000 - 1B7FFF

1B8000 - 1BFFFF

1C0000 - 1C7FFF

1C8000 - 1CFFFF

1D0000 - 1D7FFF

1D8000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 -1F7FFF

1F8000 - 1FFFF

10

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

AT49BV/LV3218T – Sector Address Table

x8

x16

Plane

B

Sector

SA0

Size (Bytes/Words)

64K/32K

Address Range (A20 - A-1)

Address Range (A20 - A0)

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

IE0000 - IEFFFF

1F0000 - 1FFFFF

200000 - 20FFFF

210000 - 21FFFF

220000 - 22FFFF

230000 - 23FFFF

240000 - 24FFFF

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

100000 - 107FFF

108000 - 10FFFF

110000 - 117FFF

118000 - 11FFFF

120000 - 127FFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

11

2452F–FLASH–10/02

AT49BV/LV3218T – Sector Address Table (Continued)

x8

x16

Plane

B

A

Sector

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Size (Bytes/Words)

64K/32K

8K/4K

Address Range (A20 - A-1)

250000 - 25FFFF

260000 - 26FFFF

270000 - 27FFFF

280000 - 28FFFF

290000 - 29FFFF

2A0000 - 2AFFFF

2B0000 - 2BFFFF

2C0000 - 2CFFFF

2D0000 - 2DFFFF

2E0000 - 2EFFFF

2F0000 - 2FFFFF

300000 - 30FFFF

310000 - 31FFFF

320000 - 32FFFF

330000 - 33FFFF

340000 - 34FFFF

350000 - 35FFFF

360000 - 36FFFF

370000 - 37FFFF

380000 - 38FFFF

390000 - 39FFFF

3A0000 - 3AFFFF

3B0000 - 3BFFFF

3C0000 - 3CFFFF

3D0000 - 3DFFFF

3E0000 - 3EFFFF

3F0000 - 3F1FFF

3F2000 - 3F3FFF

3F4000 - 3F5FFF

3F6000 - 3F7FFF

3F8000 - 3F9FFF

3FA000 - 3FBFFF

3FC000 - 3FDFFF

3FE000 - 3FFFFF

Address Range (A20 - A0)

128000 - 12FFFF

130000 - 137FFF

138000 - 13FFFF

140000 - 147FFF

148000 - 14FFFF

150000 - 157FFF

158000 - 15FFFF

160000 - 167FFF

168000 - 16FFFF

170000 - 177FFF

178000 - 17FFFF

180000 - 187FFF

188000 - 18FFFF

190000 - 197FFF

198000 - 19FFFF

1A0000 - 1A7FFF

1A8000 - 1AFFFF

1B0000 - 1B7FFF

1B8000 - 1BFFFF

1C0000 - 1C7FFF

1C8000 - 1CFFFF

1D0000 - 1D7FFF

1D8000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 - 1F7FFF

1F8000 - 1F8FFF

1F9000 - 1F9FFF

1FA000 - 1FAFFF

1FB000 - 1FBFFF

1FC000 - 1FCFFF

1FD000 - 1FDFFF

1FE000 - 1FEFFF

1FF000 - 1FFFFF

8K/4K

12

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

DC and AC Operating Range

AT49BV/LV3218(T)-85

-40°C - 85°C

AT49BV/LV3218(T)-90

AT49BV/LV3218(T)-11

-40°C - 85°C

Operating Temperature (Case)

V_CCPower Supply

Ind.

-40°C - 85°C

2.65V to 3.3V/3.0V to 3.6V

Operating Modes

Mode

CE

V_IL

V_IH

X

OE

V_IL

V_IH

X⁽¹⁾

X

WE

V_IH

V_IL

X

RESET

V_IH

Ai

X

I/O

Read

D_OUT

Program/Erase⁽²⁾

Standby/Program Inhibit

V_IH

D_IN

V_IH

High-Z

V_IH

X

V_IH

Program Inhibit

X

V_IL

V_IH

X

V_IH

Output Disable

Reset

X

V_IH

High-Z

X

V_IL

X

Product Identification

A1 - A20 = V_IL, A9 = V_H⁽³⁾, A0 = V_IL

A1 - A20 = V_IL, A9 = V_H⁽³⁾, A0 = V_IH

A0 = V_IL, A1 - A20 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

A0 = V_IH, A1 - A20 = V_IL

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC programming waveforms on page 19.

3. V_H= 12.0V 0.5V.

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: 00D8H - AT49BV/LV3218; 00D9H - AT49BV/LV3218T.

5. See details under “Software Product Identification Entry/Exit” on page 20.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

1

Units

µA

mA

µA

mA

µA

V

I_LI

Input Load Current

V_IN= 0V to V_CC

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Read Current

V_CCProgramming Current

V_PPInput Load Current

Input Low Voltage

V_I/O= 0V to V_CC

I_SB1

I_SB2

I_SB3

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

CE = 2.0V to V_CC, V_CC= 2.85V

f = 5 MHz; I_OUT= 0 mA

10

25

45

100

0.6

(1)

I_CC

I_CC1

I_PP1

V_IL

V_IH

Input High Voltage

2.0

V

V_OL1

V_OL2

V_OH1

V_OH2

Output Low Voltage

I_OL= 2.1 mA

I_OL= 1.0 mA

I_OH= -400 µA

I_OH= -100 µA

0.45

0.20

V

Output Low Voltage

V

Output High Voltage

2.4

2.5

V

Output High Voltage

V

Note:

1. In the erase mode, I_CCis 65 mA.

13

2452F–FLASH–10/02

AC Read Characteristics

AT49BV/LV3218(T)-85

AT49BV/LV3218(T)-90

AT49BV/LV3218(T)-11

Symbol

Parameter

Min

Max

85

Min

Max

90

Min

Max

110

50

Units

ns

t_ACC

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE to Output Float

(1)

t_CE

85

90

ns

(2)

t_OE

0

40

0

40

0

ns

(3)(4)

t_DF

25

30

ns

Output Hold from OE, CE or Address,

whichever occurred first

t_OH

t_RO

0

ns

RESET to Output Delay

100

AC Read Waveforms^(1)(2)(3)(4)

ADDRESS

ADDRESS VALID

CE

tCE

tOE

OE

tDF

tOH

tACC

tRO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Note:

1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on

_CEor by t_ACC- t_OEafter an address change without impact on t_ACC

.

t

.

3. t_DFis specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

14

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Input Test Waveforms and Measurement Level

t_R, t_F< 5 ns

Output Test Load

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

4

Max

6

Units

pF

Conditions

V_IN= 0V

C_OUT

8

12

pF

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested.

15

2452F–FLASH–10/02

AC Byte/Word Load Characteristics

Symbol

t_AS, t_OES

t_AH

Parameter

Min

0

Max

Units

ns

Address, OE Setup Time

Address Hold Time

90

0

ns

t_CS

Chip Select Setup Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Setup Time

ns

t_CH

0

ns

t_WP

50

0

ns

t_DS

ns

t_DH, t_OEH

t_WPH

Data, OE Hold Time

Write Pulse Width High

ns

35

ns

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

16

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte/Word Programming Time

Address Setup Time

15

20

t_AS

0

90

50

0

ns

t_AH

Address Hold Time

ns

t_DS

Data Setup Time

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

50

35

85

50

500

50

ns

t_WPH

Write Pulse Width High

Write Cycle Time

ns

t_WC

t_SR/W

ns

Latency between Read and Write Operations

Reset Pulse Width

ns

t_RP

ns

t_RH

Reset High Time before Read

Chip Erase Cycle Time

Sector Erase Cycle Time (4K Word Sectors)

Sector Erase Cycle Time (32K Word Sectors)

Erase Suspend Time

ns

t_EC

13

60

seconds

ms

µs

t_SEC1

t_SEC2

t_ES

90

300

15

200

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t_WP

t_BP

t_WPH

WE

A0 - A20

DATA

t

SR/W

t_AS

t_AH

t_DH

VALID

555

AAA

ADDRESS

READ ADDRESS

t_WC

t_DS

t

ACC

OUTPUT

DATA

55

INPUT DATA

AA

A0

17

2452F–FLASH–10/02

Sector or Chip Erase Cycle Waveforms

OE ⁽¹⁾

CE

t

EC

t

WP

WPH

WE

A0 - A20

DATA

t

SR/W

t

DH

AS

AH

ADDRESS

VALID

555

t

555

Note 2

AAA

WC

t

DS

OUTPUT

VALID

55

80

55

Note 3

AA

t

ACC

WORD 0

WORD 1

WORD 2

WORD 3

WORD 4

WORD 5

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 3 under Command Definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

18

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 14.

Data Polling Waveforms

20

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

OE High Pulse

ns

50

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 14.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t_OEHPspecification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

19

2452F–FLASH–10/02

Software Product Identification

Entry⁽¹⁾

Sector Lockdown Enable Algorithm⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

ADDRESS 555

TO

ADDRESS 555

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 80

TO

ADDRESS 555

LOAD DATA 90

TO

ADDRESS 555

LOAD DATA AA

TO

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

LOAD DATA 55

TO

(2)(3)(5)

MODE

ADDRESS AAA

Software Product Identification

Exit⁽¹⁾⁽⁶⁾

LOAD DATA 60

TO

SECTOR ADDRESS

OR

LOAD DATA AA

LOAD DATA F0

TO

ADDRESS 555

ANY ADDRESS

(2)

PAUSE 200 µs

EXIT PRODUCT

IDENTIFICATION

LOAD DATA 55

TO

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A20

(Don’t Care).

(4)

MODE

ADDRESS AAA

2. Sector Lockdown feature enabled.

LOAD DATA F0

TO

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

(4)

MODE

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A20

(Don’t Care).

2. A1 - A20 = V_IL.

Manufacturer Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH

.

3. The device does not remain in identification mode if pow-

ered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH(x8); 001FH(x16)

Device Code: 00D8H - AT49BV/LV3218

00D9H - AT49BV/LV3218T

Either one of the Product ID Exit commands can be used.

20

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Status Bit Table

Status Bit

I/O6

I/O7

I/O2

Read Address In

While

Plane A

Plane B

Plane A

Plane B

Plane A

Plane B

Programming in Plane A

Programming in Plane B

I/O7

DATA

I/O7

TOGGLE

DATA

1

DATA

1

DATA

TOGGLE

DATA

Erasing in Plane A

Erasing in Plane B

0

DATA

0

TOGGLE

DATA

TOGGLE

DATA

TOGGLE

Erase Suspended & Read

Erasing Sector

1

TOGGLE

DATA

TOGGLE

DATA

Erase Suspended & Read

Non-erasing Sector

DATA

Erase Suspended &

Program Non-erasing Sector

in Plane A

I/O7

DATA

I/O7

TOGGLE

DATA

TOGGLE

DATA

Erase Suspended &

Program Non-erasing Sector

in Plane B

DATA

TOGGLE

21

2452F–FLASH–10/02

AT49BV3218(T) Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

Industrial

AT49BV3218-85CI

AT49BV3218-85TI

48C16

48T

85

25

0.01

(-40° to 85°C)

Industrial

AT49BV3218-90CI

AT49BV3218-90TI

48C16

48T

90

110

85

25

0.01

(-40° to 85°C)

Industrial

AT49BV3218-11CI

AT49BV3218-11TI

48C16

48T

(-40° to 85°C)

Industrial

AT49BV3218T-85CI

AT49BV3218T-85TI

48C16

48T

(-40° to 85°C)

Industrial

AT49BV3218T-90CI

AT49BV3218T-90TI

48C16

48T

90

(-40° to 85°C)

Industrial

AT49BV3218T-11CI

AT49BV3218T-11TI

48C16

48T

110

(-40° to 85°C)

AT49LV3218(T) Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

Industrial

AT49LV3218-90CI

AT49LV3218-90TI

48C16

48T

90

25

0.01

(-40° to 85°C)

Industrial

AT49LV3218T-90CI

AT49LV3218T-90TI

48C16

48T

90

25

0.01

(-40° to 85°C)

Package Type

48C16

48T

48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)

48-lead, Plastic Thin Small Outline Package (TSOP)

22

AT49BV/LV3218(T)

2452F–FLASH–10/02

AT49BV/LV3218(T)

Packaging Information

48C16 – CBGA

E

A1 Ball ID

D

A1

Top View

A

2.00 REF

E1

Side View

A1 Ball Corner

e

2.70 REF

A

COMMON DIMENSIONS

(Unit of Measure = mm)

B

C

D

E

F

MIN

7.90

–

MAX

8.10

–

NOM

8.00

4.00

11.00

5.60

–

NOTE

SYMBOL

D1

E

E1

D

G

H

10.90

–

11.10

–

D1

A

e

–

1.20

–

6

5

4

3

2

1

A1

e

0.30

–

Øb

0.80 BSC

0.40

Bottom View

b

–

6/12/01

DRAWING NO. REV.

48C16

TITLE

2325 Orchard Parkway

San Jose, CA 95131

48C16, (Formerly 48C7), 48-ball (6 x 8 Array), 0.80 mm Pitch,

8.0 x 11.0 x 1.20 mm Chip-scale Ball Grid Array Package (CBGA)

A

R

23

2452F–FLASH–10/02

48T – TSOP

PIN 1

0º ~ 8º

c

Pin 1 Identifier

D1

D

L

b

L1

e

A2

E

GAGE PLANE

A

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

A1

MIN

–

MAX

1.20

0.15

1.05

20.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

19.80

18.30

11.90

0.50

–

1.00

Notes:

1. This package conforms to JEDEC reference MO-142, Variation DD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

20.00

18.40

12.00

0.60

D1

E

18.50 Note 2

12.10 Note 2

0.70

L

L1

b

0.25 BASIC

0.22

0.17

0.10

0.27

0.21

c

–

e

0.50 BASIC

10/18/01

DRAWING NO. REV.

48T

TITLE

2325 Orchard Parkway

San Jose, CA 95131

48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

B

R

24

AT49BV/LV3218(T)

2452F–FLASH–10/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

TEL (41) 26-426-5555

FAX (41) 26-426-5500

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

ASIC/ASSP/Smart Cards

Zone Industrielle

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Japan

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

2452F–FLASH–10/02

/xM


型号：	AT49LV3218T-90CJ
厂家：	ATMEL
描述：	Flash, 2MX16, 90ns, PBGA48, 11 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-48 内存集成电路
文件：	总25页 (文件大小：589K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49LV3218T-90CJ [ATMEL]

相关型号：

AT49LV3218T-90TI

AT49LV3218T-90TJ

AT49LV321T

AT49LV321T-90CI

AT49LV321T-90CJ

AT49LV321T-90TI

AT49LV4096

AT49LV4096-12RC

AT49LV4096-12RI

AT49LV4096-12RJ

AT49LV4096-12RL

AT49LV4096-12TC