AT49LV4096_技术文档

Features

Low Voltage Operation

•

- 2.7V Read

- 5V Program/Erase

Fast Read Access Time - 120 ns

Internal Erase/Program Control

Sector Architecture

•

- One 8K Words (16K bytes) Boot Block with Programming Lockout

- Two 8K Words (16K bytes) Parameter Blocks

- One 232K Words (464K bytes) Main Memory Array Block

Fast Sector Erase Time - 10 seconds

Word-By-Word Programming - 10 µs/Word

Hardware Data Protection

DATA Polling For End Of Program Detection

Low Power Dissipation

- 25 mA Active Current

- 50 µA CMOS Standby Current

Typical 10,000 Write Cycles

4-Megabit

(256K x 16)

3-volt Only

CMOS Flash

Memory

•

Description

The AT49BV4096 and AT49LV4096 are 3-volt, 4-megabit Flash Memories organized

as 256K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile

CMOS technology, the devices offer access times to 120 ns with power dissipation of

just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than

50 µA.

AT49BV4096

AT49LV4096

Preliminary

To allow for simple in-system reprogrammability, the AT49BV4096/LV4096 does not

require high input voltages for programming. Reading data out of the device is similar

to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus

Pin Configurations

(continued)

Pin Name

A0 - A17

CE

Function

AT49BV4096/LV4096

Addresses

Chip Enable

Output Enable

Write Enable

Reset

OE

WE

RESET

SOIC (SOP)

Program/Erase

Power Supply

V_PP

VPP

NC

A17

A7

A6

A5

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RESET

WE

2

3

Data

Inputs/Outputs

I/O0 - I/O15

NC

A8

A9

4

5

6

7

8

9

A10

A11

A12

A13

A14

A15

A16

NC

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

No Connect

A4

A3

TSOP Top View

A2

A1

A0

10

11

12

13

14

15

16

17

18

19

20

21

22

Type 1

A16

CE

GND

A15

A14

A13

1

3

5

7

9

48

46

44

42

40

NC

2

47

45

43

GND

I/O15

A12

A10

A8

4

6

OE

I/O0

I/O8

I/O1

I/O9

I/O2

I/O10

I/O3

I/O11

A11

A9

I/O7

I/O6

I/O5

I/O14

I/O13

I/O12

VCC

8

41

39

37

35

NC

10

WE

11

13

38

36

I/O4

RESET

12

14

I/O11

I/O10

I/O9

VPP

NC

I/O3

I/O2

NC

15

17

34

32

NC

A7

16

18

33

31

A17

I/O1

I/O0

A6

A4

19

21

23

30

28

26

I/O8

OE

CE

29

27

25

A5

A3

A1

20

22

24

GND

A0

0874A–5/97

A2

contention. Reprogramming the AT49BV4096/LV4096 is

performed by first erasing a block of data and then pro-

gramming on a word-by-word basis.

quence. Once the boot block programming lockout feature

is enabled, the data in the boot block cannot be changed

when input levels of 3.6 volts or less are used. The typical

number of program and erase cycles is in excess of

10,000 cycles.

The device is erased by executing the erase command

sequence; the device internally controls the erase opera-

tion. The memory is divided into three blocks for erase op-

erations. There are two 8K word parameter block sections

and one sector consisting of the boot block and the main

memory array block. The AT49BV4096/LV4096 is pro-

grammed on a word-by-word basis.

The optional 8K word boot block section includes a repro-

gramming lock out feature to provide data integrity. The

boot sector is designed to contain user secure code, and

when the feature is enabled, the boot sector is protected

from being reprogrammed.

The device has the capability to protect the data in the

boot block; this feature is enabled by a command se-

During a chip erase, sector erase, or word programming,

the V pin must be at 5V ± 10%.

PP

Block Diagram

Device Operation

READ: The AT49BV4096/LV4096 is accessed like an

EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the ad-

dress pins is asserted on the outputs. The outputs are put

in the high impedance state whenever CE or OE is high.

This dual-line control gives designers flexibility in prevent-

ing bus contention.

RESET: A RESET input pin is provided to ease some

system applications. When RESET is at a logic high level,

the device is in its standard operating mode. A low level on

the RESET input halts the present device operation and

puts the outputs of the device in a high impedance state.

When a high level is reasserted on the RESET pin, the

device returns to the Read or Standby mode, depending

upon the state of the control inputs. By applying a 12V ±

0.5V input signal to the RESET pin the boot block array

can be reprogrammed even if the boot block program lock-

out feature has been enabled (see Boot Block Program-

ming Lockout Override section).

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode de-

pending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command se-

quences are shown in the Command Definitions table

(I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying

a low pulse on the WE or CE input with CE or WE low

(respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data

is latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

ERASURE: Before a word can be reprogrammed, it must

be erased. The erased state of memory bits is a logical “1”.

The entire device can be erased by using the Chip Erase

command or individual sectors can be erased by using the

Sector Erase commands.

CHIP ERASE: The entire device can be erased at one

time by using the 6-byte chip erase software code. After

the chip erase has been initiated, the device will internally

time the erase operation so that no external clocks are re-

quired. The maximum time to erease the chip is t

.

EC

2

AT49BV/LV4096

If the boot block lockout has been enabled, the Chip Erase

will not erase the data in the boot block; it will erase the

main memory block and the parameter blocks only. After

the chip erase, the device will return to the read or standby

mode.

commands to specific addresses with specific data must

be performed. Please refer to the Command Definitions

table.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine if programming of the

boot block section is locked out. When the device is in the

software product identification mode (see Software Prod-

uct Identification Entry and Exit sections) a read from ad-

dress location 00002H will show if programming the boot

block is locked out. If the data on I/O0 is low, the boot

block can be programmed; if the data on I/O0 is high, the

program lockout feature has been enabled and the block

cannot be programmed. The software product identifica-

tion exit code should be used to return to standard opera-

tion.

SECTOR ERASE: As an alternative to a full chip erase,

the device is organized into three sectors that can be indi-

vidually erased. There are two 8K word parameter block

sections and one sector consisting of the boot block and

the main memory array block. The Sector Erase command

is a six bus cycle operation. The sector address is latched

on the falling WE edge of the sixth cycle while the 30H

data input command is latched at the rising edge of WE.

The sector erase starts after the rising edge of WE of the

sixth cycle. The erase operation is internally controlled; it

will automatically time to completion. When the boot block

programming lockout feature is not enabled, the boot

block and the main memory block will erase together (from

the same sector erase command). Once the boot region

has been protected, only the main memory array sector

will erase when its sector erase command is issued.

BOOT BLOCK PROGRAMMING LOCKOUT OVER-

RIDE: The user can override the boot block programming

lockout by taking the RESET pin to 12 ± 0.5 volts. By doing

this protected boot block data can be altered through a

chip erase, sector erase or word programming. When the

RESET pin is brought back to TTL levels the boot block

programming lockout feature is again active.

WORD PROGRAMMING: Once a memory block is

erased, it is programmed (to a logical “0”) on a word-by-

word basis. Programming is accomplished via the internal

device command register and is a 4 bus cycle operation.

The device will automatically generate the required inter-

nal program pulses.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset

happens during programming, the data at the location be-

ing programmed will be corrupted. Please note that a data

“0” cannot be programmed back to a “1”; only erase opera-

tions can convert “0”s to “1”s. Programming is completed

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT49BV4096/LV4096 features

DATA polling to indicate the end of a program cycle. Dur-

ing a program cycle an attempted read of the last byte

loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin.

During a chip or sector erase operation, an attempt to

read the device will give a “0” on I/O7. Once the program

or erase cycle has completed, true data will be read from

the device. DATA polling may begin at any time during the

program cycle.

after the specified t cycle time. The DATA polling fea-

BP

ture may also be used to indicate the end of a program

cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The de-

vice has one designated block that has a programming

lockout feature. This feature prevents programming of

data in the designated block once the feature has been

enabled. The size of the block is 8K words. This block,

referred to as the boot block, can contain secure code that

is used to bring up the system. Enabling the lockout fea-

ture will allow the boot code to stay in the device while data

in the rest of the device is updated. This feature does not

have to be activated; the boot block’s usage as a write

protected region is optional to the user. The address range

of the boot block is 00000H to 01FFFH.

TOGGLE BIT: I n a d d i t i o n t o DATA polling the

AT49BV4096/LV4096 provides another method for deter-

mining the end of a program or erase cycle. During a pro-

gram or erase operation, successive attempts to read data

from the device will result in I/O6 toggling between one

and zero. Once the program cycle has completed, I/O6 will

stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

Once the feature is enabled, the data in the boot block can

no longer be erased or programmed when input levels of

5.5V or less are used. Data in the main memory block can

still be changed through the regular programming method.

To activate the lockout feature, a series of six program

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the

AT49BV4096/LV4096 in the following ways: (a) V

CC

3

sense: if V is below 1.8V (typical), the program function

INPUT LEVELS: While operating with a 2.7V to 3.6V

power supply, the address inputs and control inputs (OE,

CE, and WE) may be driven from 0 to 5.5V without ad-

versely affecting the operation of the device. The I/O lines

CC

is inhibited. (b) V

power on delay: once V

has

CC

reached the V sense level, the device will automat-

CC

ically time out 10 ms (typical) before programming. (c)

Program inhibit: holding any one of OE low, CE high or

WE high inhibits program cycles. (d) Noise filter: pulses of

less than 15 ns (typical) on the WE or CE inputs will not

initiate a program cycle.

can only be driven from 0 to V + 0.6V.

CC

Command Definition (in Hex) ⁽¹⁾

Command Bus

Sequence Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr

Data

D_OUT

AA

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

1

6

Addr

5555

Read

2AAA

55

5555

80

5555

AA

2AAA

55

5555

10

30

Chip Erase

Sector

Erase

6

4

6

3

1

5555

xxxx

AA

F0

SA ^{(4, 5)}

Word

Program

2AAA

55

5555

A0

80

90

F0

Addr

5555

D_IN

AA

Boot Block

Lockout

2AAA

55

5555

40

(2)

Product ID

Entry

Product ID

(3)

Exit

Product ID

(3)

Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows:

I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

2. The 8K word boot sector has the address range

00000H to 01FFFH.

4. SA = sector addresses:

SA = 03XXX for PARAMETER BLOCK 1

SA = 05XXX for PARAMETER BLOCK 2

SA = 1FXXX for MAIN MEMORY ARRAY

3. Either one of the Product ID Exit commands

can be used.

5. When the boot block programming lockout feature is not

enabled, the boot block and the main memory block will erase

Absolute Maximum Ratings*

Temperature Under Bias................. -55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages

(including NC Pins)

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to V

+ 0.6V

CC

Voltage on OE

with Respect to Ground ................... -0.6V to +13.5V

4

AT49BV/LV4096

DC and AC Operating Range

AT49LV4096-12

0°C - 70°C

-40°C - 85°C

3.0V to 3.6V

N/A

AT49BV/LV4096-15

AT49BV/LV4096-20

0°C - 70°C

Com.

0°C - 70°C

-40°C - 85°C

3.0V to 3.6V

2.7V to 3.6V

Operating

Temperature (Case)

Ind.

-40°C - 85°C

3.0V to 3.6V

V

Power Supply

AT49LV4096

AT49BV4096

CC

2.7V to 3.6V

Operating Modes

RESET

V

PP

Mode

CE

OE

WE

Ai

I/O

Read

V

IL

V

IL

V

IH

X

Ai

D

OUT

IH

Program/

Erase

5V ±

10%

V

Ai

X

D

IL

IH

IL

IH

IN

(2)

Standby/Program

Inhibit

(1)

V

X

V

IH

X

High Z

IH

Program Inhibit

Output Disable

Reset

X

V

IH

IL

X

V

X

IL

V

X

High Z

IH

X

V

X

IL

Product

Identification

A1 - A17 = V_IL, A9 = V_H,⁽³⁾

A0 = V_IL

(4)

Manufacturer Code

Hardware

V

IL

V

IL

V

IH

A1 - A17 = V_IL, A9 = V_H,⁽³⁾

A0 = V_IH

(4)

Device Code

A0 = V_IL, A1 - A17 = V_IL

A0 = V_IH, A1 - A17 = V_IL

Manufacturer Code

(5)

Software

IH

(4)

Device Code

Notes: 1. X can be V_ILor V_IH.

4. Manufacturer Code: 1FH, Device Code: 92H

5. See details under Software Product Identification Entry/Exit.

2. Refer to AC Programming Waveforms.

3. V_H= 12.0V ± 0.5V.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

50

1

Units

µA

mA

V

I

LI

Input Load Current

Output Leakage Current

V

= 0V to V

CC

IN

I

= 0V to V

CC

LO

I/O

V

Standby Current CMOS

Standby Current TTL

Active Current

CE = V - 0.3V to V

CC CC

SB1

SB2

CC

CE = 2.0V to V

CC

(1)

f = 5 MHz; I

= 0 mA

OUT

25

0.8

CC

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

IL

2.0

2.4

V

IH

I

= 2.1 mA

.45

V

OL

OH

OL

= -400 µA

V

OH

Note: 1. In the erase mode, I_CCis 50 mA.

5

AC Read Characteristics

AT49LV4096-12

AT49BV/LV4096-15 AT49BV/LV4096-20

Min

Max

120

50

Min

Max

150

100

50

Min

Max

200

100

50

Symbol Parameter

Units

ns

t

Address to Output Delay

CE to Output Delay

ACC

(1)

ns

CE

OE

DF

(2)

OE to Output Delay

0

ns

(3, 4)

CE or OE to Output Float

30

ns

Output Hold from OE,

CE or Address,

t

0

ns

OH

whichever occurred first

AC Read Waveforms ^{(1, 2, 3, 4)}

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address

transition without impact on t_ACC

3. t_DFis specified from OE or CE whichever occurs first

(C_L= 5 pF).

.

2. OE may be delayed up to t_CE- t_OEafter the falling

edge of CE without impact on t_CEor by t_ACC- t_OE

4. This parameter is characterized and is not 100% tested.

after an address change without impact on t_ACC

.

Output Test Load

Input Test Waveforms and Measurement Level

t , t < 5 ns

R

F

Pin Capacitance (f = 1 MHz, T = 25°C) ⁽¹⁾

Typ

Max

6

Units

pF

Conditions

C

4

8

V

= 0V

IN

12

pF

= 0V

OUT

Note: 1. This parameter is characterized and is not 100% tested.

6

AT49BV/LV4096

AC Word Load Characteristics

Symbol

Parameter

Min

10

Max

Units

ns

t

, t

Address, OE Set-up Time

Address Hold Time

AS OES

100

0

ns

AH

CS

CH

WP

DS

Chip Select Set-up Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Set-up Time

ns

0

ns

200

100

10

ns

, t

Data, OE Hold Time

Write Pulse Width High

ns

DH OEH

200

ns

WPH

AC Word Load Waveforms

WE Controlled

CE Controlled

7

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t

Word Programming Time

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

10

50

BP

0

ns

AS

100

0

ns

AH

ns

DS

DH

WP

WPH

EC

ns

Write Pulse Width

Write Pulse Width High

Erase Cycle Time

200

ns

10

seconds

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

WP

BP

WPH

WE

t

AS

AH

DH

5555

AO-A17

DATA

2AAA

ADDRESS

t

DS

INPUT

DATA

55

A0

AA

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

t

WP

WPH

WE

AO-A17

DATA

t

DH

AS

AH

5555

Note 2

2AAA

t

EC

DS

55

WORD 1

80

WORD 2

55

WORD 4

Note 3

WORD 5

AA

WORD 0

AA

WORD 3

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector

erase, the address depends on what sector is to be

erased. (See note 4 under command definitions.)

3. For chip erase, the data should be 10_H, and for sector erase,

the data should be 30_H.

8

AT49BV/LV4096

Data Polling Characteristics ⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t

Data Hold Time

OE Hold Time

OE to Output Delay

DH

10

ns

OEH

OE

(2)

ns

Write Recovery Time

0

ns

WR

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics ⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t

Data Hold Time

OE Hold Time

OE to Output Delay

OE High Pulse

DH

10

ns

OEH

OE

(2)

ns

150

0

ns

OEHP

WR

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Toggle Bit Waveforms ^{(1, 2, 3)}

Notes: 1. Toggling either OE or CE or both OE and CE will

operate toggle bit. The t_OEHPspecification must be

met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address

should not vary.

9

Software Product

Boot Block Lockout

Enable Algorithm⁽¹⁾

Identification Entry ⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 90

TO

LOAD DATA 80

TO

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

MODE ^{(2, 3, 5)}

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

Software Product

Identification Exit ^{(1, 6)}

LOAD DATA 40

TO

ADDRESS 5555

OR

LOAD DATA AA

LOAD DATA F0

TO

ANY ADDRESS

TO

PAUSE 1 second

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

EXIT PRODUCT

IDENTIFICATION

MODE ⁽⁴⁾

Notes for boot block lockout feature enable:

1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A14 - A0 (Hex).

LOAD DATA F0

TO

ADDRESS 5555

2. Boot block lockout feature enabled.

EXIT PRODUCT

IDENTIFICATION

MODE ⁽⁴⁾

Notes for software product identification:

1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A14 - A0 (Hex).

2. A1 - A17 = V_IL.

Manufacture Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH.

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 92H

6. Either one of the Product ID Exit commands can be used.

10

AT49BV/LV4096

Ordering Information ⁽¹⁾

t

I

(mA)

ACC

CC

Ordering Code

Package

Operation Range

(ns)

Active

Standby

120

25

0.05

AT49LV4096-12RC

AT49LV4096-12TC

44R

48T

Commercial

(0° to 70°C)

AT49LV4096-12RI

AT49LV4096-12TI

44R

48T

Industrial

(-40° to 85°C)

150

200

150

200

25

AT49LV4096-15RC

AT49LV4096-15TC

44R

48T

Commercial

(0° to 70°C)

AT49LV4096-15RI

AT49LV4096-15TI

44R

48T

Industrial

(-40° to 85°C)

AT49LV4096-20RC

AT49LV4096-20TC

44R

48T

Commercial

(0° to 70°C)

AT49LV4096-20RI

AT49LV4096-20TI

44R

48T

Industrial

(-40° to 85°C)

AT49BV4096-15RC

AT49BV4096-15TC

44R

48T

Commercial

(0° to 70°C)

AT49BV4096-15RI

AT49BV4096-15TI

44R

48T

Industrial

(-40° to 85°C)

AT49BV4096-20RC

AT49BV4096-20TC

44R

48T

Commercial

(0° to 70°C)

AT49BV4096-20RI

AT49BV4096-20TI

44R

48T

Industrial

(-40° to 85°C)

Note: 1. The AT49BV4096/LV4096 has as optional boot block feature. The part number shown in the Ordering Information table is

for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be

in the higher address range should contact Atmel.

Package Type

44R

48T

44 Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)

48 Lead, Thin Small Outline Package (TSOP)

11


型号：	AT49LV4096
厂家：	ATMEL
描述：	4-Megabit 256K x 16 3-volt Only CMOS Flash Memory 4兆位256K ×16 3伏的CMOS只快闪记忆体
文件：	总11页 (文件大小：179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49LV4096 [ATMEL]

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