AT49F1614-90CJ_技术文档

Features

• 4.5V to 5.5V Read/Write

• Access Time – 90 ns

• Sector Erase Architecture

– Thirty 32K Word (64K byte) Sectors with Individual Write Lockout

– Eight 4K Word (8K byte) Sectors with Individual Write Lockout

– Two 16K Word (32K byte) Sectors with Individual Write Lockout

• Fast Word Program Time – 10 µs

• Fast Sector Erase Time – 200 ms

• Dual-plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors

Memory Plane B: Twenty-four 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low-power Operation

16-megabit

(1M x 16/2M x 8)

5-volt Only

– 60 mA Active

– 3 mA Standby

Flash Memory

• DATA Polling, Toggle Bit, Ready/Busy for End of Program Detection

• RESET Input for Device Initialization

• Sector Program Unlock Command

AT49F1604

AT49F1604T

AT49F1614

AT49F1614T

• TSOP, CBGA and µBGA Package Options

• Top or Bottom Boot Block Configuration Available

Description

The AT49F16X4(T) is a 5.0-volt 16-megabit Flash memory organized as 1,048,576

words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on

I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 sec-

tors for erase operations. The device is offered in 48-lead TSOP and 48-ball µBGA

packages. The device has CE and OE control signals to avoid any bus contention.

This device can be read or reprogrammed using a single 5.0V power supply, making it

ideally suited for in-system programming.

Not Recommended for

New Designs

The device powers on in the read mode. Command sequences are used to place the

device in other operation modes such as program and erase. The device has the

(continued)

Pin Configurations

Pin Name

A0 - A19

CE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

OE

WE

RESET

RDY/BUSY

READY/BUSY Output

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

I/O15 (A-1)

A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

BYTE

NC

Rev. 0977J–04/00

DC

Don’t Connect

1

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

µBGA Top View (Ball Down)

2

VCC

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

3

8

1

2

3

4

5

6

7

4

5

6

7

A

B

C

D

E

F

A8

8

A13

A14

A11

A10

A8

WE

NC

A19

A17

A6

A7

A5

A4

A2

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

RST

A18

WE

RESET

NC

AT49F1604(T)

A15

A12

A9

A3

A1

NC

A19

A18

A17

A7

A16

I/O14

I/O15

I/O7

I/O5

I/O6

I/O13

I/O11

I/O12

I/O4

I/O2

I/O3

I/O8

I/O9

CE

A0

VCC

GND

I/O0

I/O1

GND

OE

A6

A5

VCC I/O10

A4

A3

GND

CE

A2

A1

A0

CBGA Top View

TSOP Top View

Type 1

1

2

3

4

5

6

A15

1

48

A16

A14

A13

A12

A11

A10

A9

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE

GND

I/O15/A-1

I/O7

A

B

C

D

E

F

3

A3

A4

A7 RDY/BUSY WE

A9

A13

A12

A14

A15

A16

4

5

A17

A6

NC RESET A8

6

I/O14

I/O6

7

A8

8

I/O13

I/O5

A2

A18

NC

A19

I/O5

A10

A11

I/O7

A19

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

WE

A1

A5

RESET

NC

VCC

I/O11

I/O3

AT49F1614(T)

A0

I/O0

I/O8

I/O9

I/O1

I/O2

NC

RDY/BUSY

A18

A17

A7

I/O10

I/O2

CE

OE

VSS

I/O10 I/O12 I/O14 BYTE

I/O9

G

H

I/O1

I/O11 VCC I/O13 I/O15

/A-1

A6

I/O8

A5

I/O0

A4

OE

I/O3

I/O4

I/O6

VSS

A3

GND

CE

A2

A1

A0

capability to protect the data in any sector. Once the data

protection for a given sector is enabled, the data in that

sector cannot be changed using input levels between

contains an Erase Suspend feature. This feature will put

the erase on hold for any amount of time and let the user

read data from or program data to any of the remaining

sectors within the same memory plane. There is no reason

to suspend the erase operation if the data to be read is in

the other memory plane. The end of a program or an erase

cycle is detected by the Ready/Busy pin, Data Polling or by

the toggle bit.

ground and V_CC

.

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while pro-

gram or erase functions are being executed in memory

plane A and vice versa. This operation allows improved

system performance by not requiring the system to wait for

a program or erase operation to complete before a read is

performed. To further increase the flexibility of the device, it

A six-byte command (Bypass Unlock) sequence to remove

the requirement of entering the three-byte program

sequence is offered to further improve programming time.

AT49F1604(T)/1614(T)

2

AT49F1604(T)/1614(T)

After entering the six-byte code, only single pulses on the

write control lines are required for writing into the device.

This mode (Single Pulse Byte/Word Program) is exited by

powering down the device or by pulsing the RESET pin low

For the AT49BV1614(T), the BYTE pin controls whether

the device data I/O pins operate in the byte or word config-

uration. If the BYTE pin is set at logic “1”, the device is in

word configuration, I/O0 - I/O15 are active and controlled

by CE and OE.

for a minimum of 50 ns and then bringing it back to V_CC

.

Erase and Erase Suspend/Resume commands will not

work while in this mode; if entered, they will result in data

being programmed into the device. It is not recommended

that the six-byte code reside in the software of the final

product but only exist in external programming code.

If the BYTE pin is set at logic “0”, the device is in byte con-

figuration, and only data I/O pins I/O0 - I/O7 are active and

controlled by CE and OE. The data I/O pins I/O8 - I/O14

are tri-stated, and the I/O15 pin is used as an input for the

LSB (A-1) address function.

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A19

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

REGISTER

OE

RESET

BYTE

ADDRESS

LATCH

DATA

RDY/BUSY

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

PLANE B

SECTORS

PLANE A SECTORS

Device Operation

READ: The AT49F16X4(T) is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus

contention.

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode,

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table on

page 6 (I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying a

3

low pulse on the WE or CE input with CE or WE low

(respectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data

is latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

SECTOR PROGRAMMING LOCKOUT: Each sector has a

programming lockout feature. This feature prevents pro-

gramming of data in the designated sectors once the

feature has been enabled. These sectors can contain

secure code that is used to bring up the system. Enabling

the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This

feature does not have to be activated; any sector’s usage

as a write-protected region is optional to the user.

RESET: A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high-impedance state. When

a high level is reasserted on the RESET pin, the device

returns to the read or standby mode, depending upon the

state of the control inputs. By applying a 12V 0.5V input

signal to the RESET pin, any sector can be reprogrammed

even if the sector lockout feature has been enabled (see

Sector Programming Lockout Override section).

Once the feature is enabled, the data in the protected sec-

tors can no longer be erased or programmed when input

levels of 5.5V or less are used. Data in the remaining sec-

tors can still be changed through the regular programming

method. To activate the lockout feature, a series of six pro-

gram commands to specific addresses with specific data

must be performed. Please refer to the Command Defini-

tions table.

SECTOR LOCKOUT DETECTION: A software method is

available to determine if programming of a sector is locked

out. When the device is in the software product identifica-

tion mode (see Software Product Identification Entry and

Exit sections) a read from address location 00002H within a

sector will show if programming the sector is locked out. If

the data on I/O0 is low, the sector can be programmed; if

the data on I/O0 is high, the program lockout feature has

been enabled and the sector cannot be programmed. The

software product identification exit code should be used to

return to standard operation.

ERASURE: Before a byte/word can be reprogrammed, it

must be erased. The erased state of memory bits is a logi-

cal “1”. Individual sectors can be erased by using the

Sector Erase command.

SECTOR ERASE: The device is organized into 40 sectors

(SA0 - SA39) that can be individually erased. The Sector

Erase command is a six-bus cycle operation. The sector

address is latched on the falling WE edge of the sixth cycle

while the 30H data input command is latched on the rising

edge of WE. The sector erase starts after the rising edge of

WE of the sixth cycle. The erase operation is internally con-

trolled; it will automatically time to completion. The

maximum time to erase a section is t_SEC. When the sector

programming lockout feature is not enabled, the sector will

erase (from the same Sector Erase command). Once a

sector has been protected, data in the protected sectors

cannot be changed unless the RESET pin is taken to 12V

0.5V. An attempt to erase a sector that has been protected

will result in the operation terminating in 2 µs.

SECTOR PROGRAMMING LOCKOUT OVERRIDE: The

user can override the sector programming lockout by taking

the RESET pin to 12V 0.5V. By doing this, protected data

can be altered through a sector erase or byte/word pro-

gramming. When the RESET pin is brought back to TTL

levels, the sector programming lockout feature is again

active.

ERASE SUSPEND/ERASE RESUME: The Erase Sus-

pend command allows the system to interrupt a sector

erase operation and then program or read data from a dif-

ferent sector within the same plane. Since this device has a

dual-plane architecture, there is no need to use the Erase

Suspend feature while erasing a sector when you want to

read data from a sector in the other plane. After the Erase

Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After

the erase operation has been suspended, the plane that

contains the suspended sector enters the erase-suspend-

read mode. The system can then read data or program

data to any other sector within the device. An address is

not required during the Erase Suspend command. During

a sector erase suspend, another sector cannot be erased.

To resume the sector erase operation, the system must

write the Erase Resume command. The Erase Resume

BYTE/WORD PROGRAMMING: Once a memory block is

erased, it is programmed (to a logical “0”) on a byte-by-byte

or on a word-by-word basis. Programming is accomplished

via the internal device command register and is a four-bus

cycle operation. The device will automatically generate the

required internal program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

the specified t_BPcycle time. The Data Polling feature or the

Toggle Bit feature may be used to indicate the end of a pro-

gram cycle.

AT49F1604(T)/1614(T)

4

AT49F1604(T)/1614(T)

command is a one-bus cycle command, which does require

the plane address (determined by A18 and A19).

An additional toggle bit is available on I/O2, which can be

used in conjunction with the toggle bit that is available on

I/O6. While a sector is erase suspended, a read or a pro-

gram operation from the suspended sector will result in the

I/O2 bit toggling. Please see “Status Bit Table” on page 15

for more details.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

RDY/BUSY: An open-drain Ready/Busy output pin pro-

vides another method of detecting the end of a program or

erase operation. RDY/BUSY is actively pulled low during

the internal program and erase cycles and is released at

the completion of the cycle. The open-drain connection

allows for OR-tying of several devices to the same

RDY/BUSY line.

For details, see “Operating Modes” on page 9 (for hard-

ware operation) or “Software Product Identification

Entry/Exit” on page 14. The manufacturer and device

codes are the same for both modes.

DATA POLLING: The AT49F16X4(T) features Data Poll-

ing to indicate the end of a program cycle. During a

program cycle an attempted read of the last byte/word

loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin.

During a sector erase operation, an attempt to read the

device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device.

Data Polling may begin at any time during the program

cycle. Please see “Status Bit Table” on page 15 for more

details.

HARDWARE DATA PROTECTION: The Hardware Data

Protection feature protects against inadvertent programs to

the AT49F16X4(T) in the following ways: (a) V_CCsense: if

V_CCis below 3.8V (typical), the program function is inhib-

ited. (b) V_CCpower-on delay: once V_CChas reached the

V_CCsense level, the device will automatically time out

10 ms (typical) before programming. (c) Program inhibit:

holding any one of OE low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

INPUT LEVELS: While operating with a 4.5V to 5.5V

power supply, the address inputs and control inputs (OE,

CE and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V_CC+ 0.6V.

TOGGLE BIT: In addition to Data Polling, the

AT49F16X4(T) provides another method for determining

the end of a program or erase cycle. During a program or

erase operation, successive attempts to read data from the

same memory plane will result in I/O6 toggling between

one and zero. Once the program cycle has completed, I/O6

will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

5

Command Definition in Hex⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles Addr Data

Addr

Data Addr Data Addr Data

Addr

Data

Addr

Data

Read

1

6

4

6

Addr D_OUT

Sector Erase

Byte/Word Program

Bypass Unlock

5555

AA

2AAA

55

5555

80

A0

80

5555

Addr

5555

AA

D_IN

AA

2AAA

55

SA⁽³⁾⁽⁴⁾

5555

30

55

A0

Single Pulse

Byte/Word Program

1

Addr

D_IN

Sector Lockout

Erase Suspend

Erase Resume

Product ID Entry

Product ID Exit⁽²⁾

6

1

3

1

5555

xxxx

PA⁽⁵⁾

5555

xxxx

AA

B0

30

2AAA

55

5555

80

5555

AA

2AAA

55

SA⁽³⁾⁽⁴⁾

40

AA

F0

2AAA

55

5555

90

F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex). Address A19 through A14 are don’t care in the

word mode. Address A19 through A14 and A-1 are don’t care in the byte mode.

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two

pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same Sector Erase command).

Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to

12V 0.5V.

5. PA is the plane address (A19 - A18).

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F1604(T)/1614(T)

6

AT49F1604(T)/1614(T)

AT49F1604/1614 – Sector Address Table

x8

x16

Plane

A

B

Sector

SA0

Size (Bytes/Words)

8K/4K

Address Range (A19 - A-1)

000000 - 001FFF

002000 - 003FFF

004000 - 005FFF

006000 - 007FFF

008000 - 009FFF

00A000 - 00BFFF

00C000 - 00DFFF

00E000 - 00FFFF

010000 - 017FFF

018000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1FFFFF

Address Range (A19 - A0)

00000 - 00FFF

01000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 04FFF

05000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 0BFFF

0C000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

SA1

8K/4K

SA2

8K/4K

SA3

8K/4K

SA4

8K/4K

SA5

8K/4K

SA6

8K/4K

SA7

8K/4K

SA8

32K/16K

64K/32K

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

7

AT49F1604T/1614T – Sector Address Table

x8

x16

Plane

B

A

Sector

SA0

Size (Bytes/Words)

64K/32K

32K/16K

8K/4K

Address Range (A19 - A-1)

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 - 1F1FFF

1F2000 - 1F3FFF

1F4000 - 1F5FFF

1F6000 - 1F7FFF

1F8000 - 1F9FFF

1FA000 - 1FBFFF

1FC000 - 1FDFFF

1FE000 - 1FFFFF

Address Range (A19 - A0)

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F3FFF

F4000 - F7FFF

F8000 - F8FFF

F9000 - F9FFF

FA000 - FAFFF

FB000 - FBFFF

FC000 - FCFFF

FD000 - FDFFF

FE000 - FEFFF

FF000 - FFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

8K/4K

AT49F1604(T)/1614(T)

8

AT49F1604(T)/1614(T)

DC and AC Operating Range

AT49F16X4(T)-90

0°C - 70°C

Com.

Ind.

Operating

Temperature (Case)

-40°C - 85°C

4.5V to 5.5V

V_CCPower Supply

Operating Modes

Mode

CE

V_IL

V_IH

X

OE

V_IL

V_IH

X⁽¹⁾

X

WE

V_IH

V_IL

X

RESET

V_IH

Ai

X

I/O

Read

D_OUT

D_IN

Program/Erase⁽²⁾

Standby/Program Inhibit

Program Inhibit

Output Disable

Reset

V_IH

High-Z

V_IH

X

V_IH

X

V_IL

V_IH

X

V_IH

X

V_IH

High-Z

X

V_IL

X

Product Identification

(3)

A1 - A19 = V_IL, A9 = V_H

A0 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

A1 - A19 = V_IL, A9 = V_H

A0 = V_IH

A0 = V_IL, A1 - A19 = V_IL

A0 = V_IH, A1 - A19 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

V_IH

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC programming waveforms.

3. V_H= 12.0V 0.5V.

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49F16X4; 00C0H (x16)-AT49F16X4;

C2H (x8)-AT49F16X4T; 00C2H (x16)-AT49F16X4T.

5. See details under “Software Product Identification Entry/Exit” on page 14.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

3

Units

µA

mA

V

I_LI

Input Load Current

V_IN= 0V to V_CC

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Current

V_I/O= 0V to V_CC

I_SB1

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

f = 5 MHz; I_OUT= 0 mA

I_SB2

3

(1)

I_CC

60

80

0.8

I_CCRW

V_IL

V_CCRead While Write Current

Input Low Voltage

V_IH

Input High Voltage

2.0

2.4

V

V_OL

V_OH

Output Low Voltage

I_OL= 2.1 mA

I_OH= -400 µA

0.45

V

Output High Voltage

V

Note:

1. In the erase mode, I_CCis 70 mA.

9

AC Read Characteristics

AT49F16X4(T)-90

Symbol

Parameter

Min

Max

90

Units

ns

t_ACC

Address to Output Delay

CE to Output Delay

(1)

t_CE

90

ns

(2)

t_OE

OE to Output Delay

0

40

ns

(3)(4)

t_DF

CE or OE to Output Float

Output Hold from OE, CE or Address, whichever occurred first

RESET to Output Delay

25

ns

t_OH

t_RO

ns

800

ns

AC Read Waveforms^(1)(2)(3)(4)

ADDRESS

ADDRESS VALID

CE

tCE

tOE

OE

tDF

tOH

tACC

tRO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

.

3. t_DFis specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

3.0

Output Test Load

t_R, t_F< 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

4

Max

6

Units

pF

Conditions

V_IN= 0V

C_OUT

8

12

pF

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested.

AT49F1604(T)/1614(T)

10

AT49F1604(T)/1614(T)

AC Byte/Word Load Characteristics

Symbol

Parameter

Min

10

50

0

Max

Units

ns

t

_AS, t_OES

Address, OE Setup Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

ns

Chip Select Setup Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Setup Time

ns

0

ns

100

50

10

50

ns

t

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

ns

t_WPH

ns

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

11

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte/Word Programming Time

Address Setup Time

Address Hold Time

Data Setup Time

10

50

t_AS

0

50

10

100

50

ns

t_AH

ns

t_DS

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

ns

t_WPH

t_SEC

Write Pulse Width High

Sector Erase Cycle Time

ns

200

ms

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

BP

t

WP

WPH

WE

t

AS

AH

DH

5555

2AAA

ADDRESS

A0 -A19

DATA

t

DS

INPUT

DATA

55

A0

AA

Sector Erase Cycle Waveforms

(1)

OE

(3)

CE

t

WP

WPH

WE

t

DH

AS

AH

(2)

5555

2AAA

A0-A19

DATA

t

EC

DS

55

WORD

80

WORD

55

30

WORD

AA

WORD

AA

WORD

0

1

2

3

WORD

4

5

Notes: 1. OE must be high only when WE and CE are both low.

2. For sector erase, the address depends on what sector is to be erased. (See note 3 under Command Definitions.)

3. The t_WPHtime between the 5th and 6th bus cycle should be a minimum of 150 ns.

AT49F1604(T)/1614(T)

12

AT49F1604(T)/1614(T)

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 10.

Data Polling Waveforms

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

OE High Pulse

ns

150

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 10.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t_OEHPspecification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

13

Software Product Identification Entry⁽¹⁾Sector Lockout Enable Algorithm⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

LOAD DATA 90

TO

ADDRESS 5555

LOAD DATA AA

TO

ENTER PRODUCT

IDENTIFICATION

ADDRESS 5555

(2)(3)(5)

MODE

LOAD DATA 55

TO

Software Product Identification Exit⁽¹⁾⁽⁷⁾

OR

ADDRESS 2AAA

LOAD DATA AA

LOAD DATA F0

TO

ADDRESS 5555

ANY ADDRESS

LOAD DATA 40

TO

EXIT PRODUCT

IDENTIFICATION

LOAD DATA 55

TO

ADDRESS 5555

(4)

MODE

ADDRESS 2AAA

PAUSE 200 µs⁽²⁾

LOAD DATA F0

TO

ADDRESS 5555

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A15 - A0 (Hex), A-1, and A15 - A19 (Don’t

Care).

EXIT PRODUCT

IDENTIFICATION

2. Sector Lockout feature enabled.

(4)

MODE

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A15 - A0 (Hex), A-1, and A15 - A19 (Don’t

Care).

2. A1 - A19 = V_IL.

Manufacturer Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH

.

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code:1FH(x8); 001FH(x16)

6. Device Code:C0H (x8) – AT49F16X4

00C0H (x16) – AT49F16X4

C2H (x8) – AT49F16X4T

00C2H(x16) – AT49F16X4T

7. Either one of the Product ID Exit commands can be used.

AT49F1604(T)/1614(T)

14

AT49F1604(T)/1614(T)

Status Bit Table

Status Bit

I/O6

I/O7

I/O2

Read Address In

While

Plane A

Plane B

Plane A

Plane B

Plane A

Plane B

Programming in Plane A

Programming in Plane B

I/O7

DATA

I/O7

TOGGLE

DATA

1

DATA

1

DATA

TOGGLE

DATA

Erasing in Plane A

Erasing in Plane B

0

DATA

0

TOGGLE

DATA

TOGGLE

DATA

TOGGLE

Erase Suspended & Read

Erasing Sector

1

TOGGLE

DATA

TOGGLE

DATA

Erase Suspended & Read

Non-erasing Sector

DATA

Erase Suspended &

Program Erasing Sector

1

TOGGLE

DATA

Erase Suspended &

Program Non-erasing Sector

in Plane A

I/O7

DATA

TOGGLE

DATA

Erase Suspended &

Program Non-erasing Sector

in Plane B

DATA

I/O7

DATA

TOGGLE

DATA

TOGGLE

15

AT49F1604(T)/1614(T) Ordering Information

I

_CC(mA)

Standby

3.0

t_ACC

(ns)

Active

Ordering Code

Package

Operation Range

90

60

AT49F1614-90TI

48T

Industrial

(-40°C to 85°C)

Package Type

48C2

48T

48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48-lead, Thin Small Outline Package (TSOP)

48U

48-ball, Micro Ball Grid Array Package (µBGA)

AT49F1604(T)/1614(T)

16

AT49F1604(T)/1614(T)

Packaging Information

48C2, 48-ball, Plastic Chip-size Ball Grid Array

Package (CBGA)

Dimensions in Millimeters and (Inches)*

48T, 48-lead, Plastic Thin Small Outline Package

(TSOP) Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 DD

8.2 (0.322)

7.8 (0.307)

10.2 (0.401)

9.8 (0.386)

0.30 (0.012)

1.20 (0.047)

1.00 (0.039)

2.12 (0.083)

4.0 (0.157)

1.86 (0.073)

6

5

4

3

2

1

2.32 (0.091)

2.06 (0.081)

A

B

C

D

E

F

5.6 (0.220)

G

H

0.80 (0.031) BSC

0.46 (0.018)

NON-ACCUMULATIVE

DIA BALL TYP

*Controlling dimension: millimeters

48U, 48-ball, Micro Ball Grid Array Package (µBGA)

Dimensions in Millimeters

6.97

6.63

8.60

8.36

0.30

0.15 MIN.

1.03

5.25

0.82

8

7

6

5

4

3

2

1

0.73

0.63

A

B

C

D

E

F

3.75

0.40

0.27 DIA TYP

0.75 TYP

NON-ACCUMULATIVE

17

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Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

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Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel Rousset

Zone Industrielle

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France

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

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not authorized for use as critical components in life support devices or systems.

®

™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0977J–04/00/xM


型号：	AT49F1614-90CJ
厂家：	ATMEL
描述：	Flash, 1MX16, 90ns, PBGA48, PLASTIC, CBGA-48 内存集成电路
文件：	总18页 (文件大小：340K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49F1614-90CJ [ATMEL]

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