AT49F1614T-70CC [ATMEL]
16-Megabit 1M x 16/2M x 8 5-volt Only Flash Memory; 16兆位1M ×16 / 2M ×8 5伏只有闪存
| 型号： | AT49F1614T-70CC |
| 厂家： | 
ATMEL |
| 描述： | 16-Megabit 1M x 16/2M x 8 5-volt Only Flash Memory |
| 文件： | 总18页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 4.5V to 5.5V Read/Write
• Access Time - 70 ns
• Sector Erase Architecture
– Thirty 32K Word (64K byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K byte) Sectors with Individual Write Lockout
– Two 16K Word (32K byte) Sectors with Individual Write Lockout
• Fast Word Program Time - 10 µs
• Fast Sector Erase Time - 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
– Memory Plane B: Twenty-Four 32K Word Sectors
• Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
• Low Power Operation
16-Megabit
(1M x 16/2M x 8)
5-volt Only
– 40 mA Active
– 10 µA Standby
Flash Memory
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP, CBGA, and µBGA Package Options
• Top or Bottom Boot Block Configuration Available
AT49F1604
AT49F1604T
AT49F1614
AT49F1614T
Advance
Description
The AT49F16X4(T) is a 5.0 volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 blocks for
erase operations. The device is offered in 48-pin TSOP and 48-ball µBGA packages.
The device has CE, and OE control signals to avoid any bus contention. This device
can be read or reprogrammed using a single 5.0V power supply, making it ideally
suited for in-system programming.
(continued)
Pin Configurations
Information
AT49BV16X4(T)
Pin Name
A0 - A19
CE
Function
Addresses
AT49BV1604
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
READY/BUSY Output
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
I/O15 (A-1)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
BYTE
NC
DC
Don’t Connect
Rev. 0977B–06/98
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
µBGA Top View (Ball Down)
2
VCC
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
3
8
1
2
3
4
5
6
7
4
5
6
7
A
B
C
D
E
F
A8
NC
8
A13
A14
A11
A10
A8
WE
NC
NC
A18
NC
A19
A17
A6
A7
A5
A4
A2
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RST
NC
WE
RESET
NC
AT49F1604(T)
A15
A12
A9
A3
A1
NC
A19
A18
A17
A7
A16
I/O14
I/O15
I/O7
I/O5
I/O6
I/O13
I/O11
I/O12
I/O4
I/O2
I/O3
I/O8
I/O9
CE
A0
VCC
GND
I/O0
I/O1
GND
OE
A6
A5
VCC I/O10
A4
A3
GND
CE
A0
A2
A1
TSOP Top View
Type 1
A15
1
48
A16
A14
A13
A12
A11
A10
A9
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
GND
I/O15/A-1
I/O7
CBGA Top View
3
4
5
G
F
E
D
C
B
A
H
6
I/O14
I/O6
7
A8
8
I/O13
I/O5
1
2
3
4
5
6
A19
NC
9
VSS
I/O1
I/O3
I/O4
I/O6
VSS
OE
CE
A0
A1
A5
A2
A6
A4
A3
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
WE
I/O9
I/O8
I/O0
I/O2
I/O5
I/O7
A17
RESET
NC
VCC
I/O11
I/O3
AT49F1614(T)
NC
I/O11 I/O10
VCC I/O12
I/O13 I/O14
NC
A19
A11
A15
A18
NC RDY/BUSY
RDY/BUSY
A18
A17
A7
I/O10
I/O2
NC RESET WE
I/O9
I/O1
A6
I/O8
A10
A14
A8
A9
A5
I/O0
A4
OE
I/O15 BYTE A16
/A-1
A12
A13
A3
GND
CE
A2
A1
A0
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as program and erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
ground and VCC
.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
A six byte command (bypass unlock) sequence to remove
the requirement of entering the three byte program
sequence is offered to further improve programming time.
After entering the six byte code, only single pulses on the
write control lines are required for writing into the device.
This mode (single pulse byte/word program) is exited by
AT49F16X4(T)
2
AT49F16X4(T)
powering down the device, or by pulsing the RESET pin
low and then bringing it back to VCC. Erase and Erase Sus-
pend/Resume commands will not work while in this mode;
if entered they will result in data being programmed into the
device. It is not recommended that the six byte code reside
in the software of the final product but only exist in external
programming code.
set at logic “1”, the device is in word configuration, I/O0-
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0-I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8-I/O14 are
tri-stated, and the I/O15 pin is used as an input for the LSB
(A-1) address function.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A19
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
BYTE
ADDRESS
LATCH
DATA
RDY/BUSY
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
PLANE B
SECTORS
PLANE A SECTORS
Device Operation
READ: The AT49F16X4(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
3
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin any sector can be reprogrammed
even if the sector lockout feature has been enabled (see
Sector Programming Lockout Override section).
SECTOR PROGRAMMING LOCKOUT: Each sector has a
programming lockout feature. This feature prevents pro-
gramming of data in the designated sectors once the fea-
ture has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lock-
out feature will allow the boot code to stay in the device
while data in the rest of the device is updated. This feature
does not have to be activated; any sector’s usage as a
write protected region is optional to the user.
ERASURE: Before a byte/word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.
Once the feature is enabled, the data in the protected sec-
tors can no longer be erased or programmed when input
levels of 5.5V or less are used. Data in the remaining sec-
tors can still be changed through the regular programming
method. To activate the lockout feature, a series of six pro-
gram commands to specific addresses with specific data
must be performed. Please refer to the Command Defini-
tions table.
CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is tEC
.
SECTOR PROGRAMMING LOCKOUT OVERRIDE: The
user can override the sector programming lockout by taking
the RESET pin to 12V ± 0.5V. By doing this protected data
can be altered through a chip erase, sector erase or
byte/word programming. When the RESET pin is brought
back to TTL levels the sector programming lockout feature
is again active.
If the sector lockout has been enabled, the Chip Erase will
not erase the data in the sector that has been locked; it will
erase only the unprotected sectors. After the chip erase,
the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into forty sectors (SA0 - SA39) that can
be individually erased. The Sector Erase command is a six
bus cycle operation. The sector address is latched on the
falling WE edge of the sixth cycle while the 30H data input
command is latched on the rising edge of WE. The sector
erase starts after the rising edge of WE of the sixth cycle.
The erase operation is internally controlled; it will automati-
cally time to completion. The maximum time to erase a sec-
tion is tSEC. When the sector programming lockout feature
is not enabled, the sector will erase (from the same sector
erase command). Once a sector has been protected, data
in the protected sectors cannot be changed unless the
RESET pin is taken to 12V ± 0.5V. An attempt to erase a
sector that has been protected will result in the operation
terminating in 2 µs.
ERASE SUSPEND/ERASE RESUME: The erase suspend
command allows the system to interrupt a sector erase
operation and then program or read data from a different
sector within the same plane. Since this device has a dual
plane architecture, there is no need to use the erase sus-
pend feature while erasing a sector when you want to read
data from a sector in the other plane. After the erase sus-
pend command is given, the device requires a maximum
time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane which con-
tains the suspended sector enters the erase-suspend-read
mode. The system can then read data or program data to
any other sector within the device. An address is not
required during the erase suspend command. During a
sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write
the erase resume command. The erase resume command
is a one bus cycle command, which does require the plane
address (determined by A18 and A19). The device also
supports an erase suspend during a complete chip erase.
While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The com-
mand sequence for a chip erase suspend and a sector
erase suspend are the same.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or on a word-by-word basis. Programming is accomplished
via the internal device command register and is a 4-bus
cycle operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature or the
toggle bit feature may be used to indicate the end of a pro-
gram cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
AT49F16X4(T)
4
AT49F16X4(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
gram operation from the suspended sector will result in the
I/O2 bit toggling. Please see “Status Bit Table” for more
details.
DATA POLLING: The AT49F16X4(T) features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle. Please see “Status Bit Table” for more details.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F16X4(T)
in the following ways: (a) VCC sense: if VCC is below 3.8V
(typical), the program function is inhibited. (b) VCC power on
delay: once VCC has reached the VCC sense level, the
device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
TOGGLE BIT: In addition to DATA polling the
AT49F16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
INPUT LEVELS: While operating with a 4.5V to 5.5V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
An additional toggle bit is available on I/O2 which can be
used in conjunction with the toggle bit which is available on
I/O6. While a sector is erase suspended, a read or a pro-
5
Command Definition in (Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles Addr Data
Addr
Data Addr Data Addr Data
Addr
Data
Addr
Data
Read
1
6
6
4
6
Addr DOUT
Chip Erase
5555
5555
5555
5555
AA
AA
AA
AA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555
5555
5555
5555
80
80
A0
80
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
10
30
Sector Erase
Byte/Word Program
Bypass Unlock
SA(3)(4)
2AAA
2AAA
55
55
5555
A0
40
Single Pulse
Byte/Word Program
1
Addr
DIN
Sector Lockout
Erase Suspend
Erase Resume
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
6
1
1
3
3
1
5555
xxxx
PA(5)
5555
5555
xxxx
AA
B0
30
2AAA
55
5555
80
5555
AA
SA(3)(4)
AA
AA
F0
2AAA
2AAA
55
55
5555
5555
90
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).
2. Either one of the Product ID Exit commands can be used.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next four
pages for details).
4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command).
Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to
12V ± 0.5V.
5. PA is the plane address (A19 - A18).
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49F16X4(T)
6
AT49F16X4(T)
Memory Plane A - Bottom Boot
x8
x16
Sector
SA0
Size (Bytes/Words)
8K/4K
Address Range (A19 - A-1)
Address Range (A19 - A0)
000000 - 001FFF
002000 - 003FFF
004000 - 005FFF
006000 - 007FFF
008000 - 009FFF
00A000 - 00BFFF
00C000 - 00DFFF
00E000 - 00FFFF
010000 - 017FFF
018000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
00000 - 00FFF
01000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 04FFF
05000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 0BFFF
0C000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
SA1
8K/4K
SA2
8K/4K
SA3
8K/4K
SA4
8K/4K
SA5
8K/4K
SA6
8K/4K
SA7
8K/4K
SA8
32K/16K
32K/16K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
7
Memory Plane B - Bottom Boot
x8
x16
Sector
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
Address Range (A19 - A-1)
Address Range (A19 - A0)
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
150000 - 15FFFF
160000 - 16FFFF
170000 - 17FFFF
180000 - 18FFFF
190000 - 19FFFF
1A0000 - 1AFFFF
1B0000 - 1BFFFF
1C0000 - 1CFFFF
1D0000 - 1DFFFF
1E0000 - 1EFFFF
1F0000 - 1FFFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FFFFF
AT49F16X4(T)
8
AT49F16X4(T)
Memory Plane B - Top Boot
x8
x16
Sector
SA0
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
Address Range (A19 - A-1)
Address Range (A19 - A0)
000000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
100000 - 10FFFF
110000 - 11FFFF
120000 - 12FFFF
130000 - 13FFFF
140000 - 14FFFF
150000 - 15FFFF
160000 - 16FFFF
170000 - 17FFFF
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
9
Memory Plane A - Top Boot
x8
x16
Sector
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
32K/16K
32K/16K
8K/4K
Address Range (A19 - A-1)
Address Range (A19 - A0)
180000 - 18FFFF
190000 - 19FFFF
1A0000 - 1AFFFF
1B0000 - 1BFFFF
1C0000 - 1CFFFF
1D0000 - 1DFFFF
1E0000 - 1E7FFF
1E8000 - 1EFFFF
1F0000 - 1F1FFF
1F2000 - 1F3FFF
1F4000 - 1F5FFF
1F6000 - 1F7FFF
1F8000 - 1F9FFF
1FA000 - 1FBFFF
1FC000 - 1FDFFF
1FE000 - 1FFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F3FFF
F4000 - F7FFF
F8000 - F8FFF
F9000 - F9FFF
FA000 - FAFFF
FB000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FEFFF
FF000 - FFFFF
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
AT49F16X4(T)
10
AT49F16X4(T)
DC and AC Operating Range
AT49F16X4(T)-70
AT49F16X4(T)-90
0°C - 70°C
Com.
Ind.
0°C - 70°C
-40°C - 85°C
4.5V to 5.5V
Operating
Temperature (Case)
-40°C - 85°C
4.5V to 5.5V
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET
Ai
Ai
Ai
X
I/O
Read
VIH
VIH
VIH
VIH
VIH
VIH
VIL
DOUT
DIN
Program/Erase(2)
Standby/Program Inhibit
Program Inhibit
Program Inhibit
Output Disable
Reset
High Z
VIH
X
X
VIL
VIH
X
X
X
High Z
High Z
X
X
X
Product Identification
(3)
(3)
A1 - A19 = VIL, A9 = VH
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
A1 - A19 = VIL, A9 = VH
A0 = VIH
A0 = VIL, A1 - A19 = VIL
A0 = VIH, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH (x8); 161F (x16), Device Code: C0H (x8)-AT49F16X4; 16CO (x16)-AT49F16X4;
C2H (x8)-AT49F16X4T; 16C2 (x16)-AT49F16X4T.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
10
1
Units
µA
µA
µA
mA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
40
60
0.8
ICCRW
VIL
VCC Read While Write Current
Input Low Voltage
VIH
Input High Voltage
2.0
2.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
V
Note:
1. In the erase mode, ICC is 50 mA.
11
AC Read Characteristics
AT49F16X4(T)-70
AT49F16X4(T)-90
Symbol
Parameter
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
70
90
ns
(2)
tOE
OE to Output Delay
0
0
0
35
0
0
0
40
ns
(3)(4)
tDF
CE or OE to Output Float
Output Hold from OE, CE or Address, whichever occurred first
RESET to Output Delay
25
25
ns
tOH
tRO
ns
800
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
3.0
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
6
Units
pF
Conditions
VIN = 0V
CIN
4
8
COUT
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49F16X4(T)
12
AT49F16X4(T)
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
Max
Units
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
10
50
0
ns
ns
ns
ns
ns
ns
ns
ns
tAH
tCS
tCH
tWP
tDS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
0
100
50
10
50
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
tWPH
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
13
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte/Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
10
50
tAS
0
50
50
0
ns
tAH
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
100
50
ns
tWPH
tEC
Write Pulse Width High
Chip Erase Cycle Time
Sector Erase Cycle Time
ns
10
seconds
ms
tSEC
200
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
BP
t
WP
WPH
WE
t
t
t
AS
AH
DH
5555
5555
5555
2AAA
ADDRESS
A0 -A19
DATA
t
DS
INPUT
DATA
55
A0
AA
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A19
DATA
t
t
t
DH
AS
AH
5555
5555
5555
Note
2
2AAA
2AAA
t
t
EC
DS
55
WORD
80
WORD
55
WORD
Note 3
AA
WORD
AA
WORD
0
1
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 3 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49F16X4(T)
14
AT49F16X4(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
tDH
Data Hold Time
ns
ns
ns
ns
tOEH
tOE
OE Hold Time
10
OE to Output Delay(2)
Write Recovery Time
tWR
0
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
tDH
Parameter
Min
10
Typ
Max
Units
ns
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
15
Status Bit Table
Status Bit
I/O 6
I/O 7
I/O 2
Read Address In
While
Plane A
Plane B
Plane A
Plane B
Plane A
Plane B
Programming in Plane A
Programming in Plane B
I/O7
DATA
I/O7
TOGGLE
DATA
DATA
1
DATA
1
DATA
TOGGLE
DATA
Erasing in Plane A
Erasing in Plane B
0
DATA
0
TOGGLE
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
1
TOGGLE
DATA
TOGGLE
DATA
Erase Suspended & Read
Non-Erasing Sector
DATA
DATA
DATA
DATA
Erase Suspended &
Program Erasing Sector
1
1
1
1
TOGGLE
TOGGLE
TOGGLE
DATA
Erase Suspended &
Program Non-Erasing
Sector in Plane A
I/O7
DATA
TOGGLE
DATA
Erase Suspended &
Program Non-Erasing
Sector in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
AT49F16X4(T)
16
AT49F16X4(T)
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
40
0.01
AT49F1604-70TC
AT49F1604-70UC
48T
48U
Commercial
(0°C to 70°C)
AT49F1614-70CC
AT49F1614-70TC
48C2
48T
40
40
40
40
40
40
40
0.01
0.01
0.01
0.01
0.01
0.01
0.01
AT49F1604-70TI
AT49F1604-70UI
48T
48U
Industrial
(-40°C to 85°C)
AT49F1614-70CI
AT49F1614-70TI
48C2
48T
90
70
90
AT49F1604-90TC
AT49F1604-90UC
48T
48U
Commercial
(0°C to 70°C)
AT49F1614-90CC
AT49F1614-90TC
48C2
48T
AT49F1604-90TI
AT49F1604-90UI
48T
48U
Industrial
(-40°C to 85°C)
AT49F1614-90CI
AT49F1614-90TI
48C2
48T
AT49F1604T-70TC
AT49F1604T-70UC
48T
48U
Commercial
(0°C to 70°C)
AT49F1614T-70CC
AT49F1614T-70TC
48C2
48T
AT49F1604T-70TI
AT49F1604T-70UI
48T
48U
Industrial
(-40°C to 85°C)
AT49F1614T-70CI
AT49F1614T-70TI
48C2
48T
AT49F1604T-90TC
AT49F1604T-90UC
48T
48U
Commercial
(0°C to 70°C)
AT49F1614T-90CC
AT49F1614T-90TC
48C2
48T
AT49F1604T-90TI
AT49F1604T-90UI
48T
48U
Industrial
(-40°C to 85°C)
AT49F1614T-90CI
AT49F1614T-90TI
48C2
48T
Package Type
48C2
48T
48-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48-Lead, Thin Small Outline Package (TSOP)
48U
48-Ball, Micro Ball Grid Array Package (µBGA)
17
Packaging Information
48C2, 48-Ball, Plastic Chip-size Ball Grid Array
Package (CBGA)
48T, 48-Lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 DD
8.2
7.8
4.0
6
5
4
3
2
1
A
B
C
D
E
F
11.2
10.8
5.6
G
H
0.85
0.75
TYP
0.40 DIA TYP
0.35
1.2 MAX
NON-ACCUMULATIVE
*Controlling dimension: millimeters
48U, 48-Ball, Micro Ball Grid Array Package (µBGA)
6.8
6.4
3.75
F
E
D
C
B
A
1
2
3
4
5
6
7
8
8.4
8.0
5.25
0.75 TYP
0.30 DIA TYP
0.15 MIN.
0.70
1.00
0.85
NON-ACCUMULATIVE
AT49F16X4(T)
18
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