AT49BV040-12VC [ATMEL]
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory; 4兆位（ 512K ×8 ）单2.7伏的电池电压闪存
| 型号： | AT49BV040-12VC |
| 厂家： | 
ATMEL |
| 描述： | 4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory |
| 文件： | 总13页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time – 70 ns
• Internal Program Control and Timer
• 16K Bytes Boot Block with Lockout
• Fast Chip Erase Cycle Time – 10 seconds
• Byte-by-byte Programming – 30 µs/Byte Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
4-megabit
(512K x 8)
• Small Packaging
– 8 x 14 mm VSOP/TSOP
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 524,288
words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technol-
ogy, the devices offer access times to 70 ns with power dissipation of just 90 mW over
the commercial temperature range. When the device is deselected, the CMOS
standby current is less than 50 µA.
AT49BV040
AT49LV040
The device contains a user-enabled “boot block” protection feature. The
AT49BV/LV040 locates the boot block at lowest order addresses (“bottom boot”).
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
OE
WE
I/O0 - I/O7
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
8
A2 10
A1 11
A0 12
I/O0 13
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
Rev. 0679D–03/01
To allow for simple in-system reprogrammability, the
AT49BV/LV040 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040 is performed by eras-
ing the entire four megabits of memory and then
programming on a byte-by-byte basis. The typical byte pro-
gramming time is a fast 30 µs. The end of a program cycle
can be optionally detected by the Data Polling feature.
Once the end of a byte program cycle has been detected, a
new access for a read or program can begin. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lockout feature to provide data integrity.
The boot sector is designed to contain user-secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
8
OE
DATA LATCH
OE, CE, AND WE
WE
LOGIC
CE
INPUT/OUTPUT
BUFFERS
Y DECODER
ADDRESS
Y-GATING
7FFFFH
MAIN MEMORY
INPUTS
X DECODER
(496K BYTES)
04000H
03FFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
00000H
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus
contention.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a four-bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
ERASURE: Before a byte can be reprogrammed, the 512K
bytes memory array (or 496K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a six-byte software code. The
software chip erase code consists of six-byte load com-
mands to specific address locations with a specific data
pattern (please refer to “Chip Erase Cycle Waveforms” on
page 8).
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The Data Polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
AT49BV/LV040
2
AT49BV/LV040
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write-protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH.
Entry/Exit” on page 10. The manufacturer and device
codes are the same for both modes.
DATA POLLING: The AT49BV/LV040 features Data Poll-
ing to indicate the end of a program cycle. During a
program cycle, an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
TOGGLE BIT: In addition to Data Polling, the
AT49BV/LV040 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
HARDWARE DATA PROTECTION: The Hardware Data
Protection feature protects against inadvertent programs to
the AT49BV/LV040 in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel.
It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
For details, see “Operating Modes” on page 5 (for hard-
ware operation) or “Software Product Identification
3
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
DOUT
AA
Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1
6
4
6
3
3
1
Chip Erase
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
DIN
AA
2AAA
2AAA
55
55
5555
5555
10
40
Byte Program
Boot Block Lockout(1)
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
AA
AA
AA
AA
F0
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground..................................-0.6V to + 13.5V
AT49BV/LV040
4
AT49BV/LV040
DC and AC Operating Range
AT49LV040-70
0°C - 70°C
AT49BV/LV040-90
AT49BV040-12
0°C - 70°C
Com.
0°C - 70°C
-40°C - 85°C
Operating
Temperature (Case)
Ind.
-40°C - 85°C
3.0V to 3.6V
-40°C - 85°C
2.7V to 3.6V
VCC Power Supply
2.7V to 3.6V/3.0V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High-Z
VIH
X
X
VIL
VIH
X
X
High-Z
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A18 = VIL
A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Software(2)
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1FH
Device Code: 13H
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
10
10
50
1
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
ISB2
(1)
ICC
f = 5 MHz; IOUT = 0 mA, VCC = 3.6V
25
0.8
VIL
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.45
V
IOH = -100 µA; VCC = 3.0V
V
Notes: 1. In the erase mode, ICC is 50 mA.
2. See details under “Software Product Identification Entry/Exit” on page 10.
5
AC Read Characteristics
AT49LV040-70
AT49BV/LV040-90
AT49BV040-12
Symbol Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
tOE
tDF
70
90
ns
(2)
OE to Output Delay
0
0
35
0
0
40
0
0
ns
(3)(4)
CE or OE to Output Float
25
25
30
ns
Output Hold from OE, CE or Address,
whichever comes first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49BV/LV040
6
AT49BV/LV040
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
0
ns
200
100
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
30
50
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
OE must be high only when WE and CE are both low.
AT49BV/LV040
8
AT49BV/LV040
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Software Product Identification Entry(1) Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 5555
LOAD DATA 55
LOAD DATA 90
TO
ADDRESS 5555
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(4)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
OR
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 1 second(2)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot Block Lockout feature enabled.
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 13H
AT49BV/LV040
10
AT49BV/LV040
AT49BV/LV040 Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
120
70
25
0.05
AT49BV040-90JC
AT49BV040-90TC
AT49BV040-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
AT49BV040-90JI
AT49BV040-90TI
AT49BV040-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
25
25
25
0.05
0.05
0.05
AT49BV040-12JC
AT49BV040-12TC
AT49BV040-12VC
32J
32T
32V
Commercial
(0°C to 70°C)
AT49BV040-12JI
AT49BV040-12TI
AT49BV040-12VI
32J
32T
32V
Industrial
(-40°C to 85°C)
AT49LV040-70JC
AT49LV040-70TC
AT49LV040-70VC
32J
32T
32V
Commercial
(0°C to 70°C)
AT49LV040-70JI
AT49LV040-70TI
AT49LV040-70VI
32J
32T
32V
Industrial
(-40°C to 85°C)
90
AT49LV040-90JC
AT49LV040-90TC
AT49LV040-90VC
32J
32T
32V
Commercial
(0°C to 70°C)
AT49LV040-90JI
AT49LV040-90TI
AT49LV040-90VI
32J
32T
32V
Industrial
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32T
32V
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 14 mm)
11
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32T, 32-lead, Plastic Thin Small Outline Package
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BA
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
.012(.305)
.008(.203)
IDENTIFY
INDEX
MARK
.530(13.5)
.553(14.0)
.490(12.4)
18.5(.728)
18.3(.720)
20.2(.795)
19.8(.780)
.547(13.9)
.032(.813)
.021(.533)
.595(15.1)
.026(.660)
.013(.330)
.585(14.9)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
AT CONTACT
POINTS
7.50(.295)
REF
8.20(.323)
7.80(.307)
1.20(.047) MAX
.022(.559) X 45˚ MAX (3X)
0.15(.006)
0.05(.002)
.453(11.5)
.447(11.4)
0
0.20(.008)
0.10(.004)
REF
5
.495(12.6)
.485(12.3)
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
32V, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BA
INDEX
MARK
12.5(.492)
12.3(.484)
14.2(.559)
13.8(.543)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
7.50(.295)
REF
8.10(.319)
7.90(.311)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
0.20(.008)
0.10(.004)
REF
5
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
AT49BV/LV040
12
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© Atmel Corporation 2001.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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