AT49BV040-15JC [ATMEL]
4-Megabit 512K x 8 Single 2.7-volt Battery-Voltage Flash Memory; 4兆位512K ×8单2.7伏的电池电压闪存
| 型号： | AT49BV040-15JC |
| 厂家： | 
ATMEL |
| 描述： | 4-Megabit 512K x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| 文件： | 总12页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time - 120 ns
• Internal Program Control and Timer
• 16K bytes Boot Block With Lockout
• Fast Chip Erase Cycle Time - 10 seconds
• Byte-by-Byte Programming - 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Small Packaging
4-Megabit
(512K x 8)
– 8 x 8 mm CBGA
Single 2.7-volt
Battery-Voltage™
Flash Memory
– 8 x 14 mm V-TSOP
Description
The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288
words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS tech-
nology, the devices offer access times to 120 ns with power dissipation of just 90 mW
over the commercial temperature range. When the device is deselected, the CMOS
standby current is less than 50 µA.
AT49BV040
AT49BV040T
AT49LV040
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV/LV040 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BV/LV040T locates it at highest order addresses
(“top boot”).
AT49LV040T
(continued)
CBGA Top View
Pin Configurations
1
2
3
4
5
6
7
Pin Name Function
A
B
C
D
E
F
A0 - A18
CE
Addresses
GND I/O6 VCC VCC I/O2 OE GND
A17 I/O7 I/O4 NC NC I/O0 CE
A10 NC I/O5 NC I/O3 I/O1 A0
A14 A13 A9 NC NC A6 A3
A16 A11 WE NC A7 A4 A1
A15 A12 A8 NC A18 A5 A2
Chip Enable
Output Enable
Write Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
PLCC Top View
V - TSOP Top View (8 x 14 mm) or
T - TSOP Top View (8 x 20 mm)
0679AX-A–9/97
To allow for simple in-system reprogrammability, the
AT49BV/LV040 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040 is performed by eras-
ing the entire 4 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming
time is a fast 30 µs. The end of a program cycle can be
access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
optionally detected by the DATA polling feature. Once the
end of a byte program cycle has been detected, a new
Block Diagram
AT49BV/LV040
AT49BV/LV040T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
8
8
OE
WE
CE
DATA LATCH
DATA LATCH
OE, CE, AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
Y-GATING
7FFFFH
03FFFH
00000H
7FFFFH
7C000H
00000H
ADDRESS
INPUTS
MAIN MEMORY
(496K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
OPTIONAL BOOT
MAIN MEMORY
(496K BYTES)
BLOCK (16K BYTES)
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
“0”s to “1”s. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
ERASURE: Before a byte can be reprogrammed, the
512K bytes memory array (or 496K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the
AT49BV/LV040 boot block is 00000H to 03FFFH while the
address range of the AT49BV/LV040T boot block is
7C000H to 7FFFFH.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Oncethememoryarrayiserased,
the device is programmed (to a logical “0”) on a byte-by-
byte basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert
AT49BV/LV040
2
AT49BV/LV040
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Com-
mand Definitions table.
DATA POLLING: The AT49BV/LV040 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
TOGGLE BIT: In addition to DATA polling the
AT49BV/LV040 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49BV/LV040
in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel.
It may be accessed by hardware or software operation.
The hardware operation mode can be used by an external
programmer to identify the correct programming algorithm
for the Atmel product.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
3
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
DOUT
AA
Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1
6
4
6
3
3
1
Chip Erase
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
DIN
AA
2AAA
2AAA
55
55
5555
5555
10
40
Byte Program
Boot Block Lockout(1)
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
AA
AA
AA
AA
F0
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV040 and 7C000H to 7FFFFH for the
AT49BV/LV040T.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
All Output Voltages
with Respect to Ground............................ -0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground..................................-0.6V to + 13.5V
AT49BV/LV040
4
AT49BV/LV040
DC and AC Operating Range
AT49BV/LV040-12
0°C - 70°C
AT49BV/LV040-15
AT49BV/LV040-20
0°C - 70°C
Com.
0°C - 70°C
Operating
Temperature (Case)
Ind.
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
VCC Power Supply
2.7V to 3.6V/3.0V to 3.6V 2.7V to 3.6V/3.0V to 3.6V 2.7V to 3.6V/3.0V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A18 = VIL
A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4)
Device Code (4)
Software(5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH
Device Code: 13H (AT49BV/LV040), 12H (AT49BV/LV040T).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
ILI
Parameter
Condition
Min
Typ
Max
10
10
50
1
Units
µA
µA
µA
mA
mA
V
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
ISB1
ISB2
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA, VCC = 3.6V
12
25
0.8
VIL
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.45
V
IOH = -100 µA; VCC = 3.0V
V
Note:
1. In the erase mode, ICC is 50 mA.
5
AC Read Characteristics
AT49BV/LV040-12
AT49BV/LV040-15
AT49BV/LV040-20
Symbol Parameter
Min
Max
120
120
50
Min
Max
150
150
70
Min
Max
200
200
80
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
ns
(2)
tOE
OE to Output Delay
0
0
0
0
0
0
ns
(3)(4)
tDF
CE or OE to Output Float
30
40
50
ns
Output Hold from OE, CE or Address,
whichever comes first
tOH
0
0
0
ns
(1)(2)(3)(4)
AC Read Waveforms
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address
change without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement level
Output test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49BV/LV040
6
AT49BV/LV040
AC Byte Load Characteristics
Symbol
AS, tOES
Parameter
Min
0
Max
Units
ns
t
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
tDH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
tBP
Parameter
Min
Typ
Max
Units
µs
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
50
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
OE must be high only when WE and CE are both low.
AT49BV/LV040
8
AT49BV/LV040
(1)
Data Polling Characteristics
Symbol
tDH
Parameter
Min
0
Typ
Max
Units
ns
Data Hold Time
OE Hold Time
tOEH
tOE
10
ns
OE to Output Delay (2)
ns
tWR
Write Recovery Time
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
(1)
Toggle Bit Characteristics
Symbol
tDH
Parameter
Min
0
Typ
Max
Units
ns
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay (2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
(1)(2)(3)
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Software Product
Identification Entry
Boot Block Lockout
Feature Enable Algorithm
(1)
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(4)
LOAD DATA 40
TO
ADDRESS 5555
Software Product
Identification Exit
(1)
PAUSE 1 second(2)
OR
LOAD DATA AA
TO
LOAD DATA AA
TO
Notes for boot block lockout feature enable:
ADDRESS 5555
ADDRESS 5555
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE(4)
2. Boot block lockout feature enabled.
LOAD DATA F0
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 13H (AT49BV/LV040), 12H
(AT49BV/LV040T).
AT49BV/LV040
10
AT49BV/LV040
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
150
25
0.05
AT49BV040-15CC
AT49BV040-15JC
AT49BV040-15TC
AT49BV040-15VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
25
25
25
25
25
25
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49BV040-15CI
AT49BV040-15JI
AT49BV040-15TI
AT49BV040-15VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
200
150
200
AT49BV040-20CC
AT49BV040-20JC
AT49BV040-20TC
AT49BV040-20VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49BV040-20CI
AT49BV040-20JI
AT49BV040-20TI
AT49BV040-20VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
AT49BV040T-15CC
AT49BV040T-15JC
AT49BV040T-15TC
AT49BV040T-15VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49BV040T-15CI
AT49BV040T-15JI
AT49BV040T-15TI
AT49BV040T-15VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
AT49BV040T-20CC
AT49BV040T-20JC
AT49BV040T-20TC
AT49BV040T-20VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49BV040T-20CI
AT49BV040T-20JI
AT49BV040T-20TI
AT49BV040T-20VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
Package Type
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32J
32T
32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 20 mm
32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 14 mm
42-Ball, Plastic Chip-Scale Ball Grid Array (CBGA) 8 x 8 mm
32V
42C1
11
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
150
25
0.05
AT49LV040-15CC
AT49LV040-15JC
AT49LV040-15TC
AT49LV040-15VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
25
25
25
25
25
25
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49LV040-15CI
AT49LV040-15JI
AT49LV040-15TI
AT49LV040-15VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
200
150
200
AT49LV040-20CC
AT49LV040-20JC
AT49LV040-20TC
AT49LV040-20VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49LV040-20CI
AT49LV040-20JI
AT49LV040-20TI
AT49LV040-20VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
AT49LV040T-15CC
AT49LV040T-15JC
AT49LV040T-15TC
AT49LV040T-15VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49LV040T-15CI
AT49LV040T-15JI
AT49LV040T-15TI
AT49LV040T-15VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
AT49LV040T-20CC
AT49LV040T-20JC
AT49LV040T-20TC
AT49LV040T-20VC
42C1
32J
Commercial
(0°C to 70°C)
32T
32V
AT49LV040T-20CI
AT49LV040T-20JI
AT49LV040T-20TI
AT49LV040T-20VI
42C1
32J
Industrial
(-40°C to 85°C)
32T
32V
Package Type
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32J
32T
32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 20 mm
32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 14 mm
42-Ball, Plastic Chip-Scale Ball Grid Array (CBGA) 8 x 8 mm
32V
42C1
AT49BV/LV040
12
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