AT45DB321C-RI_技术文档

Features

• Single 2.7 - 3.6V Supply

• RapidS^™Serial Interface: 40 MHz Maximum Clock Frequency

(SPI Modes 0 and 3 Compatible for Frequencies Up to 33 MHz)

• Page Program

– 8192 Pages (528 Bytes/Page)

• Automated Erase Operations

– Page Erase 528 Bytes

– Block Erase 4,224 Bytes

• Two 528-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming the Flash Array

• Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

• Low-power Dissipation

– 10 mA Active Read Current Typical – Serial Interface

– 8 µA CMOS Standby Current Typical

• Hardware and Software Data Protection Features

– Individual Sector Locking

32-megabit

2.7 volt

DataFlash^®

• Security: 128-byte Security Register

– 64-byte User Programmable Space

– Unique 64-byte Device Identifier

• JEDEC Standard Manufacturer and Device ID Read

• 100,000 Program/Erase Cycles per Page

• Data Retention – 20 years

AT45DB321C

Preliminary

• Commercial and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Options

Description

The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited

for a wide variety of digital voice-, image-, program code- and data-

storage applications. The AT45DB321C supports a 4-wire serial interface known as

RapidS for applications requiring very high speed operations.

Pin Configurations

TSOP Top View – Type 1

Pin Name

Function

RDY/BUSY

RESET

WP

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

NC

2

CS

Chip Select

Serial Clock

Serial Input

Serial Output

3

NC

4

NC

5

SCK

SI

VCC

GND

NC

6

7

8

NC

9

SO

NC

10

11

12

13

14

CS

SCK

SI

Hardware Page

Write Protect Pin

WP

SO

RESET

Chip Reset

CASON – Top View

through Package

CBGA Top View

through Package

RDY/BUSY Ready/Busy

1

2

3

4

5

DataFlash Card⁽¹⁾

Top View through Package

SI

SCK

1

2

3

4

8

7

6

5

SO

GND

VCC

WP

RESET

CS

A

B

C

D

E

NC

7

6 5 4 3 2 1

NC SCK GND VCC NC

NC

CS RDY/BSY WP NC

SO

NC

SI RESET NC

NC

NC NC

3387B–DFLSH–9/04

Note:

1. See AT45DCB004 Datasheet

1

Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-

tion to the 33-megabit main memory, the AT45DB321C also contains two SRAM

buffers of 528 bytes each.

The buffers allow the receiving of data while a page in the main page Memory is being

reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or

byte alterability) is easily handled with a self-contained three step read-modify-write

operation. Unlike conventional Flash memories that are accessed randomly with multi-

ple address lines and a parallel interface, the DataFlash uses a RapidS serial interface

to sequentially access its data. The simple sequential access dramatically reduces

active pin count, facilitates hardware layout, increases system reliability, minimizes

switching noise, and reduces package size. The device is optimized for use in many

commercial and industrial applications where high-density, low-pin count, low-voltage

and low-power are essential. The device operates at clock frequencies up to 40 MHz

with a typical active read current consumption of 10 mA.

To allow for simple in-system reprogrammability, the AT45DB321C does not require

high input voltages for programming. The device operates from a single power supply,

2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled

through the chip select pin (CS) and accessed via a three-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

Block Diagram

WP

FLASH MEMORY ARRAY

PAGE (528 BYTES)

BUFFER 1 (528 BYTES)

BUFFER 2 (528 BYTES)

SCK

CS

I/O INTERFACE

RESET

VCC

GND

RDY/BUSY

SI

SO

Memory Array

To provide optimal flexibility, the memory array of the AT45DB321C is divided into three

levels of granularity comprising of sectors, blocks, and pages. The “Memory Architec-

ture Diagram” illustrates the breakdown of each level and details the number of pages

per sector and block. All program operations to the DataFlash occur on a page by page

basis. The erase operations can be performed at the block or page level.

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AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Memory Architecture Diagram

SECTOR ARCHITECTURE

BLOCK ARCHITECTURE

PAGE ARCHITECTURE

BLOCK 0

BLOCK 1

BLOCK 2

8 Pages

PAGE 0

PAGE 1

SECTOR 0a

SECTOR 0a = 8 Pages

4224 bytes (4K + 128)

SECTOR 0b = 504 Pages

266,112 bytes (252K + 8064)

PAGE 6

PAGE 7

PAGE 8

PAGE 9

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

SECTOR 1 = 512 Pages

270,336 bytes (256K + 8K)

SECTOR 2 = 512 Pages

270,336 bytes (256K + 8K)

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

BLOCK 126

BLOCK 127

BLOCK 128

BLOCK 129

SECTOR 14 = 512 Pages

270,336 bytes (256K + 8K)

PAGE 8189

PAGE 8190

PAGE 8191

SECTOR 15 = 512 Pages

270,336 bytes (256K + 8K)

BLOCK 1022

BLOCK 1023

Block = 4224 bytes

(4K + 128)

Page = 528 bytes

(512 + 16)

Device Operation

The device operation is controlled by instructions from the host processor. The list of

instructions and their associated opcodes are contained in Tables 1 through 4. A valid

instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode

and the desired buffer or main memory address location. While the CS pin is low, tog-

gling the SCK pin controls the loading of the opcode and the desired buffer or main

memory address location through the SI (serial input) pin. All instructions, addresses,

and data are transferred with the most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA9-BFA0 to

denote the 10 address bits required to designate a byte address within a buffer. Main

memory addressing is referenced using the terminology PA12-PA0 and BA9-BA0,

where PA12-PA0 denotes the 13 address bits required to designate a page address and

BA9-BA0 denotes the 10 address bits required to designate a byte address within the

page.

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from

either one of the two SRAM data buffers. The DataFlash supports RapidS protocol for

Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in

this datasheet for details on the clock cycle sequences for each mode.

CONTINUOUS ARRAY READ: By supplying an initial starting address for the main

memory array, the Continuous Array Read command can be utilized to sequentially

read a continuous stream of data from the device by simply providing a clock signal; no

additional addressing information or control signals need to be provided. The DataFlash

incorporates an internal address counter that will automatically increment on every clock

cycle, allowing one continuous read operation without the need of additional address

sequences. To perform a continuous read, an opcode of E8H must be clocked into the

device. The opcode is followed by three address bytes (which comprises 24-bit page

and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit

address sequence is reserved for upward and downward compatibility to larger and

3

3387B–DFLSH–9/04

smaller density devices (see the notes under “Command Sequence for Read/Write

Operations (except Status Register Read)” on page 22. The next 13 bits (PA12-PA0) of

the 24-bit address sequence specify which page of the main memory array to read, and

the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte

address within the page. The 32 don’t care clock cycles that follow the four address

bytes are needed to initialize the read operation. Following the don’t care clock cycles,

additional clock pulses on the SCK pin will result in data being output on the SO (serial

output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the

don’t care bytes, and the reading of data. When the end of a page in main memory is

reached during a Continuous Array Read, the device will continue reading at the begin-

ning of the next page with no delays incurred during the page boundary crossover (the

crossover from the end of one page to the beginning of the next page). When the last bit

in the main memory array has been read, the device will continue reading back at the

beginning of the first page of memory. As with crossing over page boundaries, no delays

will be incurred when wrapping around from the end of the array to the beginning of the

array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the

output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read

is defined by the f_CARspecification. The Continuous Array Read bypasses both data

buffers and leaves the contents of the buffers unchanged.

MAIN MEMORY PAGE READ: A main memory page read allows the user to read data

directly from any one of the 8192 pages in the main memory, bypassing both of the data

buffers and leaving the contents of the buffers unchanged. To start a page read, an

opcode of D2H must be clocked into the device. The opcode is followed by three

address bytes (which comprise 24-bit page and byte address sequence) and 32 don’t

care clock cycles. The first bit of the 24-bit address sequence is a reserved bit, the next

13 bits (PA12-PA0) of the 24-bit address sequence specify the page in main memory to

be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the start-

ing byte address within that page. The 32 don’t care clock cycles that follow the three

address bytes are sent to initialize the read operation. Following the don’t care bytes,

additional pulses on SCK result in data being output on the SO (serial output) pin. The

CS pin must remain low during the loading of the opcode, the address bytes, the don’t

care bytes, and the reading of data. When the end of a page in main memory is

reached, the device will continue reading back at the beginning of the same page. A

low-to-high transition on the CS pin will terminate the read operation and tri-state the

output pin (SO). The maximum SCK frequency allowable for the Main Memory Page

Read is defined by the f_SCKspecification. The Main Memory Page Read bypasses both

data buffers and leaves the contents of the buffers unchanged.

BUFFER READ: Data can be read from either one of the two buffers, using different

opcodes to specify which buffer to read from. An opcode of D4H is used to read data

from buffer 1, and an opcode of D6H is used to read data from buffer 2. To perform a

buffer read, the opcode must be clocked into the device followed by three address bytes

comprised of 14 don’t care bits and 10 buffer address bits (BFA9-BFA0). Following the

three address bytes, an additional don’t care byte must be clocked in to initialize the

read operation. Since the buffer size is 528 bytes, 10 buffer address bits are required to

specify the first byte of data to be read from the buffer. The CS pin must remain low dur-

ing the loading of the opcode, the address bytes, the don’t care bytes, and the reading

of data. When the end of a buffer is reached, the device will continue reading back at the

beginning of the buffer. A low-to-high transition on the CS pin will terminate the read

operation and tri-state the output pin (SO).

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AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Program and Erase

Commands

BUFFER WRITE: Data can be clocked in from the SI pin into either buffer 1 or buffer 2.

To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2,

must be clocked into the device, followed by three address bytes comprised of 14 don’t

care bits and 10 buffer address bits (BFA9-BFA0). The 10 buffer address bits specify

the first byte in the buffer to be written. After the last address byte has been clocked into

the device, data can then be clocked in on subsequent clock cycles. If the end of the

data buffer is reached, the device will wrap around back to the beginning of the buffer.

Data will continue to be loaded into the buffer until a low-to-high transition is detected on

the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written

into either buffer 1 or buffer 2 can be programmed into the main memory. To start the

operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the

device followed by three address bytes consisting of one reserved bit, 13 page address

bits (PA12-PA0) that specify the page in the main memory to be written and 10 don’t

care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the

selected page in main memory (the erased state is a logic 1) and then program the data

stored in the buffer into the specified page in main memory. Both the erase and the pro-

gramming of the page are internally self-timed and should take place in a maximum time

of t_EP. During this time, the status register and the RDY/BUSY pin will indicate that the

part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previ-

ously-erased page within main memory can be programmed with the contents of either

buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for

buffer 2, must be clocked into the device followed by three address bytes consisting of

one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the main

memory to be written and 10 don’t care bits. When a low-to-high transition occurs on the

CS pin, the part will program the data stored in the buffer into the specified page in the

main memory. It is necessary that the page in main memory that is being programmed

has been previously erased using one of the erase commands (Page Erase or Block

Erase). The programming of the page is internally self-timed and should take place in a

maximum time of t_P. During this time, the status register and the RDY/BUSY pin will indi-

cate that the part is busy.

PAGE ERASE: The Page Erase command can be used to individually erase any page

in the main memory array allowing the Buffer to Main Memory Page Program without

Built-in Erase command to be utilized at a later time. To perform a page erase, an

opcode of 81H must be loaded into the device, followed by three address bytes com-

prised of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the

main memory to be erased and 10 don’t care bits. When a low-to-high transition occurs

on the CS pin, the part will erase the selected page (the erased state is a logic 1). The

erase operation is internally self-timed and should take place in a maximum time of t_PE.

During this time, the status register and the RDY/BUSY pin will indicate that the part is

busy.

BLOCK ERASE: A block of eight pages can be erased at one time. This command is

useful when large amounts of data has to be written into the device. This will avoid using

multiple Page Erase Commands. To perform a block erase, an opcode of 50H must be

loaded into the device, followed by three address bytes comprised of one reserved bit,

10 page address bits (PA12-PA3) and 13 don’t care bits. The 10 page address bits are

used to specify which block of eight pages is to be erased. When a low-to-high transition

occurs on the CS pin, the part will erase the selected block of eight pages. The erase

operation is internally self-timed and should take place in a maximum time of t_BE. During

this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

5

3387B–DFLSH–9/04

Block Erase Addressing

PA12

PA11

PA10

PA9

PA8

0

PA7

0

PA6

0

PA5

0

PA4

0

PA3

0

PA2

X

PA1

X

PA0

X

Block

0

1

2

3

0

1

X

0

1

0

X

0

1

X

•

1

0

1

0

1

0

1

X

1020

1021

1022

1023

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-

tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase

operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then

programmed into a specified page in the main memory. To initiate the operation, an 8-bit

opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, fol-

lowed by three address bytes. The address bytes are comprised of one reserved bit, 13

page address bits (PA12-PA0) that select the page in the main memory where data is to

be written, and 10 buffer address bits (BFA9-BFA0) that select the first byte in the buffer

to be written. After all address bytes are clocked in, the part will take data from the input

pins and store it in the specified data buffer. If the end of the buffer is reached, the

device will wrap around back to the beginning of the buffer. When there is a low-to-high

transition on the CS pin, the part will first erase the selected page in main memory to all

1s and then program the data stored in the buffer into that memory page. Both the erase

and the programming of the page are internally self-timed and should take place in a

maximum time of t_EP. During this time, the status register and the RDY/BUSY pin will

indicate that the part is busy.

Additional Commands

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred

from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte

opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed

by three address bytes comprised of one reserved bit, 13 page address bits (PA12-

PA0), which specify the page in main memory that is to be transferred, and 10 don’t care

bits. The CS pin must be low while toggling the SCK pin to load the opcode and the

address bytes from the input pin (SI). The transfer of the page of data from the main

memory to the buffer will begin when the CS pin transitions from a low to a high state.

During the transfer of a page of data (t_XFR), the status register can be read or the

RDY/BUSY can be monitored to determine whether the transfer has been completed.

AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or

multiple pages of data are modified in a random fashion. This mode is a combination of

two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page

Program with Built-in Erase. A page of data is first transferred from the main memory to

buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed

back into its original page of main memory. To start the rewrite operation, a 1-byte

opcode, 58H for buffer 1 or 59H for buffer 2, must be clocked into the device, followed

by three address bytes comprised of one reserved bit, 13 page address bits (PA12-PA0)

6

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

that specify the page in main memory to be rewritten and 10 don’t care bits. When a low-

to-high transition occurs on the CS pin, the part will first transfer data from the page in

main memory to a buffer and then program the data from the buffer back into same

page of main memory. The operation is internally self-timed and should take place in a

maximum time of t_EP. During this time, the status register and the RDY/BUSY pin will

indicate that the part is busy.

If a sector is programmed or reprogrammed sequentially page by page, then the pro-

gramming algorithm shown in Figure 1 on page 29 is recommended. Otherwise, if

multiple bytes in a page or several pages are programmed randomly in a sector, then

the programming algorithm shown in Figure 2 on page 30 is recommended. Each page

within a sector must be updated/rewritten at least once within every 10,000 cumulative

page erase/program operations in that sector.

STATUS REGISTER READ: The status register can be used to determine the device’s

ready/busy status, or whether the sector protection has been enabled. To read the sta-

tus register, an opcode of D7H must be loaded into the device. After the opcode and

optional dummy byte is clocked in, the 1-byte status register will be clocked out on the

output pin (SO), starting with the next clock cycle. For applications over 25 MHz, the

opcode must be always followed with a dummy (don’t care) byte. The data in the status

register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next

eight clock cycles.

The most-significant bits of the status register will contain device information, while the

remaining least-significant bit is reversed for future use and will have undefined value.

After the one byte of the status register has been clocked out, the sequence will repeat

itself (as long as CS remains low and SCK is being toggled). The data in the status reg-

ister is constantly updated, so each repeating sequence will output new data.

Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the

device is not busy and is ready to accept the next command. If bit 7 is a 0, then the

device is in a busy state. There are many operations that can cause the device to be in

a busy state: Main Memory Page to Buffer Transfer, Buffer to Main Memory Page Pro-

gram with Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase,

Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite.

Bit 1 in the Status Register is used to provide information to the user whether or not the

sector protection has been enabled or disabled, either by software-controlled method or

hardware-controlled method. A logic 1 indicates that sector protection has been enabled

and logic 0 indicates that sector protection has been disabled.

The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the

AT45DB321C, the four bits are 1,1, 0, 1. The decimal value of these four binary bits

does not equate to the device density; the four bits represent a combinational code

relating to differing densities of DataFlash devices. The device density is not the same

as the density code indicated in the JEDEC device ID information. The device density is

provided only for backward compatibility.

Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY/BUSY

X

1

0

1

Protect

X

7

3387B–DFLSH–9/04

Sector Protection

Two protection methods, hardware and software controlled, are provided. The selection

of which sectors to be protected/unprotected from program and erase operations is

defined in the Sector Protection Register.

SOFTWARE SECTOR PROTECTION: Sectors specified for protection in the Sector

Protection Register can be protected from program and erase operations by issuing the

Enable Sector Protection command. To enable the sector protection using the software

controlled method, the CS pin must first be asserted as it would be with any other com-

mand. Once the CS pin has been asserted, the appropriate 4-byte command sequence

must be clocked in via the input pin (SI). After the last bit of the command sequence has

been clocked in, the CS pin must be deasserted after which the sector protection will be

enabled.

Command

Byte 1

3DH

Byte 2

2AH

Byte 3

7FH

Byte 4

A9H

Enable Sector Protection

Disable Sector Protection

Read Sector Protection Register

3DH

2AH

7FH

9AH

32H

00H

To disable the sector protection using the software controlled method, the CS pin must

first be asserted as it would be with any other command. Once the CS pin has been

asserted, the appropriate 4-byte sequence for the Disable Sector Protection command

must be clocked in via the input pin (SI). After the last bit of the command sequence has

been clocked in, the CS pin must be deasserted after which the sector protection will be

disabled. The Disable Sector Protection command is ignored while the WP pin is

asserted.

Software Sector Protection is useful in applications in which the WP pin is not or cannot

be controlled by a host processor. In such instances, the WP pin may be left floating (the

WP pin is pulled high internally) and sector protection can be controlled using the soft-

ware commands.

If the device is power cycled, then the Software Sector Protection will be disabled. Once

the device is powered up, the Enable Sector Protection command should be reissued if

sector protection is desired and if the WP pin is not used. The RESET pin has no effect

on the Software Sector Protection.

HARDWARE SECTOR PROTECTION: Sectors specified for protection in Sector Pro-

tection Register can be protected from program and erase operations by utilizing the

Write Protection (WP) pin. The protection can be enabled by asserting the WP pin and

keeping the pin in its asserted state. Any sector specified for protection cannot be

erased or reprogrammed as long as the WP pin is asserted. The protection can be dis-

abled by deasserting the WP pin high. A filter is provided on the WP pin to help protect

against spurious noise on the WP pin. Hardware Sector Protection will provide continu-

ous protection, based on the contents of the Sector Protection Register, in an

application where WP is always driven low. Please read the description of the WP pin on

page 13 for more information.

SECTOR PROTECTION REGISTER: Sector Protection Register is a nonvolatile regis-

ter that contains 16 bytes of data, as shown below:

Sector Number

Protected

0 (0a, 0b)

1 to 15

FFH

See Below

Unprotected

00H

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AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Sector 0 (0a, 0b):

0b

(Page 8-255)

Bit 4, 5

0b

(Page 256-511)

Bit 2, 3

0a

–

Data

Value

Bit 6, 7

Bit 0, 1

00

Sectors 0a, 0b

Unprotected

00

00H

Protect Sector 0a

11

00

11

00

C0H

30H

Protect Sector 0b

(Page 8-255)

Protect Sector 0b

(Page 256-511)

00

11

00

11

00

0CH

FCH

Protect Sectors 0a,

0b (Page 8-255), 0b

(Page 256-511)⁽¹⁾

Protect Sectors 0a,

0b (Page 8-255)

11

00

F0H

Note:

1. Default value for devices shipped from Atmel.

2. When protecting or unprotecting sector 0b (pages 8-511), we recommend protecting

or unprotecting the entire sector 0b simultaneously.

ERASING THE SECTOR PROTECTION REGISTER: To erase the Sector Protection

Register, the CS pin must first be asserted. Once the CS pin has been asserted, the

4-byte erase command sequence must be clocked in via the SI (serial input) pin. After

the last bit of the command sequence has been clocked in, the CS pin must be deas-

serted to initiate the internally self-timed erase cycle (t_PE). The Ready/Busy status will

indicate that the device is busy during the erase cycle. The erased state of each bit (of a

byte) in the Sector Protection Register indicates that the corresponding sector is flagged

for protection. The RESET pin is disabled during this erase cycle to prevent incomplete

erasure of the Sector Protection Register.

Command

Byte 1

Byte 2

Byte 3

Byte 4

Erase Sector Protection Register

3DH

2AH

7FH

CFH

PROGRAMMING THE SECTOR PROTECTION REGISTER: To program the Sector

Protection Register, the CS pin must first be asserted. Once the CS pin has been

asserted, the 4-byte command sequence must be clocked in via the SI (serial input) pin.

After the last bit of the command sequence has been clocked in, the data for the con-

tents of the Sector Protection Register must be clocked in. The first byte corresponds to

sector 0 (0a, 0b), the second byte corresponds to Sector 1 and the last byte (byte 16)

corresponds to Sector 15. After the last bit of data has been clocked in, the CS pin must

be deasserted to initiate the internally self-timed program cycle (t_P). The Ready/Busy

status will indicate that the device is busy during the program cycle. The RESET pin is

disabled during this program cycle to prevent incomplete programming of the sector pro-

tection register.

Command

Byte 1

Byte 2

Byte 3

Byte 4

Program Sector Protection Register

3DH

2AH

7FH

FCH

READING THE SECTOR PROTECTION REGISTER: To read the Sector Protection

Register, the CS pin must first be asserted. Once the CS pin has been asserted, a

4-byte command sequence 32H, 00H, 00H, 00H and 32 don’t care clock cycles must be

clocked in via the SI (serial input) pin. The 32 don’t care clock cycles are required to ini-

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3387B–DFLSH–9/04

tialize the read operation. After the 32 don’t care clock cycles, any additional clock

pulses on the SCK pin will result in data being output on the SO (serial output) pin. The

read will begin with Byte_1 of the Sector Protection Register for Sector_0, followed with

Byte_2 for Sector_1. The read operation will continue until Byte_16 for Sector_15 is

read. Once the last byte is read a low-to-high transition on the CS pin is required to ter-

minate the read operation.

Command

Byte 1

Byte 2

Byte 3

Byte 4

Read Sector Protection Register

32H

00H

VARIOUS ASPECTS ABOUT THE SECTOR PROTECTION REGISTER: Due to the

sharing of the internal circuitry, the contents of the buffer 1 will get modified during the

erase and programming of Sector Protection Register. If the device is powered down

during erasing or programming the sector protection register, then the contents of the

Sector Protection Register cannot be guaranteed. The Sector Protection Register can

be erased or reprogrammed with the sector protection enabled or disabled. Being able

to reprogram the Sector Protection Register with the sector protection enabled allows

the user to temporarily disable the sector protection to an individual sector rather than

disabling the sector protection completely.

The Sector Protection Register is subject to the same endurance characteristics as the

main memory array. Users are encouraged to carefully evaluate the number of times the

Sector Protection Register will be modified during the course of the applications’ life

cycle. If the application requires that the Sector Protection Register be modified more

than the specified endurance of the DataFlash because the application needs to tempo-

rarily unprotect individual sectors (sector protection remains enabled while the Sector

Protection Register is reprogrammed), then the application will need to limit this prac-

tice. Instead, a combination of temporarily unprotecting individual sectors along with

disabling sector protection completely will need to be implemented by the application to

ensure that the endurance limits of the device are not exceeded.

10

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Manufacturer and Device ID Read

This instruction conforms to the JEDEC standard and allows the user to read the Manufacturer ID, Device ID, and Extended

Device Information. A 1-byte opcode, 9FH, must be clocked into the device while the CS pin is low. After the opcode is

clocked in, the Manufacturer ID, 2 bytes of Device ID and Extended Device Information will be clocked out on the SO pin.

The fourth byte of the sequence output is the Extended Device Information String Length byte. This byte is used to signify

how many bytes of Extended Device Information will be output.

Manufacturer and Device ID Information

Byte 1 – Manufacturer ID

JEDEC Assigned Code

Hex

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1FH

0

1

Manufacturer ID

1FH = Atmel

Byte 2 – Device ID (Part 1)

Family Code

Hex

Density Code

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Family Code

Density Code

001 = DataFlash

00111 = 32-Mbit

27H

0

1

0

1

Byte 3 – Device ID (Part 2)

MLC Code

Hex

Product Version Code

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MLC Code

000 = 1-bit/Cell Technology

00000 = Initial Version

00H

0

Product Version

Byte 4 – Extended Device Information String Length

Byte Count

Hex

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00H

0

Byte Count

00H = 0 Bytes of Information

CS

9FH

SI

Opcode

1FH

27H

00H

Data

SO

Manufacturer ID

Byte n

Device ID

Byte 1

Device ID

Byte 2

Extended

Device

Extended

Device

Information

Byte x

Extended

Device

Information

Byte x + 1

Information

String Length

This information

would only be output

if the Extended Device

Information String Length

value was something

other than 00H.

Each transition represents

8 bits and 8 clock cycles

Note:

Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have

Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code

7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID

data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.

11

3387B–DFLSH–9/04

Security Register

The AT45DB321C contains a specialized register that can be used for security pur-

poses in system design. The Security Register is a unique 128-byte register that is

divided into two portions. The first 64 bytes (byte 0 to byte 63) of this page are allocated

as a one-time user programmable space. Once these 64 bytes have been programmed,

they should not be reprogrammed. The remaining 64 bytes of this page (byte 64 to byte

127) are factory programmed by Atmel and will contain a unique number for each

device. The factory programmed data is fixed and cannot be changed.

The Security Register can be read by clocking in opcode 77H to the device followed by

three address bytes (which are comprised of 14 don’t care bits plus 10 address bits) and

32 don’t care clock cycles. See the opcode table on page 17.

To program the first 64 bytes of the Security Register, a two step sequence must be

used. The first step requires that the user loads the desired data into Buffer 1 by using

the Buffer 1 Write operation (opcode 84H – see Buffer Write description on page 5). The

user should specify the starting buffer address as location zero and should write a full

64 bytes of information into the buffer. Otherwise, the first 64 bytes of the buffer may

contain data that was previously stored in the buffer. It is not necessary to fill the remain-

ing 464 bytes (byte locations 64 through 127) of the buffer with data. After the Buffer 1

Write operation has been completed, the Security Register can be subsequently pro-

grammed by reselecting the device and clocking in opcode 9AH into the device followed

by three don’t care bytes (24 clock cycles). After the final don’t care clock cycle has

been completed, a low-to-high transition on the CS pin will cause the device to initiate

an internally self-timed program operation in which the contents of Buffer 1 will be pro-

grammed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be

programmed into the Security Register; the remaining 464 bytes of the buffer will be

ignored. The Security Register program operation should take place in a maximum time

of t_P.

Operation Mode

Summary

The modes described can be separated into two groups – modes that make use of the

Flash memory array (Group A) and modes that do not make use of the Flash memory

array (Group B).

Group A modes consist of:

1. Main Memory Page Read

2. Continuous Array Read

3. Main Memory Page to Buffer 1 (or 2) Transfer

4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase

5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase

6. Main Memory Page Program through Buffer 1 (or 2)

7. Page Erase

8. Block Erase

9. Auto Page Rewrite

Group B modes consist of:

1. Buffer 1 (or 2) Read

2. Buffer 1 (or 2) Write

3. Status Register Read

4. Manufacturer and Device ID Read

If a Group A mode is in progress (not fully completed), then another mode in Group A

should not be started. However, during this time in which a Group A mode is in

12

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

progress, modes in Group B can be started, except the first two Group A commands

(Memory Array Read Commands).

This gives the DataFlash the ability to virtually accommodate a continuous data stream.

While data is being programmed into main memory from buffer 1, data can be loaded

into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial

DataFlash”) for more details.

Pin Descriptions

SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into

the device. The SI pin is used for all data input, including opcodes and address

sequences.

SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data seri-

ally out from the device.

SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow

of data to and from the DataFlash. Data is always clocked into the device on the rising

edge of SCK and clocked out of the device on the falling edge of SCK.

CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the

device is not selected, data will not be accepted on the input pin (SI), and the output pin

(SO) will remain in a high impedance state. A high-to-low transition on the CS pin is

required to start an operation, and a low-to-high transition on the CS pin is required to

end an operation or to start an internally self-timed operation.

WRITE PROTECT (WP): The WP pin is used to control the Hardware Sector Protection.

Hardware Sector Protection is enabled by asserting the WP pin and keeping the pin in

it’s asserted state. Disabling Hardware Sector Protection is accomplished by simply

deasserting the WP pin. The WP pin will override the software controlled sector protec-

tion method but only for protecting the sectors. For example, if the sectors were not

previously protected by the Enable Sector Protection command, then simply asserting

the WP pin for the minimum specified time (t_WPE) would enable the sector protection.

When the WP pin is deasserted; however, the sector protection would no longer be

enabled as long as the Enable Sector Protection command was not issued while the WP

pin was asserted. If the Enable Sector Protection command was issued before or while

the WP pin was asserted, then simply deasserting the WP pin would not disable the sec-

tor protection. In this case, the Disable Sector Protection command would need to be

issued while the WP pin is deasserted to disable the sector protection. The Disable Sec-

tor Protection command is also ignored whenever the WP pin is asserted.

To ensure backwards compatibility with previous generations of DataFlash, the function

of the WP pin has not changed. Therefore, when the WP pin is asserted, certain sectors

in the memory array will be protected, and when the WP pin is deasserted, the memory

array will be unprotected provided the Enable Sector Protection command hasn’t been

issued. New devices are shipped from Atmel with the contents of the Sector Protection

Register pre-programmed so that sectors 0a and 0b are specified for protection while

the remaining sectors are not flagged for protection. The user can reprogram the Sector

Protection Register to change which sectors will be protected by the WP pin.

The table below details the sector protection status for various scenarios of the WP pin,

the Enable Sector Protection command, and the Disable Sector Protection command.

1

2

3

WP

13

3387B–DFLSH–9/04

Time

Period

WP Pin

Enable Sector Protection Command

Disable Sector Protection Command

Sector Protection Status

High

Command Not Issued Previously

x

Disabled

Enabled

Disabled

1

2

3

Command Issued

–

Command Issued

Low

x

Enabled

High

Command Issued during Period 1 or 2

Not Issued Yet

Command Issued

–

Enabled

Disabled

Enabled

–

Issue Command

RESET: A low state on the reset pin (RESET) will terminate the operation in progress

and reset the internal state machine to an idle state. The device will remain in the reset

condition as long as a low level is present on the RESET pin. Normal operation can

resume once the RESET pin is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions

on the RESET pin during power-on sequences. The RESET pin is also internally pulled

high; therefore, in low pin count applications, connection of the RESET pin is not neces-

sary if this pin and feature will not be utilized. However, it is recommended that the

RESET pin be driven high externally whenever possible.

READY/BUSY: This open drain output pin will be driven low when the device is busy in

an internally self-timed operation. This pin, which is normally in a high state (through

an external pull-up resistor), will be pulled low during programming/erase operations,

and page-to-buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be

accessed; read and write operations to the other buffer can still be performed. During

Page Erase and Block Erase, read and write operations can be performed to both

buffers.

14

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

AT45DB321C [Preliminary]

Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the

device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance

state, and a high-to-low transition on the CS pin will be required to start a valid instruc-

tion. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge

of CS by sampling the inactive clock state. After power is applied and V_CCis at the mini-

mum datasheet value, the system should wait 20 ms before an operational mode

(DataFlash) is started.

System

Considerations

The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip

select CS pins. These signals must rise and fall monotonically and be free from noise.

Excessive noise or ringing on these pins can be misinterpreted as multiple edges and

cause improper operation of the device. The PC board traces must be kept to a mini-

mum distance or appropriately terminated to ensure proper operation. If necessary,

decoupling capacitors can be added on these pins to provide filtering against noise

glitches.

As system complexity continues to increase, voltage regulation is becoming more

important. A key element of any voltage regulation scheme is its current sourcing capa-

bility. Like all Flash memories, the peak current for DataFlash occur during the

programming and erase operation. The regulator needs to supply this peak current

requirement. An under specified regulator can cause current starvation. Besides

increasing system noise, current starvation during programming or erase can lead to

improper operation and possible data corruption.

For applications that require random modifications of data within a sector, please refer

to “Auto Page Rewrite” on page 6.

It is recommended that the RDY/BUSY bit of status register or the RDY/BUSY pin be

monitored in order to minimize the erase and programming time.

Atmel C generation DataFlash utilizes a sophisticated adaptive algorithm during erase

and programming to maximize the endurance over the life of the device. The algorithm

uses a verification mechanism to check if the memory cells have been erased or pro-

grammed successfully. If the memory cells were not erased or programmed, the

algorithm loops back and erases or programs the memory cells again. The process will

continue until the device is erased or programmed successfully.

The erase and programming operations are internally self-timed and fixed timing is not

recommended.

15

3387B–DFLSH–9/04

Table 1. Read Commands

Command

SCK Mode

Opcode

E8H

68H

RapidS Mode 0 or 3

Continuous Array Read

Main Memory Page Read

Buffer 1 Read