AT32UC3L0256-ZAUR_技术文档

Features

• High-performance, Low-power 32-bit Atmel^®AVR^®Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instructions

– Read-modify-write Instructions and Atomic Bit Manipulation

– Performance

• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)

• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)

– Memory Protection Unit (MPU)

• Secure Access Unit (SAU) providing User-defined Peripheral Protection

• picoPower^®Technology for Ultra-low Power Consumption

• Multi-hierarchy Bus System

– High-performance Data Transfers on Separate Buses for Increased Performance

– 12 Peripheral DMA Channels Improve Speed for Peripheral Communication

• Internal High-speed Flash

32-bit Atmel

AVR

Microcontroller

– 256Kbytes and 128Kbytes Versions

– Single-cycle Access up to 25MHz

AT32UC3L0256

AT32UC3L0128

– FlashVault Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User-defined Configuration Area

• Internal High-speed SRAM, Single-cycle Access at Full Speed

– 32Kbytes

Summary

• Interrupt Controller (INTC)

– Autovectored Low-latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• Peripheral Event System for Direct Peripheral to Peripheral Communication

• System Functions

– Power and Clock Manager

– SleepWalking Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32KHz Oscillator

– Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked

Loop (DFLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Six 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture, and Various Counting Capabilities

• PWM Channels on All I/O Pins (PWMA)

– 8-bit PWM with a Source Clock up to 150MHz

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

32145BS–01/2012

AT32UC3L0128/256

• Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I²C-compatible

• One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution

– Internal Temperature Sensor

• Eight Analog Comparators (AC) with Optional Window Detection

• Capacitive Touch (CAT) Module

– Hardware-assisted Atmel^®AVR^®QTouch^®and Atmel^®AVR^®QMatrix Touch Acquisition

– Supports QTouch and QMatrix Capture from Capacitive Touch Sensors

• QTouch Library Support

– Capacitive Touch Buttons, Sliders, and Wheels

– QTouch and QMatrix Acquisition

• On-chip Non-intrusive Debug System

– Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace

– aWire Single-pin Programming Trace and Debug Interface Muxed with Reset Pin

– NanoTrace Provides Trace Capabilities through JTAG or aWire Interface

• 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)

• Five High-drive I/O Pins

• Single 1.62-3.6 V Power Supply

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1. Description

The Atmel^®AVR^®AT32UC3L0128/256 is a complete system-on-chip microcontroller based on

the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-per-

formance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications,

with particular emphasis on low power consumption, high code density, and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-

troller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is

used together with the MPU to provide the required security and integrity.

Higher computation capability is achieved using a rich set of DSP instructions.

The AT32UC3L0128/256 embeds state-of-the-art picoPower technology for ultra-low power con-

sumption. Combined power control techniques are used to bring active current consumption

down to 174µA/MHz, and leakage down to 220nA while still retaining a bank of backup regis-

ters. The device allows a wide range of trade-offs between functionality and power consumption,

giving the user the ability to reach the lowest possible power consumption with the feature set

required for the application.

The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-

erals and memories without processor involvement. The Peripheral DMA controller drastically

reduces processing overhead when transferring continuous and large data streams.

The AT32UC3L0128/256 incorporates on-chip Flash and SRAM memories for secure and fast

access. The FlashVault technology allows secure libraries to be programmed into the device.

The secure libraries can be executed while the CPU is in Secure State, but not read by non-

secure software in the device. The device can thus be shipped to end customers, who will be

able to program their own code into the device to access the secure libraries, but without risk of

compromising the proprietary secure code.

The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each

external interrupt has its own interrupt request and can be individually masked.

The Peripheral Event System allows peripherals to receive, react to, and send peripheral events

without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low

power sleep modes.

The Power Manager (PM) improves design flexibility and security. The Power Manager supports

SleepWalking functionality, by which a module can be selectively activated based on peripheral

events, even in sleep modes where the module clock is stopped. Power monitoring is supported

by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The

device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency

Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these

oscillators can be used as source for the system clock. The DFLL is a programmable internal

oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate reference clock is

running, e.g. the 32KHz crystal oscillator.

The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-

ware. This allows the device to recover from a condition that has caused the system to be

unstable.

The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful

real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in

counter mode or calendar mode.

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The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it

to a known reference clock.

The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-

pendently programmed to perform frequency measurement, event counting, interval

measurement, pulse generation, delay timing, and pulse width modulation.

The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be syn-

chronized and controlled from a common timer. One PWM channel is available for each I/O pin

on the device, enabling applications that require multiple PWM outputs, such as LCD backlight

control. The PWM channels can operate independently, with duty cycles set individually, or in

interlinked mode, with multiple channels changed at the same time.

The AT32UC3L0128/256 also features many communication interfaces, like USART, SPI, and

TWI, for communication intensive applications. The USART supports different communication

modes, like SPI Mode and LIN Mode.

A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The

ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering

up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel.

The analog comparators can be paired to detect when the sensing voltage is within or outside

the defined reference window.

The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using

the QTouch technology. Capacitive touch sensors use no external mechanical components,

unlike normal push buttons, and therefore demand less maintenance in the user application.

The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced.

All touch sensors can be configured to operate autonomously without software interaction,

allowing wakeup from sleep modes when activated.

Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels

functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers

robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key

Suppression^®(AKS^®) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.

The AT32UC3L0128/256 integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System, with

non-intrusive real-time trace and full-speed read/write memory access, in addition to basic run-

time control. The NanoTrace interface enables trace feature for aWire- or JTAG-based

debuggers. The single-pin aWire interface allows all features available through the JTAG inter-

face to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or

peripherals.

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2. Overview

2.1

Block Diagram

Figure 2-1. Block Diagram

MCKO

MDO[5..0]

MSEO[1..0]

EVTI_N

LOCAL BUS

INTERFACE

AVR32UC CPU

EVTO_N

NEXUS

CLASS 2+

OCD

TCK

TDO

MEMORY PROTECTION UNIT

JTAG

32 KB

SRAM

TDI

TMS

INTERFACE

INSTR

INTERFACE

DATA

INTERFACE

DATAOUT

aWire

RESET_N

M

S

128/256 KB

FLASH

HIGH SPEED

BUS MATRIX

S/M

SAU

S

M

CONFIGURATION

REGISTERS BUS

PERIPHERAL

DMA

CONTROLLER

HSB-PB

BRIDGE A

HSB-PB

BRIDGE B

DIS

VDIVEN

CSA[16:0]

CSB[16:0]

SMP

POWER MANAGER

CAPACITIVE TOUCH

MODULE

CLOCK

CONTROLLER

PA

PB

SYNC

SLEEP

CONTROLLER

USART0

USART1

USART2

USART3

RXD

TXD

CLK

RESET

CONTROLLER

RTS, CTS

SCK

GCLK_IN[1..0]

GCLK[4..0]

MISO, MOSI

SPI

NPCS[3..0]

RCSYS

RC32OUT

RC32K

RC120M

OSC32K

OSC0

TWCK

PA

PB

TWI MASTER 0

TWI MASTER 1

TWD

SYSTEM CONTROL

INTERFACE

XIN32

XOUT32

TWALM

XIN0

XOUT0

TWCK

TWI SLAVE 0

TWI SLAVE 1

TWD

DFLL

TWALM

PLL

ADP[1..0]

TRIGGER

INTERRUPT

CONTROLLER

8-CHANNEL ADC

INTERFACE

AD[8..0]

ADVREFP

EXTINT[5..1]

NMI

EXTERNAL INTERRUPT

CONTROLLER

A[2..0]

TIMER/COUNTER 0

TIMER/COUNTER 1

B[2..0]

PWMA[35..0]

PWM CONTROLLER

CLK[2..0]

ASYNCHRONOUS

TIMER

ACBP[3..0]

ACBN[3..0]

ACAP[3..0]

ACAN[3..0]

ACREFN

AC INTERFACE

WATCHDOG

TIMER

FREQUENCY METER

OUT[1:0]

IN[7..0]

GLUE LOGIC

CONTROLLER

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2.2

Configuration Summary

Table 2-1.

Feature

Flash

Configuration Summary

AT32UC3L0256

AT32UC3L0128

256KB

128KB

SRAM

32KB

GPIO

36

5

High-drive pins

External Interrupts

TWI

6

2

USART

4

Peripheral DMA Channels

Peripheral Event System

SPI

12

1

Asynchronous Timers

Timer/Counter Channels

PWM channels

1

6

36

1

Frequency Meter

Watchdog Timer

Power Manager

Secure Access Unit

Glue Logic Controller

1

Digital Frequency Locked Loop 20-150 MHz (DFLL)

Phase Locked Loop 40-240 MHz (PLL)

Crystal Oscillator 0.45-16 MHz (OSC0)

Crystal Oscillator 32 KHz (OSC32K)

RC Oscillator 120MHz (RC120M)

Oscillators

RC Oscillator 115 kHz (RCSYS)

RC Oscillator 32 kHz (RC32K)

ADC

8-channel 12-bit

Temperature Sensor

Analog Comparators

Capacitive Touch Module

JTAG

1

8

1

aWire

1

Max Frequency

Packages

50 MHz

TQFP48/QFN48/TLLGA48

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32145BS–01/2012

AT32UC3L0128/256

3. Package and Pinout

3.1

Package

The device pins are multiplexed with peripheral functions as described in Section 3.2.1.

Figure 3-1. TQFP48/QFN48 Pinout

PA15

PA16

PA17

PA19

PA18

VDDIO

GND

PB11

GND

PA10

PA12

VDDIO

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

PA21

PB10

RESET_N

PB04

PB05

GND

VDDCORE

VDDIN

PB01

PA07

PA01

PA02

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Figure 3-2. TLLGA48 Pinout

24

23

22

21

20

19

18

17

16

15

14

PA21

PB10

RESET_N

PB04

PB05

PA16

PA17

PA19

PA18

VDDIO

GND

PB11

GND

PA10

PA12

VDDIO

38

39

40

41

42

43

44

45

46

47

48

GND

VDDCORE

VDDIN

PB01

PA07

PA01

3.2

Peripheral Multiplexing on I/O Lines

3.2.1

Multiplexed Signals

Each GPIO line can be assigned to one of the peripheral functions. The following table

describes the peripheral signals multiplexed to the GPIO lines.

Table 3-1.

GPIO Controller Function Multiplexing

G

P

I

GPIO Function

48-

O

Supply

Type

A

B

C

D

E

F

G

H

Normal

I/O

U S A R T 0

TXD

U S A R T 1

RTS

S P I

NPCS[2]

P W M A

PWMA[0]

S C I F

GCLK[0]

C AT

CSA[2]

11

PA00

PA01

0

1

VDDIO

Normal

I/O

U S A R T 0

RXD

U S A R T 1

CTS

S P I

NPCS[3]

U S A R T 1

CLK

P W M A

PWMA[1]

ACIFB

ACAP[0]

T W I M S 0

TWALM

C AT

CSA[1]

14

VDDIO

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Table 3-1.

GPIO Controller Function Multiplexing

High-

drive I/O

U S A R T 0

RTS

A D C I F B

TRIGGER

U S A R T 2

TXD

T C 0

A0

P W M A

PWMA[2]

ACIFB

ACBP[0]

U S A R T 0

CLK

C AT

CSA[3]

13

PA02

2

3

4

5

VDDIO

Normal

I/O

U S A R T 0

CTS

S P I

NPCS[1]

U S A R T 2

TXD

T C 0

B0

P W M A

PWMA[3]

ACIFB

ACBN[3]

U S A R T 0

CLK

C AT

CSB[3]

4

PA03

PA04

PA05

Normal

I/O

S P I

MISO

T W I M S 0

TWCK

U S A R T 1

RXD

T C 0

B1

P W M A

PWMA[4]

ACIFB

ACBP[1]

C AT

CSA[7]

28

12

Normal

I/O (TWI)

S P I

MOSI

T W I M S 1

TWCK

U S A R T 1

TXD

T C 0

A1

P W M A

PWMA[5]

ACIFB

ACBN[0]

T W I M S 0

TWD

C AT

CSB[7]

High-

drive I/O,

5V

S P I

SCK

U S A R T 2

TXD

U S A R T 1

CLK

T C 0

B0

P W M A

PWMA[6]

EIC

EXTINT[2]

S C I F

GCLK[1]

C AT

CSB[1]

10

15

PA06

PA07

6

7

VDDIO

tolerant

E I C

NMI

(EXTINT[0])

Normal

I/O (TWI)

S P I

NPCS[0]

U S A R T 2

RXD

T W I M S 1

TWALM

T W I M S 0

TWCK

P W M A

PWMA[7]

ACIFB

ACAN[0]

C AT

CSB[2]

High-

drive I/O

U S A R T 1

TXD

S P I

NPCS[2]

T C 0

A2

A D C I F B

ADP[0]

P W M A

PWMA[8]

C AT

CSA[4]

3

PA08

PA09

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

8

VDDIO

VDDIN

VDDIO

VDDIN

VDDIO

VDDIN

High-

drive I/O

U S A R T 1

RXD

S P I

NPCS[3]

T C 0

B2

A D C I F B

ADP[1]

P W M A

PWMA[9]

SCIF

GCLK[2]

E I C

EXTINT[1]

C AT

CSB[4]

2

9

Normal

I/O

T W I M S 0

TWD

T C 0

A0

P W M A

PWMA[10]

ACIFB

ACAP[1]

S C I F

GCLK[2]

C AT

CSA[5]

46

27

47

26

36

37

38

39

41

40

25

10

11

12

13

14

15

16

17

18

19

20

Normal

I/O

P W M A

PWMA[11]

Normal

I/O

U S A R T 2

CLK

T C 0

CLK1

C AT

SMP

P W M A

PWMA[12]

ACIFB

ACAN[1]

S C I F

GCLK[3]

C AT

CSB[5]

Normal

I/O

G L O C

OUT[0]

G L O C

IN[7]

T C 0

A0

S C I F

GCLK[2]

P W M A

PWMA[13]

CAT

SMP

E I C

EXTINT[2]

C AT

CSA[0]

Normal

I/O

A D C I F B

AD[0]

T C 0

CLK2

U S A R T 2

RTS

C AT

SMP

P W M A

PWMA[14]

S C I F

GCLK[4]

C AT

CSA[6]

Normal

I/O

A D C I F B

AD[1]

T C 0

CLK1

G L O C

IN[6]

P W M A

PWMA[15]

CAT

SYNC

E I C

EXTINT[3]

C AT

CSB[6]

Normal

I/O

A D C I F B

AD[2]

T C 0

CLK0

G L O C

IN[5]

P W M A

PWMA[16]

ACIFB

ACREFN

E I C

EXTINT[4]

C AT

CSA[8]

Normal

I/O (TWI)

T C 0

A1

U S A R T 2

CTS

T W I M S 1

TWD

P W M A

PWMA[17]

CAT

SMP

C AT

DIS

C AT

CSB[8]

Normal

I/O

A D C I F B

AD[4]

T C 0

B1

G L O C

IN[4]

P W M A

PWMA[18]

CAT

SYNC

E I C

EXTINT[5]

C AT

CSB[0]

Normal

I/O

A D C I F B

AD[5]

T C 0

A2

T W I M S 1

TWALM

P W M A

PWMA[19]

SCIF

GCLK_IN[0]

C AT

SYNC

C AT

CSA[10]

Normal

I/O

U S A R T 2

TXD

T C 0

A1

G L O C

IN[3]

P W M A

PWMA[20]

SCIF

RC32OUT

C AT

CSA[12]

Normal

I/O (TWI,

5V

tolerant,

SMBus)

U S A R T 2

RXD

T W I M S 0

TWD

T C 0

B1

A D C I F B

TRIGGER

P W M A

PWMA[21]

P WM A

PWMAOD[21]

S C I F

GCLK[0]

C AT

SMP

24

PA21

21

VDDIN

Normal

I/O

U S A R T 0

CTS

U S A R T 2

CLK

T C 0

B2

C AT

SMP

P W M A

PWMA[22]

ACIFB

ACBN[2]

C AT

CSB[10]

9

6

PA22

PB00

PB01

PB02

22

32

33

34

VDDIO

Normal

I/O

U S A R T 3

TXD

A D C I F B

ADP[0]

S P I

NPCS[0]

T C 0

A1

P W M A

PWMA[23]

ACIFB

ACAP[2]

T C 1

A0

C AT

CSA[9]

High-

drive I/O

U S A R T 3

RXD

A D C I F B

ADP[1]

S P I

SCK

T C 0

B1

P W M A

PWMA[24]

T C 1

A1

C AT

CSB[9]

16

7

Normal

I/O

U S A R T 3

RTS

U S A R T 3

CLK

S P I

MISO

T C 0

A2

P W M A

PWMA[25]

ACIFB

ACAN[2]

S C I F

GCLK[1]

C AT

CSB[11]

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Table 3-1.

GPIO Controller Function Multiplexing

Normal

I/O

U S A R T 3

CTS

U S A R T 3

CLK

S P I

MOSI

T C 0

B2

P W M A

PWMA[26]

ACIFB

ACBP[2]

T C 1

A2

C AT

CSA[11]

8

PB03

35

VDDIO

Normal

I/O (TWI,

5V

tolerant,

SMBus)

T C 1

A0

U S A R T 1

RTS

U S A R T 1

CLK

T W I M S 0

TWALM

P W M A

PWMA[27]

P WM A

PWMAOD[27]

T W I M S 1

TWCK

C AT

CSA[14]

21

PB04

36

VDDIN

Normal

I/O (TWI,

5V

tolerant,

SMBus)

T C 1

B0

U S A R T 1

CTS

U S A R T 1

CLK

T W I M S 0

TWCK

P W M A

PWMA[28]

P WM A

PWMAOD[28]

S C I F

GCLK[3]

C AT

CSB[14]

20

30

PB05

PB06

37

38

VDDIN

VDDIO

E I C

NMI

(EXTINT[0])

Normal

I/O

T C 1

A1

U S A R T 3

TXD

A D C I F B

AD[6]

G L O C

IN[2]

P W M A

PWMA[29]

ACIFB

ACAN[3]

C AT

CSB[13]

Normal

I/O

T C 1

B1

U S A R T 3

RXD

A D C I F B

AD[7]

G L O C

IN[1]

P W M A

PWMA[30]

ACIFB

ACAP[3]

E I C

EXTINT[1]

C AT

CSA[13]

31

32

29

23

44

5

PB07

PB08

PB09

PB10

PB11

PB12

39

40

41

42

43

44

VDDIO

VDDIN

VDDIO

Normal

I/O

T C 1

A2

U S A R T 3

RTS

A D C I F B

AD[8]

G L O C

IN[0]

P W M A

PWMA[31]

CAT

SYNC

E I C

EXTINT[2]

C AT

CSB[12]

Normal

I/O

T C 1

B2

U S A R T 3

CTS

U S A R T 3

CLK

P W M A

PWMA[32]

ACIFB

ACBN[1]

E I C

EXTINT[3]

C AT

CSB[15]

Normal

I/O

T C 1

CLK0

U S A R T 1

TXD

U S A R T 3

CLK

G L O C

OUT[1]

P W M A

PWMA[33]

SCIF

GCLK_IN[1]

E I C

EXTINT[4]

C AT

CSB[16]

Normal

I/O

T C 1

CLK1

U S A R T 1

RXD

A D C I F B

TRIGGER

P W M A

PWMA[34]

CAT

VDIVEN

E I C

EXTINT[5]

C AT

CSA[16]

Normal

I/O

T C 1

CLK2

T W I M S 1

TWALM

C AT

SYNC

P W M A

PWMA[35]

ACIFB

ACBP[3]

S C I F

GCLK[4]

C AT

CSA[15]

See Section 3.3 for a description of the various peripheral signals.

Refer to ”Electrical Characteristics” on page 41 for a description of the electrical properties of the

pin types used.

3.2.2

TWI, 5V Tolerant, and SMBUS Pins

Some normal I/O pins offer TWI, 5V tolerance, and SMBUS features. These features are only

available when either of the TWI functions or the PWMAOD function in the PWMA are selected

for these pins.

Refer to the ”TWI Pin Characteristics(1)” on page 48 for a description of the electrical properties

of the TWI, 5V tolerance, and SMBUS pins.

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3.2.3

Peripheral Functions

Each GPIO line can be assigned to one of several peripheral functions. The following table

describes how the various peripheral functions are selected. The last listed function has priority

in case multiple functions are enabled on the same pin.

Table 3-2.

Function

Peripheral Functions

Description

GPIO Controller Function multiplexing

Nexus OCD AUX port connections

aWire DATAOUT

GPIO and GPIO peripheral selection A to H

OCD trace system

aWire output in two-pin mode

JTAG debug port

JTAG port connections

Oscillators

OSC0, OSC32

3.2.4

JTAG Port Connections

If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O

Controller configuration.

Table 3-3.

JTAG Pinout

48-pin

Pin name

PA00

JTAG pin

TCK

11

14

13

4

PA01

TMS

PA02

TDO

PA03

TDI

3.2.5

Nexus OCD AUX Port Connections

If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-

spectively of the I/O Controller configuration. Two different OCD trace pin mappings are

possible, depending on the configuration of the OCD AXS register. For details, see the AVR32

UC Technical Reference Manual.

Table 3-4.

Nexus OCD AUX Port Connections

AXS=1

PA05

PA10

PA18

PA17

PA16

PA15

PA14

AXS=0

PB08

PB00

PB04

PB05

PB03

PB02

PB09

EVTI_N

MDO[5]

MDO[4]

MDO[3]

MDO[2]

MDO[1]

MDO[0]

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Table 3-4.

Nexus OCD AUX Port Connections

AXS=1

PA04

PA06

PA07

PA11

AXS=0

PA04

EVTO_N

MCKO

PB01

PB11

PB12

MSEO[1]

MSEO[0]

3.2.6

Oscillator Pinout

The oscillators are not mapped to the normal GPIO functions and their muxings are controlled

by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more

information about this.

Table 3-5.

Oscillator Pinout

48-pin

Pin Name

PA08

Oscillator Pin

XIN0

3

46

26

2

PA10

XIN32

PA13

XIN32_2

XOUT0

PA09

47

25

PA12

XOUT32

XOUT32_2

PA20

3.2.7

Other Functions

The functions listed in Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA

pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active

after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is

always enabled. Please refer to Section 6.1.4 on page 40 for constraints on the WAKE_N pin.

Table 3-6.

Other Functions

48-pin

PA11

Function

WAKE_N

27

22

11

RESET_N

PA00

aWire DATA

aWire DATAOUT

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3.3

Signal Descriptions

The following table gives details on signal names classified by peripheral.

Table 3-7.

Signal Descriptions List

Function

Active

Level

Signal Name

Type

Comments

Analog Comparator Interface - ACIFB

ACAN3 - ACAN0

ACAP3 - ACAP0

ACBN3 - ACBN0

ACBP3 - ACBP0

ACREFN

Negative inputs for comparators "A"

Positive inputs for comparators "A"

Negative inputs for comparators "B"

Positive inputs for comparators "B"

Common negative reference

Analog

ADC Interface - ADCIFB

AD8 - AD0

ADP1 - ADP0

TRIGGER

Analog Signal

Analog

Output

Input

Drive Pin for resistive touch screen

External trigger

aWire - AW

DATA

aWire data

I/O

DATAOUT

aWire data output for 2-pin mode

Capacitive Touch Module - CAT

CSA16 - CSA0

CSB16 - CSB0

DIS

Capacitive Sense A

Capacitive Sense B

I/O

Discharge current control

SMP signal

Analog

Output

Input

SMP

SYNC

Synchronize signal

Voltage divider enable

VDIVEN

Output

External Interrupt Controller - EIC

NMI (EXTINT0)

Non-Maskable Interrupt

Input

EXTINT5 - EXTINT1

External interrupt

Input

Glue Logic Controller - GLOC

Input

IN7 - IN0

Inputs to lookup tables

OUT1 - OUT0

Outputs from lookup tables

Output

JTAG module - JTAG

TCK

TDI

Test Clock

Input

Test Data In

TDO

TMS

Test Data Out

Test Mode Select

Output

Input

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Table 3-7.

Signal Descriptions List

Reset

Power Manager - PM

Input

Pulse Width Modulation Controller - PWMA

RESET_N

Low

PWMA35 - PWMA0

PWMA channel waveforms

Output

PWMAOD35 -

PWMAOD0

PWMA channel waveforms, open drain

mode

Not all channels support open

drain mode

System Control Interface - SCIF

GCLK4 - GCLK0

Generic Clock Output

Output

Input

GCLK_IN1 - GCLK_IN0 Generic Clock Input

RC32OUT

XIN0

RC32K output at startup

Output

Analog/

Digital

Crystal 0 Input

Analog/

Digital

XIN32

Crystal 32 Input (primary location)

Crystal 32 Input (secondary location)

Analog/

Digital

XIN32_2

XOUT0

Crystal 0 Output

Analog

XOUT32

XOUT32_2

Crystal 32 Output (primary location)

Crystal 32 Output (secondary location)

Serial Peripheral Interface - SPI

MISO

Master In Slave Out

Master Out Slave In

I/O

MOSI

NPCS3 - NPCS0

SCK

SPI Peripheral Chip Select

Clock

I/O

Low

I/O

Timer/Counter - TC0, TC1

A0

Channel 0 Line A

Channel 1 Line A

Channel 2 Line A

Channel 0 Line B

Channel 1 Line B

Channel 2 Line B

I/O

A1

A2

B0

B1

B2

CLK0

CLK1

CLK2

Channel 0 External Clock Input

Channel 1 External Clock Input

Channel 2 External Clock Input

Input

Two-wire Interface - TWIMS0, TWIMS1

TWALM

TWCK

TWD

SMBus SMBALERT

I/O

Low

Two-wire Serial Clock

Two-wire Serial Data

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Table 3-7.

Signal Descriptions List

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

CLK

CTS

RTS

RXD

TXD

Clock

I/O

Clear To Send

Request To Send

Receive Data

Transmit Data

Input

Low

Output

Input

Output

Note:

1. ADCIFB: AD3 does not exist.

Table 3-8.

Signal Description List, Continued

Active

Level

Signal Name

Function

Type

Comments

Power

Input/Output

VDDCORE

VDDIO

Core Power Supply / Voltage Regulator Output

I/O Power Supply

1.62V to 1.98V

1.62V to 3.6V. VDDIO should

always be equal to or lower than

VDDIN.

Power Input

VDDANA

ADVREFP

VDDIN

Analog Power Supply

Analog Reference Voltage

Voltage Regulator Input

Analog Ground

Power Input

Ground

1.62V to 1.98V

1.62V to 3.6V ⁽¹⁾

GNDANA

GND

Ground

Auxiliary Port - AUX

MCKO

Trace Data Output Clock

Trace Data Output

Trace Frame Control

Event In

Output

Input

MDO5 - MDO0

MSEO1 - MSEO0

EVTI_N

Low

EVTO_N

Event Out

Output

General Purpose I/O pin

PA22 - PA00

PB12 - PB00

Parallel I/O Controller I/O Port 0

Parallel I/O Controller I/O Port 1

I/O

1.

See Section 6.1 on page 36

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3.4

I/O Line Considerations

3.4.1

JTAG Pins

The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI

pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled dur-

ing reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG

pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.

Please refer to Section 3.2.4 on page 11 for the JTAG port connections.

3.4.2

3.4.3

PA00

Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the

application.

RESET_N Pin

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As

the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in

case no reset from the system needs to be applied to the product.

The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-

ging, it must not be driven by external circuitry.

3.4.4

TWI Pins PA21/PB04/PB05

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and

inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have

the same characteristics as other GPIO pins. Selected pins are also SMBus compliant (refer to

Section 3.2.1 on page 8). As required by the SMBus specification, these pins provide no leakage

path to ground when the AT32UC3L0128/256 is powered down. This allows other devices on

the SMBus to continue communicating even though the AT32UC3L0128/256 is not powered.

After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the

GPIO Module Configuration chapter for details.

3.4.5

TWI Pins PA05/PA07/PA17

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and

inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have

the same characteristics as other GPIO pins.

After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the

GPIO Module Configuration chapter for details.

3.4.6

3.4.7

GPIO Pins

All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed

independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as

inputs with pull-up resistors disabled, except PA00 which has the pull-up resistor enabled. PA20

selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset.

High-drive Pins

The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to

Section 7. on page 41 for electrical characteristics.

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3.4.8

RC32OUT Pin

3.4.8.1

Clock output at startup

After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20,

even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by

the system to start other devices or to clock a switching regulator to rise the power supply volt-

age up to an acceptable value.

The clock will be available on PA20, but will be disabled if one of the following conditions are

true:

• PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT)

• PA20 is configured as a General Purpose Input/Output (GPIO)

• The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power

Manager chapter)

The maximum amplitude of the clock signal will be defined by VDDIN.

Once the RC32K output on PA20 is disabled it can never be enabled again.

3.4.8.2

XOUT32_2 function

PA20 selects RC32OUT as default enabled after reset. This function is not automatically dis-

abled when the user enables the XOUT32_2 function on PA20. This disturbs the oscillator and

may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2

is enabled.

3.4.9

ADC Input Pins

These pins are regular I/O pins powered from the VDDIO. However, when these pins are used

for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures

that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins

are not used for ADC inputs, the pins may be driven to the full I/O voltage range.

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4. Processor and Architecture

Rev: 2.1.2.0

This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-

sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical

Reference Manual.

4.1

Features

• 32-bit load/store AVR32A RISC architecture

– 15 general-purpose 32-bit registers

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file

– Fully orthogonal instruction set

– Privileged and unprivileged modes enabling efficient and secure operating systems

– Innovative instruction set together with variable instruction length ensuring industry leading

code density

– DSP extension with saturating arithmetic, and a wide variety of multiply instructions

• 3-stage pipeline allowing one instruction per clock cycle for most instructions

– Byte, halfword, word, and double word memory access

– Multiple interrupt priority levels

• MPU allows for operating systems with memory protection

• Secure State for supporting FlashVault technology

4.2

AVR32 Architecture

AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-

sensitive embedded applications, with particular emphasis on low power consumption and high

code density. In addition, the instruction set architecture has been tuned to allow a variety of

microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance

processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been com-

piled and analyzed to achieve the best code density in its class. In addition to lowering the

memory requirements, a compact code size also contributes to the core’s low power characteris-

tics. The processor supports byte and halfword data types without penalty in code size and

performance.

Memory load and store operations are provided for byte, halfword, word, and double word data

with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely

linked to the architecture and is able to exploit code optimization features, both for size and

speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

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single cycle. Load and store instructions have several different formats in order to reduce code

size and speed up execution.

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the

Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values

from function calls and is used implicitly by some instructions.

4.3

The AVR32UC CPU

The AVR32UC CPU targets low- and medium-performance applications, and provides an

advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU).

Java acceleration hardware is not implemented.

AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,

one High Speed Bus master for data access, and one High Speed Bus slave interface allowing

other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the

CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.

Also, power consumption is reduced by not needing a full High Speed Bus access for memory

accesses. A dedicated data RAM interface is provided for communicating with the internal data

RAMs.

A local bus interface is provided for connecting the CPU to device-specific high-speed systems,

such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a

one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data

between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated

memory range allocated to it, and data transfers are performed using regular load and store

instructions. Details on which devices that are mapped into the local bus space is given in the

CPU Local Bus section in the Memories chapter.

Figure 4-1 on page 20 displays the contents of AVR32UC.

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Figure 4-1. Overview of the AVR32UC CPU

Power/

Reset

control

OCD

system

AVR32UC CPU pipeline

MPU

Data memory controller

Instruction memory controller

High Speed Bus master

High

Speed

CPU Local

Bus

High Speed

Bus master

CPU RAM

Bus slave

master

4.3.1

Pipeline Overview

AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-

tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic

(ALU) section, one multiply (MUL) section, and one load/store (LS) section.

Instructions are issued and complete in order. Certain operations require several clock cycles to

complete, and in this case, the instruction resides in the ID and EX stages for the required num-

ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is

required, and no data dependencies can arise in the pipeline.

Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages.

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Figure 4-2. The AVR32UC Pipeline

MUL

Multiply unit

ALU unit

Regfile

Read

Regfile

write

IF

ID

ALU

LS

Prefetch unit

Decode unit

Load-store

unit

4.3.2

AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-

geted at cost-sensitive, lower-end applications like smaller microcontrollers. This

microarchitecture does not provide dedicated hardware registers for shadowing of register file

registers in interrupt contexts. Additionally, it does not provide hardware registers for the return

address registers and return status registers. Instead, all this information is stored on the system

stack. This saves chip area at the expense of slower interrupt handling.

4.3.2.1

Interrupt Handling

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These

registers are pushed regardless of the priority level of the pending interrupt. The return address

and status register are also automatically pushed to stack. The interrupt handler can therefore

use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are

restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.

Executing the rete or rets instruction at the completion of an exception or system call will pop

this status register and continue execution at the popped return address.

4.3.2.2

4.3.2.3

Java Support

AVR32UC does not provide Java hardware acceleration.

Memory Protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is

attempted to an illegal memory address, the access is aborted and an exception is taken. The

MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

4.3.2.4

Unaligned Reference Handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is

able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an

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address exception. Doubleword-sized accesses with word-aligned pointers will automatically be

performed as two word-sized accesses.

The following table shows the instructions with support for unaligned addresses. All other

instructions require aligned addresses.

Table 4-1.

Instruction

ld.d

Instructions with Unaligned Reference Support

Supported Alignment

Word

st.d

4.3.2.5

Unimplemented Instructions

The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented

Instruction Exception if executed:

• All SIMD instructions

• All coprocessor instructions if no coprocessors are present

• retj, incjosp, popjc, pushjc

• tlbr, tlbs, tlbw

• cache

4.3.2.6

CPU and Architecture Revision

Three major revisions of the AVR32UC CPU currently exist. The device described in this

datasheet uses CPU revision 3.

The Architecture Revision field in the CONFIG0 system register identifies which architecture

revision is implemented in a specific device.

AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled

for revision 1 or 2 is binary-compatible with revision 3 CPUs.

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4.4

Programming Model

4.4.1

Register File Configuration

The AVR32UC register file is shown below.

Figure 4-3. The AVR32UC Register File

Supervisor

INT0

Bit 31

INT1

Bit 31

INT2

Bit 31

INT3

Bit 31

Exception

NMI

Secure

Bit 31

Application

Bit 31

Bit 0

Bit 31

Bit 0

Bit 31

Bit 0

Bit 31

Bit 0

PC

LR

PC

LR

PC

LR

PC

LR

PC

LR

PC

LR

PC

LR

PC

LR

PC

LR

SP_APP

R12

SP_SYS

R12

SP_SYS

R12

SP_SYS

R12

SP_SYS

R12

SP_SYS

R12

SP_SYS

R12

SP_SYS

R12

SP_SEC

R12

R11

R10

R9

R8

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

INTR07PC

INTR16PC

FINRT5PC

SMRP4C

R3

R2

R1

R0

SR

SS_STATUS

SS_ADRF

SS_ADRR

SS_ADR0

SS_ADR1

SS_SP_SYS

SS_SP_APP

SS_RAR

SS_RSR

4.4.2

Status Register Configuration

The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4

and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,

and L bits, while the upper halfword contains information about the mode and state the proces-

sor executes in. Refer to the AVR32 Architecture Manual for details.

Figure 4-4. The Status Register High Halfword

Bit 31

Bit 16

LC

-

SS

-

DM

0

D

0

-

M2

0

M1

0

M0

1

EM

1

I3M IF2EM I1M I0M GM

Bit name

1

0

1

Initial value

Global Interrupt Mask

Interrupt Level 0 Mask

Interrupt Level 1 Mask

Interrupt Level 2 Mask

Interrupt Level 3 Mask

Exception Mask

Mode Bit 0

Mode Bit 1

Mode Bit 2

Reserved

Debug State

Debug State Mask

Reserved

Secure State

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Figure 4-5. The Status Register Low Halfword

Bit 15

Bit 0

-

T

0

-

L

0

Q

0

V

0

N

0

Z

0

C

0

Bit name

0

Initial value

Carry

Zero

Sign

Overflow

Saturation

Lock

Reserved

Scratch

Reserved

4.4.3

Processor States

4.4.3.1

Normal RISC State

The AVR32 processor supports several different execution contexts as shown in Table 4-2.

Table 4-2.

Overview of Execution Modes, their Priorities and Privilege Levels.

Priority

Mode

Security

Description

1

Non Maskable Interrupt

Exception

Privileged

Unprivileged

Non Maskable high priority interrupt mode

Execute exceptions

2

3

Interrupt 3

General purpose interrupt mode

Runs supervisor calls

4

Interrupt 2

5

Interrupt 1

6

Interrupt 0

N/A

Supervisor

Application

Normal program execution mode

Mode changes can be made under software control, or can be caused by external interrupts or

exception processing. A mode can be interrupted by a higher priority mode, but never by one

with lower priority. Nested exceptions can be supported with a minimal software overhead.

When running an operating system on the AVR32, user processes will typically execute in the

application mode. The programs executed in this mode are restricted from executing certain

instructions. Furthermore, most system registers together with the upper halfword of the status

register cannot be accessed. Protected memory areas are also not available. All other operating

modes are privileged and are collectively called System Modes. They have full access to all priv-

ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.

4.4.3.2

Debug State

The AVR32 can be set in a debug state, which allows implementation of software monitor rou-

tines that can read out and alter system information for use during application development. This

implies that all system and application registers, including the status registers and program

counters, are accessible in debug state. The privileged instructions are also available.

All interrupt levels are by default disabled when debug state is entered, but they can individually

be switched on by the monitor routine by clearing the respective mask bit in the status register.

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Debug state can be entered as described in the AVR32UC Technical Reference Manual.

Debug state is exited by the retd instruction.

4.4.3.3

Secure State

The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with

higher security levels. The rest of the code can not access resources reserved for this secure

code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Techni-

cal Reference Manual for details.

4.4.4

System Registers

The system registers are placed outside of the virtual memory space, and are only accessible

using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-

fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is

responsible for maintaining correct sequencing of any instructions following a mtsr instruction.

For detail on the system registers, refer to the AVR32UC Technical Reference Manual.

Table 4-3.

System Registers

Reg #

0

Address

0

Name

Function

SR

Status Register

1

4

EVBA

Exception Vector Base Address

Application Call Base Address

CPU Control Register

Exception Cause Register

Unused in AVR32UC

Return Status Register for Debug mode

Unused in AVR32UC

Return Address Register for Debug mode

Unused in AVR32UC

2

8

ACBA

3

12

16

20

24

28

32

36

40

44

48

52

56

60

64

68

72

76

80

84

88

92

CPUCR

4

ECR

5

RSR_SUP

RSR_INT0

RSR_INT1

RSR_INT2

RSR_INT3

RSR_EX

RSR_NMI

RSR_DBG

RAR_SUP

RAR_INT0

RAR_INT1

RAR_INT2

RAR_INT3

RAR_EX

RAR_NMI

RAR_DBG

JECR

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

JOSP

JAVA_LV0

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Table 4-3.

Reg #

24

System Registers (Continued)

Address

96

Name

Function

JAVA_LV1

JAVA_LV2

JAVA_LV3

JAVA_LV4

JAVA_LV5

JAVA_LV6

JAVA_LV7

JTBA

Unused in AVR32UC

25

100

104

108

112

116

120

124

128

132-252

256

260

264

268

272

276

280

284

288

292

296

300

304

308

312

316

320

324

328

332

336

340

344

348

352

356

Unused in AVR32UC

26

Unused in AVR32UC

27

Unused in AVR32UC

28

Unused in AVR32UC

29

Unused in AVR32UC

30

Unused in AVR32UC

31

Unused in AVR32UC

32

JBCR

Unused in AVR32UC

33-63

64

Reserved

CONFIG0

CONFIG1

COUNT

Reserved for future use

Configuration register 0

Configuration register 1

Cycle Counter register

65

66

67

COMPARE

TLBEHI

Compare register

68

Unused in AVR32UC

69

TLBELO

PTBR

Unused in AVR32UC

70

Unused in AVR32UC

71

TLBEAR

MMUCR

TLBARLO

TLBARHI

PCCNT

Unused in AVR32UC

72

Unused in AVR32UC

73

Unused in AVR32UC

74

Unused in AVR32UC

75

Unused in AVR32UC

76

PCNT0

Unused in AVR32UC

77

PCNT1

Unused in AVR32UC

78

PCCR

Unused in AVR32UC

79

BEAR

Bus Error Address Register

MPU Address Register region 0

MPU Address Register region 1

MPU Address Register region 2

MPU Address Register region 3

MPU Address Register region 4

MPU Address Register region 5

MPU Address Register region 6

MPU Address Register region 7

MPU Privilege Select Register region 0

MPU Privilege Select Register region 1

80

MPUAR0

MPUAR1

MPUAR2

MPUAR3

MPUAR4

MPUAR5

MPUAR6

MPUAR7

MPUPSR0

MPUPSR1

81

82

83

84

85

86

87

88

89

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Table 4-3.

Reg #

90

System Registers (Continued)

Address

360

Name

Function

MPUPSR2

MPUPSR3

MPUPSR4

MPUPSR5

MPUPSR6

MPUPSR7

MPUCRA

MPUCRB

MPUBRA

MPUBRB

MPUAPRA

MPUAPRB

MPUCR

MPU Privilege Select Register region 2

MPU Privilege Select Register region 3

MPU Privilege Select Register region 4

MPU Privilege Select Register region 5

MPU Privilege Select Register region 6

MPU Privilege Select Register region 7

Unused in this version of AVR32UC

MPU Access Permission Register A

MPU Access Permission Register B

MPU Control Register

91

364

92

368

93

372

94

376

95

380

96

384

97

388

98

392

99

396

100

101

102

103

104

105

106

107

108

109

110

111

112-191

192-255

400

404

408

412

SS_STATUS

SS_ADRF

SS_ADRR

SS_ADR0

SS_ADR1

SS_SP_SYS

SS_SP_APP

SS_RAR

Secure State Status Register

416

Secure State Address Flash Register

Secure State Address RAM Register

Secure State Address 0 Register

Secure State Address 1 Register

Secure State Stack Pointer System Register

Secure State Stack Pointer Application Register

Secure State Return Address Register

Secure State Return Status Register

Reserved for future use

420

424

428

432

436

440

444

SS_RSR

448-764

768-1020

Reserved

IMPL

IMPLEMENTATION DEFINED

4.5

Exceptions and Interrupts

In the AVR32 architecture, events are used as a common term for exceptions and interrupts.

AVR32UC incorporates a powerful event handling scheme. The different event sources, like Ille-

gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined

behavior when multiple events are received simultaneously. Additionally, pending events of a

higher priority class may preempt handling of ongoing events of a lower priority class.

When an event occurs, the execution of the instruction stream is halted, and execution is passed

to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are

placed sequentially in the code space starting at the address specified by EVBA, with four bytes

between each handler. This gives ample space for a jump instruction to be placed there, jump-

ing to the event routine itself. A few critical handlers have larger spacing between them, allowing

the entire event routine to be placed directly at the address specified by the EVBA-relative offset

generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR)

addresses. This allows the interrupt controller to directly specify the ISR address as an address

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relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384

bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),

not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up

appropriately. The same mechanisms are used to service all different types of events, including

interrupt requests, yielding a uniform event handling scheme.

An interrupt controller does the priority handling of the interrupts and provides the autovector off-

set to the CPU.

4.5.1

System Stack Issues

Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,

SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event

code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,

since the timing of accesses to this memory section is both fast and deterministic.

The user must also make sure that the system stack is large enough so that any event is able to

push the required registers to stack. If the system stack is full, and an event occurs, the system

will enter an UNDEFINED state.

4.5.2

Exceptions and Interrupt Requests

When an event other than scall or debug request is received by the core, the following actions

are performed atomically:

1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and

GM bits in the Status Register are used to mask different events. Not all events can be

masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and

Bus Error) can not be masked. When an event is accepted, hardware automatically

sets the mask bits corresponding to all sources with equal or lower priority. This inhibits

acceptance of other events of the same or lower priority, except for the critical events

listed above. Software may choose to clear some or all of these bits after saving the

necessary state if other priority schemes are desired. It is the event source’s respons-

ability to ensure that their events are left pending until accepted by the CPU.

2. When a request is accepted, the Status Register and Program Counter of the current

context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-

isters R8-R12 and LR are also automatically stored to stack. Storing the Status

Register ensures that the core is returned to the previous execution mode when the

current event handling is completed. When exceptions occur, both the EM and GM bits

are set, and the application may manually enable nested exceptions if desired by clear-

ing the appropriate bit. Each exception handler has a dedicated handler address, and

this address uniquely identifies the exception source.

3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-

ter file bank is selected. The address of the event handler, as shown in Table 4-4 on

page 31, is loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the Return Status Register

and Return Address Register are popped from the system stack and restored to the Status Reg-

ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,

registers R8-R12 and LR are also popped from the system stack. The restored Status Register

contains information allowing the core to resume operation in the previous execution mode. This

concludes the event handling.

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4.5.3

4.5.4

4.5.5

Supervisor Calls

The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is

designed so that privileged routines can be called from any context. This facilitates sharing of

code between different execution modes. The scall mechanism is designed so that a minimal

execution cycle overhead is experienced when performing supervisor routine calls from time-

critical event handlers.

The scall instruction behaves differently depending on which mode it is called from. The behav-

iour is detailed in the instruction set reference. In order to allow the scall routine to return to the

correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC

CPU, scall and rets uses the system stack to store the return address and the status register.

Debug Requests

The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by

the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the

status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the

Debug Exception handler. By default, Debug mode executes in the exception context, but with

dedicated Return Address Register and Return Status Register. These dedicated registers

remove the need for storing this data to the system stack, thereby improving debuggability. The

Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers

in all contexts, while retaining full privileges.

Debug mode is exited by executing the retd instruction. This returns to the previous context.

Entry Points for Events

Several different event handler entry points exist. In AVR32UC, the reset address is

0x80000000. This places the reset address in the boot flash memory area.

TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-

dler can be placed. This speeds up execution by removing the need for a jump instruction placed

at the program address jumped to by the event hardware. All other exceptions have a dedicated

event routine entry point located relative to EVBA. The handler routine address identifies the

exception source directly.

AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.

ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of

the entries in the MPU. TLB multiple hit exception indicates that an access address did map to

multiple TLB entries, signalling an error.

All interrupt requests have entry points located at an offset relative to EVBA. This autovector off-

set is specified by an interrupt controller. The programmer must make sure that none of the

autovector offsets interfere with the placement of other code. The autovector offset has 14

address bits, giving an offset of maximum 16384 bytes.

Special considerations should be made when loading EVBA with a pointer. Due to security con-

siderations, the event handlers should be located in non-writeable flash memory, or optionally in

a privileged memory protection region if an MPU is present.

If several events occur on the same instruction, they are handled in a prioritized way. The priority

ordering is presented in Table 4-4 on page 31. If events occur on several instructions at different

locations in the pipeline, the events on the oldest instruction are always handled before any

events on any younger instruction, even if the younger instruction has events of higher priority

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than the oldest instruction. An instruction B is younger than an instruction A if it was sent down

the pipeline later than A.

The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of

the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-

point unit.

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Table 4-4.

Priority and Handler Addresses for Events

Priority

1

Handler Address

0x80000000

Provided by OCD system

EVBA+0x00

EVBA+0x04

EVBA+0x08

EVBA+0x0C

EVBA+0x10

Autovectored

EVBA+0x14

EVBA+0x50

EVBA+0x18

EVBA+0x1C

EVBA+0x20

EVBA+0x24

EVBA+0x28

EVBA+0x2C

EVBA+0x30

EVBA+0x100

EVBA+0x34

EVBA+0x38

EVBA+0x60

EVBA+0x70

EVBA+0x3C

EVBA+0x40

EVBA+0x44

Name

Event source

External input

OCD system

Internal

Stored Return Address

Reset

Undefined

2

OCD Stop CPU

Unrecoverable exception

TLB multiple hit

First non-completed instruction

PC of offending instruction

First non-completed instruction

PC of offending instruction

First non-completed instruction

PC of offending instruction

3

4

MPU

5

Bus error data fetch

Bus error instruction fetch

NMI

Data bus

External input

CPU

6

7

8

Interrupt 3 request

Interrupt 2 request

Interrupt 1 request

Interrupt 0 request

Instruction Address

ITLB Miss

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

MPU

ITLB Protection

MPU

Breakpoint

OCD system

Instruction

UNUSED

Instruction

CPU

Illegal Opcode

Unimplemented instruction

Privilege violation

Floating-point

Coprocessor absent

Supervisor call

PC of offending instruction

PC(Supervisor Call) +2

Data Address (Read)

Data Address (Write)

DTLB Miss (Read)

DTLB Miss (Write)

DTLB Protection (Read)

DTLB Protection (Write)

DTLB Modified

PC of offending instruction

CPU

MPU

UNUSED

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5. Memories

5.1

Embedded Memories

• Internal high-speed flash

– 256Kbytes (AT32UC3L0256)

– 128Kbytes (AT32UC3L0128)

• 0 wait state access at up to 25MHz in worst case conditions

• 1 wait state access at up to 50MHz in worst case conditions

• Pipelined flash architecture, allowing burst reads from sequential flash locations, hiding

penalty of 1 wait state access

• Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation

to only 8% compared to 0 wait state operation

• 100 000 write cycles, 15-year data retention capability

• Sector lock capabilities, bootloader protection, security bit

• 32 fuses, erased during chip erase

• User page for data to be preserved during chip erase

• Internal high-speed SRAM, single-cycle access at full speed

– 32Kbytes

5.2

Physical Memory Map

The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they

are never remapped in any way, not even during boot. Note that AVR32 UC CPU uses unseg-

mented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address

space is mapped as follows:

Table 5-1.

AT32UC3L0128/256 Physical Memory Map

Size

Device

Start Address

AT32UC3L0256

32Kbytes

256Kbytes

256 bytes

64Kbytes

AT32UC3L0128

32Kbytes

128Kbytes

256 bytes

64Kbytes

Embedded SRAM

Embedded Flash

SAU Channels

0x00000000

0x80000000

0x90000000

0xFFFE0000

0xFFFF0000

HSB-PB Bridge B

HSB-PB Bridge A

Table 5-2.

Flash Memory Parameters

Number of pages

Page size

Part Number

Flash Size (FLASH_PW)

(FLASH_P)

(FLASH_W)

AT32UC3L0256

AT32UC3L0128

256Kbytes

128Kbytes

512

512bytes

256

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5.3

Peripheral Address Map

Table 5-3.

Peripheral Address Mapping

Address

Peripheral Name

0xFFFE0000

FLASHCDW

Flash Controller - FLASHCDW

0xFFFE0400

0xFFFE0800

0xFFFF0000

0xFFFF1000

0xFFFF1400

0xFFFF1800

0xFFFF1C00

0xFFFF2000

0xFFFF2400

0xFFFF2800

0xFFFF2C00

0xFFFF3000

0xFFFF3400

0xFFFF3800

0xFFFF3C00

0xFFFF4000

0xFFFF4400

HMATRIX

SAU

HSB Matrix - HMATRIX

Secure Access Unit - SAU

PDCA

INTC

Peripheral DMA Controller - PDCA

Interrupt controller - INTC

PM

Power Manager - PM

SCIF

System Control Interface - SCIF

Asynchronous Timer - AST

AST

WDT

Watchdog Timer - WDT

EIC

External Interrupt Controller - EIC

Frequency Meter - FREQM

FREQM

GPIO

General-Purpose Input/Output Controller - GPIO

Universal Synchronous Asynchronous Receiver

Transmitter - USART0

USART0

USART1

USART2

USART3

SPI

Universal Synchronous Asynchronous Receiver

Transmitter - USART1

Universal Synchronous Asynchronous Receiver

Transmitter - USART2

Universal Synchronous Asynchronous Receiver

Transmitter - USART3

Serial Peripheral Interface - SPI

TWIM0

Two-wire Master Interface - TWIM0

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Table 5-3.

Peripheral Address Mapping

0xFFFF4800

TWIM1

Two-wire Master Interface - TWIM1

0xFFFF4C00

0xFFFF5000

0xFFFF5400

0xFFFF5800

0xFFFF5C00

0xFFFF6000

0xFFFF6400

0xFFFF6800

0xFFFF6C00

0xFFFF7000

TWIS0

TWIS1

PWMA

TC0

Two-wire Slave Interface - TWIS0

Two-wire Slave Interface - TWIS1

Pulse Width Modulation Controller - PWMA

Timer/Counter - TC0

TC1

Timer/Counter - TC1

ADCIFB

ACIFB

CAT

ADC Interface - ADCIFB

Analog Comparator Interface - ACIFB

Capacitive Touch Module - CAT

Glue Logic Controller - GLOC

aWire - AW

GLOC

AW

5.4

CPU Local Bus Mapping

Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to

being mapped on the Peripheral Bus. These registers can therefore be reached both by

accesses on the Peripheral Bus, and by accesses on the local bus.

Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since

the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at

CPU speed, one write or read operation can be performed per clock cycle to the local bus-

mapped GPIO registers.

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The following GPIO registers are mapped on the local bus:

Table 5-4.

Local Bus Mapped GPIO Registers

Local Bus

Port

Register

Mode

WRITE

SET

Address

Access

0

Output Driver Enable Register (ODER)

Output Value Register (OVR)

0x40000040

0x40000044

0x40000048

0x4000004C

0x40000050

0x40000054

0x40000058

0x4000005C

0x40000060

0x40000140

0x40000144

0x40000148

0x4000014C

0x40000150

0x40000154

0x40000158

0x4000015C

0x40000160

Write-only

Read-only

Write-only

Read-only

CLEAR

TOGGLE

WRITE

SET

CLEAR

TOGGLE

-

Pin Value Register (PVR)

1

Output Driver Enable Register (ODER)

WRITE

SET

CLEAR

TOGGLE

WRITE

SET

Output Value Register (OVR)

Pin Value Register (PVR)

CLEAR

TOGGLE

-

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6. Supply and Startup Considerations

6.1

Supply Considerations

6.1.1

Power Supplies

The AT32UC3L0128/256 has several types of power supply pins:

•VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal.

•VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal.

•VDDANA: Powers the ADC. Voltage is 1.8V nominal.

•VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.

The ground pins GND are common to VDDCORE, VDDIO, and VDDIN. The ground pin for

VDDANA is GNDANA.

When VDDCORE is not connected to VDDIN, the VDDIN voltage must be higher than 1.98V.

Refer to Section 7. on page 41 for power consumption on the various supply pins.

For decoupling recommendations for the different power supplies, please refer to the schematic

checklist.

Refer to Section 3.2 on page 8 for power supply connections for I/O pins.

6.1.2

Voltage Regulator

The AT32UC3L0128/256 embeds a voltage regulator that converts from 3.3V nominal to 1.8V

with a load of up to 60mA. The regulator supplies the output voltage on VDDCORE. The regula-

tor may only be used to drive internal circuitry in the device. VDDCORE should be externally

connected to the 1.8V domains. See Section 6.1.3 for regulator connection figures.

Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid

oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE

and GND as close to the device as possible. Please refer to Section 7.8.1 on page 55 for decou-

pling capacitors values and regulator characteristics.

Figure 6-1. Supply Decoupling

3.3V

VDDIN

C

IN1

IN3

IN2

1.8V

Regulator

1.8V

VDDCORE

C

OUT2

OUT1

The voltage regulator can be turned off in the shutdown mode to power down the core logic and

keep a small part of the system powered in order to reduce power consumption. To enter this

mode the 3.3V supply mode, with 1.8V regulated I/O lines power supply configuration must be

used.

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6.1.3

Regulator Connection

The AT32UC3L0128/256 supports three power supply configurations:

• 3.3V single supply mode

– Shutdown mode is not available

• 1.8V single supply mode

– Shutdown mode is not available

• 3.3V supply mode, with 1.8V regulated I/O lines

– Shutdown mode is available

6.1.3.1

3.3V Single Supply Mode

In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin)

and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V

single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO).

Figure 6-2. 3.3V Single Supply Mode

+

1.98-3.6V

-

VDDIN

VDDIO

GND

I/O Pins

OSC32K_2,

AST, Wake,

Regulator

control

OSC32K,

RC32K,

POR33,

SM33

VDDCORE

VDDANA

Linear

regulator

CPU,

Peripherals,

Memories,

SCIF, BOD,

RCSYS,

ADC

DFLL, PLL

GNDANA

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6.1.3.2

1.8 V Single Supply Mode

In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are

powered by a single 1.8 V supply as shown in Figure 6-3. All I/O lines will be powered by the

same power (VDDIN = VDDIO = VDDCORE).

Figure 6-3. 1.8V Single Supply Mode.

+

1.62-1.98V

-

VDDIN

VDDIO

GND

I/O Pins

OSC32K_2,

AST, Wake,

Regulator

control

OSC32K,

RC32K,

POR33,

SM33

VDDCORE

VDDANA

CPU,

Peripherals,

Memories,

SCIF, BOD,

RCSYS,

ADC

DFLL, PLL

GNDANA

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6.1.3.3

3.3V Supply Mode with 1.8V Regulated I/O Lines

In this mode, the internal regulator is connected to the 3.3V source and its output is connected

to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to

use Shutdown mode.

Figure 6-4. 3.3V Supply Mode with 1.8V Regulated I/O Lines

+

1.98-3.6V

-

VDDIO

GND

VDDIN

I/O Pins

OSC32K_2,

AST, Wake,

Regulator

control

OSC32K,

RC32K,

POR33,

SM33

VDDCORE

Linear

regulator

CPU,

Peripherals,

Memories,

SCIF, BOD,

RCSYS,

ADC

VDDANA

DFLL, PLL

GNDANA

In this mode, some I/O lines are powered by VDDIN while other I/O lines are powered by VDDIO.

Refer to Section 3.2.1 on page 8 for description of power supply for each I/O line.

Refer to the Power Manager chapter for a description of what parts of the system are powered in

Shutdown mode.

Important note: As the regulator has a maximum output current of 60mA, this mode can only be

used in applications where the maximum I/O current is known and compatible with the core and

peripheral power consumption. Typically, great care must be used to ensure that only a few I/O

lines are toggling at the same time and drive very small loads.

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6.1.4

Power-up Sequence

6.1.4.1

Maximum Rise Rate

To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values

described in Table 7-3 on page 42.

Recommended order for power supplies is also described in this chapter.

6.1.4.2

Minimum Rise Rate

The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply

requires a minimum rise rate for the VDDIN power supply.

See Table 7-3 on page 42 for the minimum rise rate value.

If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-

ply is met, one of the following configurations can be used:

• A logic “0” value is applied during power-up on pin PA11 (WAKE_N) until VDDIN rises above

1.2V.

• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.

6.2

Startup Considerations

This chapter summarizes the boot sequence of the AT32UC3L0128/256. The behavior after

power-up is controlled by the Power Manager. For specific details, refer to the Power Manager

chapter.

6.2.1

Starting of Clocks

After power-up, the device will be held in a reset state by the Power-on Reset (POR18 and

POR33) circuitry for a short time to allow the power to stabilize throughout the device. After

reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to

Table 7-17 on page 54 for the frequency for this oscillator.

On system start-up, all high-speed clocks are disabled. All clocks to all modules are running. No

clocks have a divided frequency; all parts of the system receive a clock with the same frequency

as the System RC Oscillator.

When powering up the device, there may be a delay before the voltage has stabilized, depend-

ing on the rise time of the supply used. The CPU can start executing code as soon as the supply

is above the POR18 and POR33 thresholds, and before the supply is stable. Before switching to

a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above

the minimum level (1.62V).

6.2.2

Fetching of Initial Instructions

After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset

address, which is 0x80000000. This address points to the first address in the internal Flash.

The code read from the internal flash is free to configure the clock system and clock sources.

Please refer to the PM and SCIF chapters for more details.

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7. Electrical Characteristics

7.1

Absolute Maximum Ratings*

Table 7-1.

Absolute Maximum Ratings

*NOTICE:

Stresses beyond those listed under

“Absolute Maximum Ratings” may cause

permanent damage to the device. This is

a stress rating only and functional opera-

tion of the device at these or other condi-

tions beyond those indicated in the

operational sections of this specification is

not implied. Exposure to absolute maxi-

mum rating conditions for extended peri-

ods may affect device reliability.

Operating temperature..................................... -40°C to +85°C

Storage temperature...................................... -60°C to +150°C

Voltage on input pins (except for 5V pins) with respect to ground

.................................................................-0.3V to V_VDD⁽²⁾+0.3V

Voltage on 5V tolerant⁽¹⁾pins with respect to ground ...............

.............................................................................-0.3V to 5.5V

Total DC output current on all I/O pins - VDDIO ........... 120mA

Total DC output current on all I/O pins - VDDIN ............. 36mA

Maximum operating voltage VDDCORE......................... 1.98V

Maximum operating voltage VDDIO, VDDIN .................... 3.6V

Notes: 1. 5V tolerant pins, see Section 3.2 ”Peripheral Multiplexing on I/O Lines” on page 8

2. V_VDDcorresponds to either V_VDDINor V_VDDIO, depending on the supply for the pin. Refer to Section 3.2 on page 8 for details.

7.2

Supply Characteristics

The following characteristics are applicable to the operating temperature range: T_A=-40°C to

85°C, unless otherwise specified and are valid for a junction temperature up to T_J=100°C.

Please refer to Section 6. ”Supply and Startup Considerations” on page 36

Table 7-2.

Supply Characteristics

Voltage

Max

Symbol

Parameter

Min

Unit

V_VDDIO

DC supply peripheral I/Os

1.62

3.6

V

DC supply peripheral I/Os, 1.8V

single supply mode

1.62

1.98

3.6

V

V_VDDIN

DC supply peripheral I/Os and

internal regulator, 3.3V supply

mode

V_VDDCORE

V_VDDANA

DC supply core

1.62

1.98

V

Analog supply voltage

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Table 7-3.

Supply Rise Rates and Order⁽¹⁾

Rise Rate

Symbol

Parameter

Min

Max

Unit

Comment

V_VDDIO

DC supply peripheral I/Os

0

2.5

V/µs

Slower rise time requires

external power-on reset

circuit.

DC supply peripheral I/Os

and internal regulator

V_VDDIN

0.002

2.5

V/µs

Rise before or at the same

time as VDDIO

V_VDDCORE

V_VDDANA

Note:

DC supply core

0

2.5

V/µs

Rise together with

VDDCORE

Analog supply voltage

1. These values are based on simulation and characterization of other AVR microcontrollers

manufactured in the same process technology. These values are not covered by test limits in

production.

7.3

Maximum Clock Frequencies

These parameters are given in the following conditions:

• V_VDDCORE= 1.62V to 1.98V

• Temperature = -40°C to 85°C

Table 7-4.

Symbol Parameter

f_CPUCPU clock frequency

f_PBA

Clock Frequencies

Description

Min Max Units

50

PBA clock frequency

PBB clock frequency

f_PBB

f_GCLK0

GCLK0 clock frequency DFLLIF main reference, GCLK0 pin

DFLLIF dithering and SSG reference,

f_GCLK1

GCLK1 clock frequency

GCLK1 pin

50

20

f_GCLK2

f_GCLK3

f_GCLK4

f_GCLK5

f_GCLK6

f_GCLK7

f_GCLK8

f_GCLK9

GCLK2 clock frequency AST, GCLK2 pin

GCLK3 clock frequency PWMA, GCLK3 pin

GCLK4 clock frequency CAT, ACIFB, GCLK4 pin

GCLK5 clock frequency GLOC

MHz

140

50

80

GCLK6 clock frequency

50

GCLK7 clock frequency

50

GCLK8 clock frequency PLL source clock

GCLK9 clock frequency FREQM, GCLK0-8

50

150

7.4

Power Consumption

The values in Table 7-5 are measured values of power consumption under the following condi-

tions, except where noted:

• Operating conditions, internal core supply (Figure 7-1) - this is the default configuration

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– V_VDDIN= 3.0V

– V_VDDCORE= 1.62V, supplied by the internal regulator

– Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to

the Supply and Startup Considerations section for more details

• Equivalent to the 3.3V single supply mode

• Consumption in 1.8V single supply mode can be estimated by subtracting the regula-

tor static current

• Operating conditions, external core supply (Figure 7-2) - used only when noted

– V_VDDIN= V_VDDCORE= 1.8V

– Corresponds to the 1.8V single supply mode, please refer to the Supply and Startup

Considerations section for more details

• T^A= 25°C

• Oscillators

– OSC0 (crystal oscillator) stopped

– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal

– DFLL running at 50MHz with OSC32K as reference

• Clocks

– DFLL used as main clock source

– CPU, HSB, and PBB clocks undivided

– PBA clock divided by 4

– The following peripheral clocks running

• PM, SCIF, AST, FLASHCDW, PBA bridge

– All other peripheral clocks stopped

• I/Os are inactive with internal pull-up

• Flash enabled in high speed mode

• POR18 enabled

• POR33 disabled

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Table 7-5.

Mode

Power Consumption for Different Operating Modes

Conditions

Measured on

Consumption Typ

Unit

CPU running a recursive Fibonacci algorithm

CPU running a division algorithm

300

174

96

Active⁽¹⁾

Idle⁽¹⁾

µA/MHz

Frozen⁽¹⁾

Standby⁽¹⁾

Stop

57

46

38

DeepStop

25

-OSC32K and AST stopped

-Internal core supply

14

7.3

6.7

Amp0

µA

nA

-OSC32K running

Static

-AST running at 1KHz

-External core supply (Figure 7-2)

-OSC32K and AST stopped

-External core supply (Figure 7-2)

-OSC32K running

800

220

-AST running at 1KHz

Shutdown

AST and OSC32K stopped

Note:

1. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies.

Figure 7-1. Measurement Schematic, Internal Core Supply

VDDIN

Amp0

VDDIO

VDDCORE

VDDANA

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Figure 7-2. Measurement Schematic, External Core Supply

VDDIN

VDDIO

Amp0

VDDCORE

VDDANA

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7.5

I/O Pin Characteristics

Table 7-6.

Symbol

Normal I/O Pin Characteristics⁽¹⁾

Parameter

Condition

Min

75

Typ

Max

145

Units

R_PULLUP

Pull-up resistance

100

kOhm

V

_VDD= 3.0V

V_VDD= 1.62V

_VDD= 3.6V

V_VDD= 1.98V

_VDD= 3.0V, I_OL= 3mA

V_VDD= 1.62V, I_OL= 2mA

_VDD= 3.0V, I_OH= 3mA

-0.3

0.3*V_VDD

V_VDD+ 0.3

0.4

V_IL

Input low-level voltage

Input high-level voltage

Output low-level voltage

Output high-level voltage

Output frequency⁽²⁾

Rise time⁽²⁾

V

-0.3

V

0.7*V_VDD

V_IH

V

V_OL

V_OH

f_MAX

t_RISE

V

0.4

V

V_VDD- 0.4

V

V_VDD= 1.62V, I_OH= 2mA

V_VDD= 3.0V, load = 10pF

V_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

45

23

MHz

4.7

11.5

4.8

12

V

_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

_VDD= 3.0V, load = 30pF

ns

t_FALL

I_LEAK

Fall time⁽²⁾

V

Input leakage current

Pull-up resistors disabled

TQFP48 package

QFN48 package

1

µA

1.4

1.1

2.7

2.4

3.8

3.5

Input capacitance, all

normal I/O pins except

PA05, PA07, PA17, PA20,

PA21, PB04, PB05

C_IN

TLLGA48 package

TQFP48 package

QFN48 package

Input capacitance, PA20

pF

TLLGA48 package

TQFP48 package

QFN48 package

Input capacitance, PA05,

PA07, PA17, PA21, PB04,

PB05

TLLGA48 package

Notes: 1. V_VDDcorresponds to either V_VDDINor V_VDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for

details.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-7.

Symbol

High-drive I/O Pin Characteristics⁽¹⁾

Parameter

Condition

Min

30

Typ

50

Max

110

145

45

Units

PA06

R_PULLUP

Pull-up resistance

PA02, PB01, RESET

PA08, PA09

75

100

20

kOhm

10

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Table 7-7.

Symbol

High-drive I/O Pin Characteristics⁽¹⁾

Parameter

Condition

_VDD= 3.0V

V_VDD= 1.62V

_VDD= 3.6V

V_VDD= 1.98V

_VDD= 3.0V, I_OL= 6mA

V_VDD= 1.62V, I_OL= 4mA

_VDD= 3.0V, I_OH= 6mA

Min

-0.3

Typ

Max

0.3*V_VDD

V_VDD+ 0.3

0.4

Units

V

V_IL

Input low-level voltage

V

-0.3

V

0.7*V_VDD

V_IH

Input high-level voltage

Output low-level voltage

Output high-level voltage

V

V_OL

V_OH

f_MAX

t_RISE

t_FALL

f_MAX

t_RISE

0.4

V

V_VDD-0.4

V

V_VDD= 1.62V, I_OH= 4mA

V_VDD= 3.0V, load = 10pF

V_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

45

23

Output frequency, all High-drive I/O

pins, except PA08 and PA09⁽²⁾

MHz

4.7

11.5

4.8

12

Rise time, all High-drive I/O pins,

except PA08 and PA09⁽²⁾

V

_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

_VDD= 3.0V, load = 30pF

ns

Fall time, all High-drive I/O pins,

except PA08 and PA09⁽²⁾

V

V_VDD= 3.0V, load = 10pF

V_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

54

Output frequency, PA08 and

PA09⁽²⁾

MHz

40

2.8

4.9

2.4

4.6

1

Rise time, PA08 and PA09⁽²⁾

V

_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

_VDD= 3.0V, load = 30pF

ns

t_FALL

I_LEAK

Fall time, PA08 and PA09⁽²⁾

Input leakage current

V

Pull-up resistors disabled

TQFP48 package

QFN48 package

µA

2.2

2.0

7.0

6.7

Input capacitance, all High-drive I/O

pins, except PA08 and PA09

C_IN

TLLGA48 package

TQFP48 package

QFN48 package

pF

C_IN

Input capacitance, PA08 and PA09

TLLGA48 package

Notes: 1. V_VDDcorresponds to either V_VDDINor V_VDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for

details.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-8.

Symbol

High-drive I/O, 5V Tolerant, Pin Characteristics⁽¹⁾

Parameter

Condition

Min

30

Typ

Max

110

Units

R_PULLUP

Pull-up resistance

50

kOhm

V

_VDD= 3.0V

-0.3

0.3*V_VDD

V_IL

Input low-level voltage

V

V_VDD= 1.62V

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Table 7-8.

Symbol

High-drive I/O, 5V Tolerant, Pin Characteristics⁽¹⁾

Parameter

Condition

_VDD= 3.6V

V_VDD= 1.98V

_VDD= 3.0V, I_OL= 6mA

V_VDD= 1.62V, I_OL= 4mA

_VDD= 3.0V, I_OH= 6mA

Min

Typ

Max

5.5

0.4

Units

V

0.7*V_VDD

V_IH

Input high-level voltage

V

V_OL

V_OH

f_MAX

t_RISE

Output low-level voltage

Output high-level voltage

Output frequency⁽²⁾

Rise time⁽²⁾

V

V_VDD-0.4

V_VDD= 1.62V, I_OH= 4mA

V_VDD= 3.0V, load = 10pF

V_VDD= 3.0V, load = 30pF

V_VDD= 3.0V, load = 10pF

87

58

MHz

2.3

4.3

1.9

3.7

10

V_VDD= 3.0V, load = 30pF

ns

V_VDD= 3.0V, load = 10pF

V_VDD= 3.0V, load = 30pF

5.5V, pull-up resistors disabled

TQFP48 package

t_FALL

I_LEAK

Fall time⁽²⁾

Input leakage current

µA

pF

4.5

4.2

C_IN

Input capacitance

QFN48 package

TLLGA48 package

Notes: 1. V_VDDcorresponds to either V_VDDINor V_VDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for

details.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-9.

Symbol

TWI Pin Characteristics⁽¹⁾

Parameter

Condition

Min

25

Typ

Max

Units

R_PULLUP

Pull-up resistance

35

60

kOhm

V

_VDD= 3.0V

V_VDD= 1.62V

_VDD= 3.6V

-0.3

0.3*V_VDD

V_IL

Input low-level voltage

Input high-level voltage

V

-0.3

0.3*V_VDD

V

0.7*V_VDD

V_VDD+ 0.3

V_VDD= 1.98V

V_VDD+ 0.3

V_IH

V_VDD= 3.6V

5.5

0.4

1

Input high-level voltage, 5V tolerant

SMBUS compliant pins

V

V_VDD= 1.98V

V_OL

I_LEAK

I_IL

Output low-level voltage

Input leakage current

Input low leakage

I_OL= 3mA

Pull-up resistors disabled

1

µA

pF

I_IH

Input high leakage

1

TQFP48 package

QFN48 package

TLLGA48 package

3.8

3.5

C_IN

Input capacitance

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Table 7-9.

Symbol

TWI Pin Characteristics⁽¹⁾

Parameter

Condition

Min

Typ

250

470

Max

Units

ns

Cbus = 400pF, V_VDD> 2.0V

Cbus = 400pF, V_VDD> 1.62V

Cbus = 400pF, V_VDD> 2.0V

t_FALL

Fall time

f_MAX

Max frequency

400

kHz

Note:

1. V_VDDcorresponds to either V_VDDINor V_VDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for

details.

7.6

Oscillator Characteristics

Oscillator 0 (OSC0) Characteristics

Digital Clock Characteristics

7.6.1

7.6.1.1

The following table describes the characteristics for the oscillator when a digital clock is applied

on XIN.

Table 7-10. Digital Clock Characteristics

Symbol

f_CPXIN

Parameter

Conditions

Min

Typ

Max

50

60

Units

MHz

XIN clock frequency

XIN clock duty cycle⁽¹⁾

Startup time

t_CPXIN

40

%

t_STARTUP

0

cycles

TQFP48 package

QFN48 package

TLLGA48 package

7.0

6.7

C_IN

XIN input capacitance

pF

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.6.1.2

Crystal Oscillator Characteristics

The following table describes the characteristics for the oscillator when a crystal is connected

between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator

where the crystal load capacitance C_Lis within the range given in the table. The exact value of C_L

can be found in the crystal datasheet. The capacitance of the external capacitors (C_LEXT) can

then be computed as follows:

C_LEXT= 2(C_L– C_i) – C_PCB

where C_PCBis the capacitance of the PCB and C_iis the internal equivalent load capacitance.

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Table 7-11. Crystal Oscillator Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

0.45

6

Typ

Max

16

Unit

Crystal oscillator frequency⁽³⁾

Crystal load capacitance⁽³⁾

Internal equivalent load capacitance

Startup time

10

MHz

C_L

18

pF

C_i

2

t_STARTUP

SCIF.OSCCTRL.GAIN = 2⁽¹⁾

30 000⁽²⁾

cycles

Active mode, f = 0.45MHz,

SCIF.OSCCTRL.GAIN = 0

30

I_OSC

Current consumption

µA

Active mode, f = 10MHz,

SCIF.OSCCTRL.GAIN = 2

220

Notes: 1. Please refer to the SCIF chapter for details.

2. Nominal crystal cycles.

3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Figure 7-3. Oscillator Connection

C_LEXT

XOUT

UC3L

C_i

C_L

XIN

C_LEXT

7.6.2

32KHz Crystal Oscillator (OSC32K) Characteristics

Figure 7-3 and the equation above also applies to the 32KHz oscillator connection. The user

must choose a crystal oscillator where the crystal load capacitance C_Lis within the range given

in the table. The exact value of C_Lcan then be found in the crystal datasheet.

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Table 7-12. 32 KHz Crystal Oscillator Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

Typ

Max

Unit

Hz

Crystal oscillator frequency

32 768

30 000⁽¹⁾

t_STARTUP

C_L

Startup time

R_S= 60kOhm, C_L= 9pF

cycles

Crystal load capacitance⁽²⁾

6

12.5

pF

Internal equivalent load

capacitance

C_i

2

I_OSC32

R_S

Current consumption

0.6

µA

Equivalent series resistance⁽²⁾

32 768Hz

35

85

kOhm

Notes: 1. Nominal crystal cycles.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.6.3

Phase Locked Loop (PLL) Characteristics

Table 7-13. Phase Locked Loop Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

40

4

Typ

Max

240

16

Unit

MHz

Output frequency⁽¹⁾

Input frequency⁽¹⁾

Current consumption

f_IN

I_PLL

8

µA/MHz

Startup time, from enabling

the PLL until the PLL is

locked

f_IN= 4MHz

200

t_STARTUP

µs

f_IN= 16MHz

155

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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7.6.4

Digital Frequency Locked Loop (DFLL) Characteristics

Table 7-14. Digital Frequency Locked Loop Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

20

8

Typ

Max

150

Unit

MHz

kHz

%

Output frequency⁽²⁾

Reference frequency⁽²⁾

FINE resolution step

f_REF

FINE > 100, all COARSE values ⁽³⁾

Open loop mode

0.38

Frequency drift over voltage

and temperature

See

Figure 7-4

FINE lock, f_REF= 32kHz, SSG disabled

0.1

0.5

ACCURATE lock, f_REF= 32kHz, dither clk

RCSYS/2, SSG disabled

0.06

Accuracy⁽²⁾

%

FINE lock, f_REF= 8-150kHz, SSG

disabled

0.2

1

ACCURATE lock, f_REF= 8-150kHz,

dither clk RCSYS/2, SSG disabled

0.1

25

I_DFLL

Power consumption

Startup time⁽²⁾

µA/MHz

µs

t_STARTUP

Within 90% of final values

100

f_REF= 32kHz, FINE lock, SSG disabled

8

t_LOCK

Lock time

ms

f

_REF= 32kHz, ACCURATE lock, dithering

28

clock = RCSYS/2, SSG disabled

Notes: 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively.

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Figure 7-4. DFLL Open Loop Frequency Variation⁽¹⁾⁽²⁾

DFLL Open Loop Frequency variation

160

150

140

130

120

1,98V

1,8V

1.62V

110

100

90

80

-40

-20

0

20

40

60

80

Temperature

Notes: 1. The plot shows a typical open loop mode behavior with COARSE= 99 and FINE= 255

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.6.5

120MHz RC Oscillator (RC120M) Characteristics

Table 7-15. Internal 120MHz RC Oscillator Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

Typ

120

1.2

3

Max

Unit

MHz

mA

Output frequency⁽¹⁾

Current consumption

Startup time⁽¹⁾

88

152

I_RC120M

t_STARTUP

V_VDDCORE= 1.8V

µs

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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7.6.6

32kHz RC Oscillator (RC32K) Characteristics

Table 7-16. 32kHz RC Oscillator Characteristics

Symbol

f_OUT

Parameter

Conditions

Min

Typ

32

Max

Unit

kHz

µA

Output frequency⁽¹⁾

Current consumption

Startup time⁽¹⁾

20

44

I_RC32K

0.7

100

t_STARTUP

µs

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.6.7

System RC Oscillator (RCSYS) Characteristics

Table 7-17. System RC Oscillator Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_OUT

Output frequency

Calibrated at 85°C

111.6

115

118.4

kHz

7.7

Flash Characteristics

Table 7-18 gives the device maximum operating frequency depending on the number of flash

wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the

number of wait states used when accessing the flash memory.

Table 7-18. Maximum Operating Frequency

Flash Wait States

Read Mode

Maximum Operating Frequency

1

0

1

0

50MHz

25MHz

30MHz

15MHz

High speed read mode

Normal read mode

Table 7-19. Flash Characteristics

Symbol

t_FPP

Parameter

Conditions

Min

Typ

5

Max

Unit

Page programming time

Page erase time

t_FPE

5

f_{CLK_HSB}= 50MHz

t_FFP

Fuse programming time

Full chip erase time (EA)

JTAG chip erase time (CHIP_ERASE)

1

ms

t_FEA

6

t_FCE

f_{CLK_HSB}= 115kHz

310

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Table 7-20. Flash Endurance and Data Retention

Symbol

N_FARRAY

N_FFUSE

t_RET

Parameter

Conditions

Min

100k

10k

15

Typ

Max

Unit

cycles

years

Array endurance (write/page)

General Purpose fuses endurance (write/bit)

Data retention

7.8

Analog Characteristics

7.8.1

Voltage Regulator Characteristics

Table 7-21. VREG Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

3.3

1.8

Max

Units

V_VDDIN

Input voltage range

1.98

3.6

V

V_VDDCOREOutput voltage, calibrated value

Output voltage accuracy⁽¹⁾

V_VDDIN>= 1.98V

I_OUT= 0.1mA to 60mA,

V_VDDIN> 1.98V

2

4

%

I_OUT= 0.1mA to 60mA,

V_VDDIN< 1.98V

Normal mode

60

1

I_OUT

DC output current⁽¹⁾

mA

µA

Low power mode

Normal mode

13

4

I_VREG

Note:

Static current of internal regulator

Low power mode

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-22. Decoupling Requirements

Symbol

C_IN1

Parameter

Condition

Typ

33

Techno.

Units

Input regulator capacitor 1

Input regulator capacitor 2

Input regulator capacitor 3

Output regulator capacitor 1

nF

C_IN2

100

10

C_IN3

µF

nF

C_OUT1

100

Tantalum

C_OUT2

Output regulator capacitor 2

2.2

µF

0.5<ESR<10Ohm

Note:

1. Refer to Section 6.1.2 on page 36.

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7.8.2

Power-on Reset 18 Characteristics

Table 7-23. POR18 Characteristics

Symbol

V_POT+

Parameter

Condition

Min

Typ

1.45

Max

Units

Voltage threshold on V_VDDCORErising

Voltage threshold on V_VDDCOREfalling

1.58

V

V_POT-

1.2

1.32

Time with VDDCORE < V_POT-

necessary to generate a reset

signal

t_DET

Detection time⁽¹⁾

460

µs

I_POR18

Current consumption

Startup time⁽¹⁾

4

6

µA

µs

t_STARTUP

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Figure 7-5. POR18 Operating Principle

V_POT+

V_POT-

Time

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7.8.3

Power-on Reset 33 Characteristics

Table 7-24. POR33 Characteristics

Symbol

V_POT+

Parameter

Condition

Min

Typ

1.49

Max

Units

Voltage threshold on V_VDDINrising

Voltage threshold on V_VDDINfalling

1.58

V

V_POT-

1.3

1.45

Time with VDDIN < V_POT-

necessary to generate a reset

signal

t_DET

Detection time⁽¹⁾

460

µs

I_POR33

Current consumption

Startup time⁽¹⁾

20

µA

µs

t_STARTUP

400

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Figure 7-6. POR33 Operating Principle

V_POT+

V_POT-

Time

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7.8.4

Brown Out Detector Characteristics

The values in Table 7-25 describe the values of the BODLEVEL in the flash General Purpose

Fuse register.

Table 7-25. BODLEVEL Values

BODLEVEL Value

Min

Typ

Max

Units

011111 binary (31) 0x1F

100111 binary (39) 0x27

1.60

1.69

V

Table 7-26. BOD Characteristics

Symbol

Parameter

Condition

T = 25°C

Min

Typ

Max

Units

mV

V_HYST

BOD hysteresis

10

Time with VDDCORE <

BODLEVEL necessary to

generate a reset signal

t_DET

Detection time

1

µs

I_BOD

Current consumption

Startup time

7

5

µA

µs

t_STARTUP

7.8.5

Supply Monitor 33 Characteristics

Table 7-27. SM33 Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_TH

Voltage threshold

Calibrated⁽¹⁾, T = 25°C

1.675

1.75

1.825

V

Step size, between adjacent values

in SCIF.SM33.CALIB⁽²⁾

11

30

mV

V_HYST

t_DET

Hysteresis⁽²⁾

Time with VDDIN < V_TH

necessary to generate a reset

signal

Detection time

280

µs

I_SM33

Current consumption

Startup time

Normal mode

17

µA

µs

t_STARTUP

140

Notes: 1. Calibration value can be read from the SM33.CALIB field. This field is updated by the flash fuses after a reset. Refer to SCIF

chapter for details.

2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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7.8.6

Analog to Digital Converter Characteristics

Table 7-28. ADC Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Units

f_ADC

ADC clock frequency

12-bit resolution mode

10-bit resolution mode

8-bit resolution mode

Return from Idle Mode

f_ADC= 6MHz

6

MHz

f_ADC

ADC clock frequency

MHz

t_STARTUP

t_CONV

Startup time

15

µs

Conversion time (latency)

11

26

28

cycles

V_VDD> 3.0V, f_ADC= 6MHz,

Throughput rate

12-bit resolution mode,

low impedance source

kSPS

V_VDD> 3.0V, f_ADC= 6MHz,

10-bit resolution mode,

low impedance source

460

Throughput rate

kSPS

V_VDD> 3.0V, f_ADC= 6MHz,

8-bit resolution mode,

low impedance source

460

V_ADVREFP

I_ADC

Reference voltage range

V_ADVREFP= V_VDDANA

ADC Clock = 6MHz

1.62

1.98

V

Current consumption on V_VDDANA

350

150

µA

Current consumption on ADVREFP

I_ADVREFP

f_ADC= 6MHz

Note:

These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process

technology. These values are not covered by test limits in production.

7.8.6.1

Inputs and Sample and Hold Acquisition Times

Table 7-29. Analog Inputs

Symbol

Parameter

Conditions

12-bit mode

10-bit mode

8-bit mode

Min

Typ

Max

Units

V

V_ADn

Input Voltage Range

Internal Capacitance⁽¹⁾

Internal Resistance⁽¹⁾

0

V_ADVREFP

C_ONCHIP

22.5

3.15

55.9

pF

V_VDDIO= 3.0V to 3.6V,

V_VDDCORE= 1.8V

R_ONCHIP

kOhm

V_VDDIO= V_VDDCORE= 1.62V to 1.98V

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the

ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resis-

tor (R_ONCHIP) and a capacitor (C_ONCHIP). In addition, the resistance (R_SOURCE) and capacitance

(C_SOURCE) of the PCB and source must be taken into account when calculating the required

sample and hold time. Figure 7-7 shows the ADC input channel equivalent circuit.

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Figure 7-7. ADC Input

Positive Input

R_SOURCE

R_ONCHIP

C_SOURCE

C_ONCHIP

ADCVREFP/2

V_IN

The minimum sample and hold time (in ns) can be found using this formula:

t_SAMPLEHOLD≥ (R_ONCHIP+ R_SOURCE) × (C_ONCHIP+ C_SOURCE) × ln(2^{n + 1}

)

Where n is the number of bits in the conversion. t_SAMPLEHOLDis defined by the SHTIM field in the

ADCIFB ACR register. Please refer to the ADCIFB chapter for more information.

7.8.6.2

Applicable Conditions and Derating Data

Table 7-30. Transfer Characteristics 12-bit Resolution Mode⁽¹⁾

Parameter

Conditions

Min

Typ

Max

Units

Resolution

12

Bit

ADC clock frequency = 6MHz,

+/-4

Input Voltage Range = 0 - V_ADVREFP

Integral non-linearity

ADC clock frequency = 6MHz,

+/-2

Input Voltage Range = (10% V_ADVREFP) -

LSB

(90% V_ADVREFP

)

Differential non-linearity

Offset error

-1.5

1.5

ADC clock frequency = 6MHz

+/-3

+/-5

Gain error

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-31. Transfer Characteristics, 10-bit Resolution Mode⁽¹⁾

Parameter

Conditions

Min

Typ

10

Max

Units

Resolution

Bit

Integral non-linearity

Differential non-linearity

Offset error

+/-1

-1

1

ADC clock frequency = 6MHz

LSB

+/-1

+/-2

Gain error

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Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Table 7-32. Transfer Characteristics, 8-bit Resolution Mode⁽¹⁾

Parameter

Conditions

Min

Typ

8

Max

Units

Resolution

Bit

Integral non-linearity

Differential non-linearity

Offset error

+/-0.5

-0.3

0.3

ADC clock frequency = 6MHz

LSB

+/-1

Gain error

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.8.7

Temperature Sensor Characteristics

Table 7-33. Temperature Sensor Characteristics⁽¹⁾

Symbol

Parameter

Condition

Min

Typ

1

Max

Units

mV/°C

Gradient

I_TS

Current consumption

Startup time

1

µA

µs

t_STARTUP

0

Note:

1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy.

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7.8.8

Analog Comparator Characteristics

Table 7-34. Analog Comparator Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Positive input

-0.2

V_VDDIO+ 0.3

voltage range⁽³⁾

V

Negative input

voltage range⁽³⁾

-0.2

V_VDDIO- 0.6

V_ACREFN= 1.0V,

f_AC= 12MHz,

Statistical offset⁽³⁾

20

mV

filter length = 2,

hysteresis = 0⁽¹⁾

Clock frequency for

GCLK4⁽³⁾

f_AC

12

MHz

Comparisons

per second

Throughput rate⁽³⁾

f_AC= 12MHz

12 000 000

Delay from input

change to

Interrupt Status

Register Changes

⎛

⎝

1

⎞

Propagation delay

+ 3 × t_CLKACIFB

ns

----------------------------------------

t_CLKACIFB× f_AC

⎠

All channels,

VDDIO = 3.3V,

Current

I_AC

420

µA

consumption⁽³⁾

f_A= 3MHz

t_STARTUP

Startup time

3

cycles

Input current per

pin⁽³⁾

0.2

µA/MHz⁽²⁾

Notes: 1. AC.CONFn.FLEN and AC.CONFn.HYS fields, refer to the Analog Comparator Interface chapter.

2. Referring to f_AC

.

3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.8.9

Capacitive Touch Characteristics

7.8.9.1

Discharge Current Source

Table 7-35. DICS Characteristics

Symbol

R_REF

k

Parameter

Min

Typ

170

0.7

Max

Unit

kOhm

%

Internal resistor

Trim step size⁽¹⁾

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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7.8.9.2

Strong Pull-up Pull-down

Table 7-36. Strong Pull-up Pull-down

Parameter

Min

Typ

Max

Unit

Pull-down resistor

1

kOhm

Pull-up resistor

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7.9

Timing Characteristics

7.9.1

Startup, Reset, and Wake-up Timing

The startup, reset, and wake-up timings are calculated using the following formula:

t = t

+ N

× t

CONST

CPU

Where t

and N

are found in Table 7-37. t

is the period of the CPU clock. If a

CPU

CONST

CPU

clock source other than RCSYS is selected as the CPU clock, the oscillator startup time,

, must be added to the wake-up time from the stop, deepstop, and static sleep

t

OSCSTART

modes. Please refer to the source for the CPU clock in the ”Oscillator Characteristics” on page

49 for more details about oscillator startup times.

Table 7-37. Maximum Reset and Wake-up Timing⁽¹⁾

Parameter

Measuring

Max t

(in µs) Max N

CONST

CPU

Time from VDDIN crossing the V_POT+threshold of

POR33 to the first instruction entering the decode

stage of CPU. VDDCORE is supplied by the internal

regulator.

Startup time from power-up, using

regulator

2210

0

Time from VDDIN crossing the V_POT+threshold of

POR33 to the first instruction entering the decode

stage of CPU. VDDCORE is connected to VDDIN.

Startup time from power-up, no

regulator

1810

170

0

Time from releasing a reset source (except POR18,

POR33, and SM33) to the first instruction entering

the decode stage of CPU.

Startup time from reset release

Idle

0

19

Frozen

110

116

From wake-up event to the first instruction of an

interrupt routine entering the decode stage of the

CPU.

Standby

Wake-up

Stop

27 + t

97 + t

OSCSTART

Deepstop

Static

From wake-up event to the first instruction entering

the decode stage of the CPU.

Wake-up from shutdown

1180

0

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

7.9.2

RESET_N Timing

Table 7-38. RESET_N Waveform Parameters⁽¹⁾

Symbol

Parameter

Conditions

Min

10

Max

Units

ns

t_RESET

RESET_N minimum pulse length

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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7.9.3

USART in SPI Mode Timing

7.9.3.1

Master mode

Figure 7-8. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)

SPCK

MISO

USPI0

USPI1

MOSI

USPI2

Figure 7-9. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and

CPHA= 0)

SPCK

MISO

USPI3

USPI4

MOSI

USPI5

Table 7-39. USART in SPI Mode Timing, Master Mode⁽¹⁾

Symbol

USPI0

USPI1

USPI2

USPI3

USPI4

USPI5

Parameter

Conditions

Min

Max

16.5

Units

(2)

MISO setup time before SPCK rises

MISO hold time after SPCK rises

SPCK rising to MOSI delay

MISO setup time before SPCK falls

MISO hold time after SPCK falls

SPCK falling to MOSI delay

28.7 + t_SAMPLE

0

V_VDDIOfrom

3.0V to 3.6V,

maximum

external

capacitor =

40pF

ns

25.8 + t_SAMPLE

0

21.19

Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

t_SPCK

1

2

⎛

⎞

2. Where: t_SAMPLE= t_SPCK

–

-- × t_CLKUSART

------------------------------------

⎝

⎠

2 × t_CLKUSART

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Maximum SPI Frequency, Master Output

The maximum SPI master output frequency is given by the following formula:

× 2

f

1

SPIn

CLKSPI

f

= MIN(f

,------------ , ----------------------------)

PINMAX

SPCKMAX

9

Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f_PINMAXis

the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for

the maximum frequency of the pins. f_CLKSPIis the maximum frequency of the CLK_SPI. Refer

to the SPI chapter for a description of this clock.

Maximum SPI Frequency, Master Input

The maximum SPI master input frequency is given by the following formula:

f

× 2

1

CLKSPI

f

= MIN(-----------------------------------,----------------------------)

SPCKMAX

SPIn + t

9

VALID

Where SPIn is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending on

CPOL and NCPHA.T_VALIDis the SPI slave response time. Please refer to the SPI slave

datasheet for T_VALID.f_CLKSPIis the maximum frequency of the CLK_SPI. Refer to the SPI chap-

ter for a description of this clock.

7.9.3.2

Slave mode

Figure 7-10. USART in SPI Slave Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and

CPHA= 0)

SPCK

MISO

USPI6

MOSI

USPI7

USPI8

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Figure 7-11. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)

SPCK

MISO

USPI9

MOSI

USPI10

USPI11

Figure 7-12. USART in SPI Slave Mode, NPCS Timing

USPI12

USPI13

USPI15

SPCK, CPOL=0

SPCK, CPOL=1

USPI14

NSS

Table 7-40. USART in SPI mode Timing, Slave Mode⁽¹⁾

Symbol

Parameter

Conditions

Min

Max

Units

USPI6

SPCK falling to MISO delay

37.3

(2)

2.6 + t_SAMPLE

+

USPI7

MOSI setup time before SPCK rises

t_{CLK_USART}

USPI8

USPI9

MOSI hold time after SPCK rises

SPCK rising to MISO delay

0

V_VDDIOfrom

3.0V to 3.6V,

maximum

external

37.0

(2)

2.6 + t_SAMPLE

t_{CLK_USART}

USPI10

MOSI setup time before SPCK falls

ns

capacitor =

40pF

USPI11

USPI12

USPI13

USPI14

USPI15

MOSI hold time after SPCK falls

NSS setup time before SPCK rises

NSS hold time after SPCK falls

NSS setup time before SPCK falls

NSS hold time after SPCK rises

0

27.2

0

27.2

0

Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

t_SPCK

1

2

⎛

⎞

2. Where: t_SAMPLE= t_SPCK

–

+ -- × t_CLKUSART

------------------------------------

⎝

⎠

2 × t_CLKUSART

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Maximum SPI Frequency, Slave Input Mode

The maximum SPI slave input frequency is given by the following formula:

× 2

f

1

SPIn

CLKSPI

f

= MIN(----------------------------,------------ )

SPCKMAX

9

Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending

on CPOL and NCPHA. f_CLKSPIis the maximum frequency of the CLK_SPI. Refer to the SPI

chapter for a description of this clock.

Maximum SPI Frequency, Slave Output Mode

The maximum SPI slave output frequency is given by the following formula:

f

× 2

1

CLKSPI

f

= MIN(----------------------------, f

,------------------------------------ )

SPCKMAX

PINMAX

9

SPIn + t

SETUP

Where SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. T_SETUPis

the SPI master setup time. Please refer to the SPI master datasheet for T_SETUP. f_CLKSPIis the

maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this

clock.f_PINMAXis the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris-

tics section for the maximum frequency of the pins.

7.9.4

SPI Timing

7.9.4.1

Master mode

Figure 7-13. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)

SPCK

MISO

SPI0

SPI1

MOSI

SPI2

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Figure 7-14. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)

SPCK

MISO

SPI3

SPI4

MOSI

SPI5

Table 7-41. SPI Timing, Master Mode⁽¹⁾

Symbol

SPI0

SPI1

SPI2

SPI3

SPI4

SPI5

Parameter

Conditions

Min

Max

7.1

Units

MISO setup time before SPCK rises

MISO hold time after SPCK rises

SPCK rising to MOSI delay

33.4 + (t_{CLK_SPI})/2

0

V_VDDIOfrom

3.0V to 3.6V,

maximum

external

capacitor =

40pF

ns

MISO setup time before SPCK falls

MISO hold time after SPCK falls

SPCK falling to MOSI delay

29.2 + (t_{CLK_SPI})/2

0

8.63

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Maximum SPI Frequency, Master Output

The maximum SPI master output frequency is given by the following formula:

1

f

= MIN(f

,------------ )

PINMAX

SPCKMAX

SPIn

Where SPIn is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. f_PINMAXis the

maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the

maximum frequency of the pins.

Maximum SPI Frequency, Master Input

The maximum SPI master input frequency is given by the following formula:

1

f

= -----------------------------------

SPCKMAX

SPIn + t

VALID

Where SPIn is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on

CPOL and NCPHA. t_VALIDis the SPI slave response time. Please refer to the SPI slave

datasheet for t_VALID

.

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7.9.4.2

Slave mode

Figure 7-15. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)

SPCK

MISO

SPI6

MOSI

SPI7

SPI8

Figure 7-16. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)

SPCK

MISO

SPI9

MOSI

SPI10

SPI11

Figure 7-17. SPI Slave Mode, NPCS Timing

SPI12

SPI13

SPI15

SPCK, CPOL=0

SPCK, CPOL=1

SPI14

NPCS

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Table 7-42. SPI Timing, Slave Mode⁽¹⁾

Symbol

SPI6

Parameter

Conditions

Min

Max

Units

SPCK falling to MISO delay

29.4

SPI7

MOSI setup time before SPCK rises

MOSI hold time after SPCK rises

SPCK rising to MISO delay

0

SPI8

6.0

V_VDDIOfrom

3.0V to 3.6V,

maximum

external

capacitor =

40pF

SPI9

29.0

SPI10

SPI11

SPI12

SPI13

SPI14

SPI15

MOSI setup time before SPCK falls

MOSI hold time after SPCK falls

NPCS setup time before SPCK rises

NPCS hold time after SPCK falls

NPCS setup time before SPCK falls

NPCS hold time after SPCK rises

0

ns

5.5

3.4

1.1

3.3

0.7

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

Maximum SPI Frequency, Slave Input Mode

The maximum SPI slave input frequency is given by the following formula:

1

f

= MIN(f

,------------ )

CLKSPI

SPCKMAX

SPIn

Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on

CPOL and NCPHA. f_CLKSPIis the maximum frequency of the CLK_SPI. Refer to the SPI chap-

ter for a description of this clock.

Maximum SPI Frequency, Slave Output Mode

The maximum SPI slave output frequency is given by the following formula:

1

f

= MIN(f

,------------------------------------ )

PINMAX

SPCKMAX

SPIn + t

SETUP

Where SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. t_SETUPis the

SPI master setup time. Please refer to the SPI master datasheet for t_SETUP.f_PINMAXis the max-

imum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the

maximum frequency of the pins.

7.9.5

TWIM/TWIS Timing

Figure 7-43 shows the TWI-bus timing requirements and the compliance of the device with

them. Some of these requirements (t_rand t_f) are met by the device without requiring user inter-

vention. Compliance with the other requirements (t_HD-STA, t_SU-STA, t_SU-STO, t_HD-DAT, t_SU-DAT-TWI, t_LOW-

_TWI, t_HIGH, and f_TWCK) requires user intervention through appropriate programming of the relevant

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TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more

information.

Table 7-43. TWI-Bus Timing Requirements

Minimum

Requirement

Maximum

Requirement

Symbol

t_r

Parameter

Mode

Standard⁽¹⁾

Fast⁽¹⁾

Standard

Fast

Device

Unit

-

1000

300

TWCK and TWD rise time

ns

20 + 0.1C_b

-

t_f

TWCK and TWD fall time

(Repeated) START hold time

(Repeated) START set-up time

STOP set-up time

ns

μs

20 + 0.1C_b

Standard

Fast

4

t_HD-STA

t_SU-STA

t_SU-STO

t_HD-DAT

t_clkpb

-

0.6

4.7

0.6

4.0

0.6

Standard

Fast

t_clkpb

Standard

Fast

4t_clkpb

Standard

Fast

3.45⁽⁾

0.9⁽⁾

Data hold time

0.3⁽²⁾

2t_clkpb

15t_prescaled+ t_clkpbμs

Standard

Fast

250

100

-

t_SU-DAT-TWIData set-up time

t_SU-DAT

t_LOW-TWI

t_LOW

2t_clkpb

t_clkpb

4t_clkpb

t_clkpb

-

ns

-

Standard

Fast

4.7

1.3

-

TWCK LOW period

μs

-

Standard

Fast

4.0

0.6

t_HIGH

TWCK HIGH period

TWCK frequency

8t_clkpb

μs

Standard

Fast

100

400

1

f_TWCK

-

-----------------------

kHz

12t

clkpb

Notes: 1. Standard mode: f_TWCK≤ 100 kHz ; fast mode: f_TWCK> 100 kHz .

2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.

Notations:

C_b= total capacitance of one bus line in pF

t_clkpb= period of TWI peripheral bus clock

t_prescaled= period of TWI internal prescaled clock (see chapters on TWIM and TWIS)

The maximum t_HD;DAThas only to be met if the device does not stretch the LOW period (t_LOW-TWI

of TWCK.

)

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7.9.6

JTAG Timing

Figure 7-18. JTAG Interface Signals

JTAG2

TCK

JTAG0

JTAG1

TMS/TDI

JTAG3

JTAG4

TDO

JTAG5

JTAG6

Boundary

Scan Inputs

JTAG7

JTAG8

Boundary

Scan Outputs

JTAG9

JTAG10

Table 7-44. JTAG Timings⁽¹⁾

Symbol

JTAG0

JTAG1

JTAG2

JTAG3

JTAG4

JTAG5

JTAG6

JTAG7

JTAG8

JTAG9

JTAG10

Parameter

Conditions

Min

21.8

8.6

Max

Units

TCK Low Half-period

TCK High Half-period

TCK Period

30.3

2.0

TDI, TMS Setup before TCK High

TDI, TMS Hold after TCK High

TDO Hold Time

V_VDDIOfrom

3.0V to 3.6V,

maximum

external

capacitor =

40pF

2.3

9.5

ns

TCK Low to TDO Valid

21.8

32.2

Boundary Scan Inputs Setup Time

Boundary Scan Inputs Hold Time

Boundary Scan Outputs Hold Time

TCK to Boundary Scan Outputs Valid

0.6

6.9

9.3

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

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8. Mechanical Characteristics

8.1

Thermal Considerations

8.1.1

Thermal Data

Table 8-1 summarizes the thermal resistance data depending on the package.

Table 8-1.

Symbol

θ_JA

Thermal Resistance Data

Parameter

Condition

Package

TQFP48

QFN48

Typ

54.4

15.7

26.0

1.6

Unit

Junction-to-ambient thermal resistance Still Air

Junction-to-case thermal resistance

°C/W

θ_JC

θ_JA

Junction-to-ambient thermal resistance Still Air

Junction-to-case thermal resistance

°C/W

θ_JC

QFN48

θ_JA

Junction-to-ambient thermal resistance Still Air

Junction-to-case thermal resistance

TLLGA48

25.4

12.7

θ_JC

8.1.2

Junction Temperature

The average chip-junction temperature, T_J, in °C can be obtained from the following:

1. = T + (P × θ

T

)

JA

J

A

D

2. T_J= T_A+ (P_D× (θ_HEATSINK+ θ_JC))

where:

• θ_JA= package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1.

• θ_JC= package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in

Table 8-1.

• θ_{HEAT SINK}= cooling device thermal resistance (°C/W), provided in the device datasheet.

• P_D= device power consumption (W) estimated from data provided in Section 7.4 on page 42.

• T_A= ambient temperature (°C).

From the first equation, the user can derive the estimated lifetime of the chip and decide if a

cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second

equation should be used to compute the resulting average chip-junction temperature T_Jin °C.

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8.2

Package Drawings

Figure 8-1. TQFP-48 Package Drawing

Table 8-2.

Device and Package Maximum Weight

140

mg

Table 8-3.

Package Characteristics

Moisture Sensitivity Level

MSL3

Table 8-4.

Package Reference

JEDEC Drawing Reference

JESD97 Classification

MS-026

E3

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Figure 8-2. QFN-48 Package Drawing

Note:

The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.

Table 8-5.

Device and Package Maximum Weight

140

mg

Table 8-6.

Package Characteristics

Moisture Sensitivity Level

MSL3

Table 8-7.

Package Reference

JEDEC Drawing Reference

JESD97 Classification

M0-220

E3

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Figure 8-3. TLLGA-48 Package Drawing

Table 8-8.

Device and Package Maximum Weight

39.3

mg

Table 8-9.

Package Characteristics

Moisture Sensitivity Level

MSL3

Table 8-10. Package Reference

JEDEC Drawing Reference

JESD97 Classification

N/A

E4

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8.3

Soldering Profile

Table 8-11 gives the recommended soldering profile from J-STD-20.

Table 8-11. Soldering Profile

Profile Feature

Green Package

3°C/s max

150-200°C

60-150 s

Average Ramp-up Rate (217°C to Peak)

Preheat Temperature 175°C 25°C

Time Maintained Above 217°C

Time within 5°C of Actual Peak Temperature

Peak Temperature Range

30 s

260°C

Ramp-down Rate

6°C/s max

8 minutes max

Time 25°C to Peak Temperature

A maximum of three reflow passes is allowed per component.

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9. Ordering Information

Table 9-1.

Ordering Information

Temperature Operating

Device

Ordering Code

Carrier Type

ES

Package

Package Type

Range

AT32UC3L0256-AUTES

AT32UC3L0256-AUT

AT32UC3L0256-AUR

AT32UC3L0256-ZAUTES

Tray

TQFP 48

Tape & Reel

ES

JESD97 Classification E3

AT32UC3L0256

AT32UC3L0256-ZAUT

AT32UC3L0256-ZAUR

AT32UC3L0256-D3HES

AT32UC3L0256-D3HT

AT32UC3L0256-D3HR

AT32UC3L0128-AUT

AT32UC3L0128-AUR

AT32UC3L0128-ZAUT

AT32UC3L0128-ZAUR

AT32UC3L0128-D3HT

AT32UC3L0128-D3HR

Tray

QFN 48

Tape & Reel

ES

Tray

TLLGA 48

JESD97 Classification E4 Industrial (-40°C to 85°C)

Tape & Reel

Tray

TQFP 48

QFN 48

Tape & Reel

Tray

JESD97 Classification E3

JESD97 Classification E4

AT32UC3L0128

Tape & Reel

Tray

TLLGA 48

Tape & Reel

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10. Errata

10.1 Rev. C

10.1.1

SCIF

1. The RC32K output on PA20 is not always permanently disabled

The RC32K output on PA20 may sometimes re-appear.

Fix/Workaround

Before using RC32K for other purposes, the following procedure has to be followed in order

to properly disable it:

- Run the CPU on RCSYS

- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT

- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as

one

- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as

zero.

2. PLLCOUNT value larger than zero can cause PLLEN glitch

Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-

nal during asynchronous wake up.

Fix/Workaround

The lock-masking mechanism for the PLL should not be used.

The PLLCOUNT field of the PLL Control Register should always be written to zero.

3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature

The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-

tion in the SCIF memory range.

Fix/Workaround

None.

10.1.2

SPI

1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0

When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI

module will not start a data transfer.

Fix/Workaround

Disable mode fault detection by writing a one to MR.MODFDIS.

2. Disabling SPI has no effect on the SR.TDRE bit

Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered

when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is

disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer

is empty, and this data will be lost.

Fix/Workaround

Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the

SPI and PDCA.

3. SPI disable does not work in SLAVE mode

SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

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4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

5. SPI mode fault detection enable causes incorrect behavior

When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate

properly.

Fix/Workaround

Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

6. SPI RDR.PCS is not correct

The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not

correctly indicate the value on the NPCS pins at the end of a transfer.

Fix/Workaround

Do not use the PCS field of the SPI RDR.

10.1.3

TWI

1. SMBALERT bit may be set after reset

The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after

system reset.

Fix/Workaround

After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.

2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

set.

10.1.4

TC

1. Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

10.1.5

CAT

1. CAT QMatrix sense capacitors discharged prematurely

At the end of a QMatrix burst charging sequence that uses different burst count values for

different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-

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eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.

This results in premature loss of charge from the sense capacitors and thus increased vari-

ability of the acquired count values.

Fix/Workaround

Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,

13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.

2. Autonomous CAT acquisition must be longer than AST source clock period

When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the

CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST

source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,

the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,

ruining the result.

Fix/Workaround

Always ensure that the ATCFG1.max field is set so that the duration of the autonomous

touch acquisition is greater than one clock period of the AST source clock.

10.1.6

aWire

1. aWire MEMORY_SPEED_REQUEST command does not return correct CV

The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to

the formula in the aWire Debug Interface chapter.

Fix/Workaround

Issue

a

dummy read to address 0x100000000 before issuing the

MEMORY_SPEED_REQUEST command and use this formula instead:

7f_aw

f_sab= ----------------

CV – 3

10.2 Rev. B

10.2.1

SCIF

1. The RC32K output on PA20 is not always permanently disabled

The RC32K output on PA20 may sometimes re-appear.

Fix/Workaround

Before using RC32K for other purposes, the following procedure has to be followed in order

to properly disable it:

- Run the CPU on RCSYS

- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT

- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as

one

- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as

zero.

2. PLLCOUNT value larger than zero can cause PLLEN glitch

Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-

nal during asynchronous wake up.

Fix/Workaround

The lock-masking mechanism for the PLL should not be used.

The PLLCOUNT field of the PLL Control Register should always be written to zero.

3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature

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The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-

tion in the SCIF memory range.

Fix/Workaround

None.

10.2.2

WDT

1. WDT Control Register does not have synchronization feedback

When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),

Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-

nizer is started to propagate the values to the WDT clcok domain. This synchronization

takes a finite amount of time, but only the status of the synchronization of the EN bit is

reflected back to the user. Writing to the synchronized fields during synchronization can lead

to undefined behavior.

Fix/Workaround

-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock

cycles of both the WDT peripheral bus clock and the selected WDT clock source.

-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the

written value.

10.2.3

SPI

1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0

When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI

module will not start a data transfer.

Fix/Workaround

Disable mode fault detection by writing a one to MR.MODFDIS.

2. Disabling SPI has no effect on the SR.TDRE bit

Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered

when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is

disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer

is empty, and this data will be lost.

Fix/Workaround

Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the

SPI and PDCA.

3. SPI disable does not work in SLAVE mode

SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

5. SPI mode fault detection enable causes incorrect behavior

When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate

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properly.

Fix/Workaround

Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

6. SPI RDR.PCS is not correct

The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not

correctly indicate the value on the NPCS pins at the end of a transfer.

Fix/Workaround

Do not use the PCS field of the SPI RDR.

10.2.4

TWI

1. TWIS may not wake the device from sleep mode

If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-

tion, the CPU may not wake upon a TWIS address match. The request is NACKed.

Fix/Workaround

When using the TWI address match to wake the device from sleep, do not switch to sleep

modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the

TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus

events.

2. SMBALERT bit may be set after reset

The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after

system reset.

Fix/Workaround

After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.

3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

set.

10.2.5

PWMA

1. The SR.READY bit cannot be cleared by writing to SCR.READY

The Ready bit in the Status Register will not be cleared when writing a one to the corre-

sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is

set.

Fix/Workaround

Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an

operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-

tus Register before enabling the interrupt.

10.2.6

TC

1. Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

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Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

10.2.7

CAT

1. CAT QMatrix sense capacitors discharged prematurely

At the end of a QMatrix burst charging sequence that uses different burst count values for

different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-

eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.

This results in premature loss of charge from the sense capacitors and thus increased vari-

ability of the acquired count values.

Fix/Workaround

Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,

13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.

2. Autonomous CAT acquisition must be longer than AST source clock period

When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the

CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST

source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,

the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,

ruining the result.

Fix/Workaround

Always ensure that the ATCFG1.max field is set so that the duration of the autonomous

touch acquisition is greater than one clock period of the AST source clock.

3. CAT consumes unnecessary power when disabled or when autonomous touch not

used

A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-

ule is disabled or when the autonomous touch feature is not used, thereby causing

unnecessary power consumption.

Fix/Workaround

If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT

module is used but the autonomous touch feature is not used, the power consumption of the

CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.

10.2.8

aWire

1. aWire MEMORY_SPEED_REQUEST command does not return correct CV

The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to

the formula in the aWire Debug Interface chapter.

Fix/Workaround

Issue

a

dummy read to address 0x100000000 before issuing the

MEMORY_SPEED_REQUEST command and use this formula instead:

7f_aw

f_sab= ----------------

CV – 3

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10.3 Rev. A

10.3.1

Device

1. JTAGID is wrong

The JTAGID is 0x021DF03F.

Fix/Workaround

None.

10.3.2

FLASHCDW

1. General-purpose fuse programming does not work

The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the

Fuse Settings chapter in the FLASHCDW for more information about what functions are

affected.

Fix/Workaround

None.

2. Set Security Bit command does not work

The Set Security Bit (SSB) command of the FLASHCDW does not work. The device cannot

be locked from external JTAG, aWire, or other debug accesses.

Fix/Workaround

None.

3. Flash programming time is longer than specified

The flash programming time is now:

Table 10-1. Flash Characteristics

Symbol Parameter

Conditions

Min

Typ

7.5

1

Max

Unit

T_FPP

T_FPE

T_FFP

T_FEA

Page programming time

Page erase time

f

_{CLK_HSB}= 50MHz

Fuse programming time

Full chip erase time (EA)

ms

9

JTAG chip erase time

(CHIP_ERASE)

T_FCE

f_{CLK_HSB}= 115kHz

250

Fix/Workaround

None.

10.3.3

Power Manager

1. Clock Failure Detector (CFD) can be issued while turning off the CFD

While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will

change the main clock source to RCSYS.

Fix/Workaround

Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch

back to original main clock source.

Solution 2: Only turn off the CFD while running the main clock on RCSYS.

2. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks

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If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-

ing, all PB clocks will be masked except the PB clock to the sleepwalking module.

Fix/Workaround

Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.

2. Unused PB clocks are running

Three unused PBA clocks are enabled by default and will cause increased active power

consumption.

Fix/Workaround

Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register.

10.3.4

SCIF

1. The RC32K output on PA20 is not always permanently disabled

The RC32K output on PA20 may sometimes re-appear.

Fix/Workaround

Before using RC32K for other purposes, the following procedure has to be followed in order

to properly disable it:

- Run the CPU on RCSYS

- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT

- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as

one

- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as

zero.

2. PLL lock might not clear after disable

Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator

may not go back to zero after the PLL oscillator has been disabled. This can cause the prop-

agation of clock signals with the wrong frequency to parts of the system that use the PLL

clock.

Fix/Workaround

PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL

has been turned off, a delay of 30us must be observed after the PLL has been enabled

again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is

locked.

3. PLLCOUNT value larger than zero can cause PLLEN glitch

Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-

nal during asynchronous wake up.

Fix/Workaround

The lock-masking mechanism for the PLL should not be used.

The PLLCOUNT field of the PLL Control Register should always be written to zero.

4. RCSYS is not calibrated

The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz

can be expected.

Fix/Workaround

If a known clock source is available the RCSYS can be runtime calibrated by using the fre-

quency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF.

5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature

The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-

tion in the SCIF memory range.

Fix/Workaround

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None.

10.3.5

WDT

1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will

issue a Watchdog reset

If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-

ately issue a Watchdog reset.

Fix/Workaround

Use twice as long timeout period as needed and clear the WDT counter within the first half

of the timeout period. If the WDT counter is cleared after the first half of the timeout period,

you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time

before the reset will be twice as long as needed.

2. WDT Control Register does not have synchronization feedback

When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),

Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-

nizer is started to propagate the values to the WDT clcok domain. This synchronization

takes a finite amount of time, but only the status of the synchronization of the EN bit is

reflected back to the user. Writing to the synchronized fields during synchronization can lead

to undefined behavior.

Fix/Workaround

-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock

cycles of both the WDT peripheral bus clock and the selected WDT clock source.

-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the

written value.

10.3.6

GPIO

1. Clearing Interrupt flags can mask other interrupts

When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening

in the same clock cycle will not be registered.

Fix/Workaround

Read the PVR register of the port before and after clearing the interrupt to see if any pin

change has happened while clearing the interrupt. If any change occurred in the PVR

between the reads, they must be treated as an interrupt.

10.3.7

SPI

1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0

When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI

module will not start a data transfer.

Fix/Workaround

Disable mode fault detection by writing a one to MR.MODFDIS.

2. Disabling SPI has no effect on the SR.TDRE bit

Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered

when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is

disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer

is empty, and this data will be lost.

Fix/Workaround

Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the

SPI and PDCA.

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3. SPI disable does not work in SLAVE mode

SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

5. SPI mode fault detection enable causes incorrect behavior

When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate

properly.

Fix/Workaround

Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

6. SPI RDR.PCS is not correct

The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not

correctly indicate the value on the NPCS pins at the end of a transfer.

Fix/Workaround

Do not use the PCS field of the SPI RDR.

10.3.8

TWI

1. TWIS may not wake the device from sleep mode

If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-

tion, the CPU may not wake upon a TWIS address match. The request is NACKed.

Fix/Workaround

When using the TWI address match to wake the device from sleep, do not switch to sleep

modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the

TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus

events.

2. SMBALERT bit may be set after reset

The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after

system reset.

Fix/Workaround

After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.

3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

set.

4. TWIS stretch on Address match error

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When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for

the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD

at the same time. This can cause a TWI timing violation.

Fix/Workaround

None.

5. TWIM TWALM polarity is wrong

The TWALM signal in the TWIM is active high instead of active low.

Fix/Workaround

Use an external inverter to invert the signal going into the TWIM. When using both TWIM

and TWIS on the same pins, the TWALM cannot be used.

10.3.9

PWMA

1. The SR.READY bit cannot be cleared by writing to SCR.READY

The Ready bit in the Status Register will not be cleared when writing a one to the corre-

sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is

set.

Fix/Workaround

Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an

operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-

tus Register before enabling the interrupt.

10.3.10 TC

1. Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

10.3.11 ADCIFB

1. ADCIFB DMA transfer does not work with divided PBA clock

DMA requests from the ADCIFB will not be performed when the PBA clock is slower than

the HSB clock.

Fix/Workaround

Do not use divided PBA clock when the PDCA transfers from the ADCIFB.

10.3.12 CAT

1. CAT QMatrix sense capacitors discharged prematurely

At the end of a QMatrix burst charging sequence that uses different burst count values for

different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-

eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.

This results in premature loss of charge from the sense capacitors and thus increased vari-

ability of the acquired count values.

Fix/Workaround

Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,

13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.

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2. Autonomous CAT acquisition must be longer than AST source clock period

When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the

CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST

source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,

the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,

ruining the result.

Fix/Workaround

Always ensure that the ATCFG1.max field is set so that the duration of the autonomous

touch acquisition is greater than one clock period of the AST source clock.

3. CAT consumes unnecessary power when disabled or when autonomous touch not

used

A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-

ule is disabled or when the autonomous touch feature is not used, thereby causing

unnecessary power consumption.

Fix/Workaround

If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT

module is used but the autonomous touch feature is not used, the power consumption of the

CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.

4. CAT module does not terminate QTouch burst on detect

The CAT module does not terminate a QTouch burst when the detection voltage is

reached on the sense capacitor. This can cause the sense capacitor to be charged more

than necessary. Depending on the dielectric absorption characteristics of the capacitor, this

can lead to unstable measurements.

Fix/Workaround

Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and

TG1CFG1 registers.

10.3.13 aWire

1. aWire MEMORY_SPEED_REQUEST command does not return correct CV

The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to

the formula in the aWire Debug Interface chapter.

Fix/Workaround

Issue

a

dummy read to address 0x100000000 before issuing the

MEMORY_SPEED_REQUEST command and use this formula instead:

7f_aw

f_sab= ----------------

CV – 3

10.3.14 I/O Pins

1. PA05 is not 3.3V tolerant.

PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V.

Fix/Workaround

None.

2. No pull-up on pins that are not bonded

PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current

consumption on VDDIO/VDDIN if left undriven.

Fix/Workaround

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Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the

GPIO.

3. PA17 has low ESD tolerance

PA17 only tolerates 500V ESD pulses (Human Body Model).

Fix/Workaround

Care must be taken during manufacturing and PCB design.

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11. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

11.1 Rev. B – 01/2012

1.

Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz.

2.

3.

4.

Description: “One touch sensor can be configured to operate autonomously...” replaced by “All

touch sensors can be configured to operate autonomously...”.

Block Diagram: GCLK_IN is input, not output, and is 2 bits wide (GCLK_IN[1..0]). CAT SMP

corrected from I/O to output. SPI NPCS corrected from output to I/O.

Package and Pinout: PRND signal removed from Signal Descriptions List table and GPIO

Controller Function Multiplexing table.

5.

Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is

1.62-1.98V, not 1.98-3.6V. “On system start-up, the DFLL is disabled” is replaced by “On

system start-up, all high-speed clocks are disabled”.

6.

7.

ADCIFB: PRND signal removed from block diagram.

Electrical Characteristics: Added PLL source clock in the Clock Frequencies table in the

Maximum Clock Frequencies section. Removed 64-pin package information from I/O Pin

Characteristics tables and Digital Clock Characteristics table.

8.

Electrical Characteristics: Removed USB Transceiver Characteristics, as the device contains

no USB.

9.

Mechanical Characteristics: Added notes to package drawings.

10.

Summary: Removed Programming and Debugging chapter, added Processor and Architecture

chapter.

11.

Datasheet Revision History: Corrected release date for datasheet rev. A; the correct date is

12/2011.

11.2 Rev. A – 12/2011

1.

Initial revision.

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Table of Contents

Features..................................................................................................... 1

Description ............................................................................................... 3

Overview ................................................................................................... 5

1

2

2.1

2.2

Block Diagram ...................................................................................................5

Configuration Summary .....................................................................................6

3

4

Package and Pinout ................................................................................. 7

3.1

3.2

3.3

3.4

Package .............................................................................................................7

Peripheral Multiplexing on I/O Lines ..................................................................8

Signal Descriptions ..........................................................................................13

I/O Line Considerations ...................................................................................16

Processor and Architecture .................................................................. 18

4.1

4.2

4.3

4.4

4.5

Features ..........................................................................................................18

AVR32 Architecture .........................................................................................18

The AVR32UC CPU ........................................................................................19

Programming Model ........................................................................................23

Exceptions and Interrupts ................................................................................27

5

Memories ................................................................................................ 32

5.1

5.2

5.3

5.4

Embedded Memories ......................................................................................32

Physical Memory Map .....................................................................................32

Peripheral Address Map ..................................................................................33

CPU Local Bus Mapping .................................................................................34

6

7

Supply and Startup Considerations ..................................................... 36

6.1

6.2

Supply Considerations .....................................................................................36

Startup Considerations ....................................................................................40

Electrical Characteristics ...................................................................... 41

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Absolute Maximum Ratings* ...........................................................................41

Supply Characteristics .....................................................................................41

Maximum Clock Frequencies ..........................................................................42

Power Consumption ........................................................................................42

I/O Pin Characteristics .....................................................................................46

Oscillator Characteristics .................................................................................49

Flash Characteristics .......................................................................................54

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7.8

7.9

Analog Characteristics .....................................................................................55

Timing Characteristics .....................................................................................64

8

9

Mechanical Characteristics ................................................................... 74

8.1

8.2

8.3

Thermal Considerations ..................................................................................74

Package Drawings ...........................................................................................75

Soldering Profile ..............................................................................................78

Ordering Information ............................................................................. 79

10 Errata ....................................................................................................... 80

10.1

10.2

10.3

Rev. C ..............................................................................................................80

Rev. B ..............................................................................................................82

Rev. A ..............................................................................................................86

11 Datasheet Revision History .................................................................. 93

11.1

11.2

Rev. B – 01/2012 .............................................................................................93

Rev. A – 12/2011 .............................................................................................93

Table of Contents....................................................................................... i

ii

32145BS–01/2012

Atmel Corporation

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San Jose, CA 95131

USA

Tel: (+1)(408) 441-0311

Fax: (+1)(408) 487-2600

www.atmel.com

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Atmel^®, logo and combinations thereof, AVR^®, picoPower^®, QTouch^®, AKS^®and others are registered trademarks or trademarks of

Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to

any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL

TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY

EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,

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HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or com-

pleteness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.

Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suit-

able for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applica-

tions intended to support or sustain life.

32145BS–01/2012


型号：	AT32UC3L0256-ZAUR
厂家：	ATMEL
描述：	32-bit Atmel AVR Microcontroller 32位爱特梅尔AVR微控制器微控制器
文件：	总96页 (文件大小：1716K)
中文：	中文翻译
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