AT32UC3L032-AUR [ATMEL]
32-bit AVR®Microcontroller; 32位AVR®Microcontroller型号: | AT32UC3L032-AUR |
厂家: | ATMEL |
描述: | 32-bit AVR®Microcontroller |
文件: | 总88页 (文件大小:1165K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power 32-bit AVR® Microcontroller
– Compact Single-Cycle RISC Instruction Set Including DSP Instructions
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performance
• Up to 64 DMIPS Running at 50MHz from Flash (1 Flash Wait State)
• Up to 36 DMIPS Running at 25MHz from Flash (0 Flash Wait State)
– Memory Protection Unit (MPU)
• Secure Access Unit (SAU) providing user defined peripheral protection
• picoPower® Technology for Ultra-Low Power Consumption
• Multi-Hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 12 Peripheral DMA Channels Improve Speed for Peripheral Communication
• Internal High-Speed Flash
32-bit AVR®
Microcontroller
– 64Kbytes, 32Kbytes, and 16Kbytes Versions
AT32UC3L064
AT32UC3L032
AT32UC3L016
– Single-Cycle Access up to 25MHz
– FlashVault™ Technology Allows Pre-programmed Secure Library Support for End
User Applications
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
• Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash)
• Interrupt Controller (INTC)
– Autovectored Low Latency Interrupt Service with Programmable Priority
• External Interrupt Controller (EIC)
• Peripheral Event System for Direct Peripheral to Peripheral Communication
• System Functions
Preliminary
Summary
– Power and Clock Manager
– SleepWalking™ Power Saving Control
– Internal System RC Oscillator (RCSYS)
– 32KHz Oscillator
– Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL)
• Windowed Watchdog Timer (WDT)
• Asynchronous Timer (AST) with Real-Time Clock Capability
– Counter or Calendar Mode Supported
• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
• Six 16-bit Timer/Counter (TC) Channels
– External Clock Inputs, PWM, Capture and Various Counting Capabilities
• PWM Channels on All I/O Pins (PWMA)
– 8-bit PWM up to 150MHz Source Clock
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independent Baudrate Generator, Support for SPI
– Support for Hardware Handshaking
• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
– Up to 15 SPI Slaves can be Addressed
• Two Master and Two Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible
• One 8-channel Analog-To-Digital Converter (ADC) with up to 12 Bits Resolution
– Internal Temperature Sensor
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• Eight Analog Comparators (AC) with Optional Window Detection
• Capacitive Touch (CAT) Module
– Hardware Assisted QTouch® and QMatrix® Touch Acquisition
– Supports QTouch® and QMatrix® Capture from Capacitive Touch Sensors
• QTouch® Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch® and QMatrix® Acquisition
• On-Chip Non-Intrusive Debug System
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
– aWire™ Single-Pin Programming Trace and Debug Interface Muxed with Reset Pin
– NanoTrace™ Provides Trace Capabilities through JTAG or aWire Interface
• 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)
• Five High-Drive I/O Pins
• Single 1.62-3.6V Power Supply
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1. Description
The AT32UC3L is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density, and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. The Secure
Access Unit (SAU) is used together with the MPU to provide the required security and integrity.
Higher computation capability is achieved using a rich set of DSP instructions.
The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption.
Combined power control techniques are used to bring active current consumption down to
165µA/MHz, and leakage down to 9nA while still retaining a bank of backup registers. The
device allows a wide range of trade-offs between functionality and power consumption, giving
the user the ability to reach the lowest possible power consumption with the feature set required
for the application.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access.
The FlashVault technology allows secure libraries to be programmed into the device. The secure
libraries can be executed while the CPU is in Secure State, but not read by non-secure software
in the device. The device can thus be shipped to end costumers, who will be able to program
their own code into the device, accessing the secure libraries, but without risk of compromising
the proprietary secure code.
The Peripheral Event System allows peripherals to receive, react to, and send peripheral events
without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low
power sleep modes.
The Power Manager improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-On Reset (POR), Brown-Out Detector (BOD), and Supply Monitor (SM). The
device features several oscillators, such as Digital Frequency Locked Loop (DFLL), Oscillator 0
(OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source
for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can
be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter mode or calendar mode.
The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it
to a known reference clock.
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The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be syn-
chronized and controlled from a common timer. One PWM channel is available for each I/O pin
on the device, enabling applications that require multiple PWM outputs, such as LCD backlight
control. The PWM channels can operate independently, with duty cycles set independently from
each other, or in interlinked mode, with multiple channels changed at the same time.
The AT32UC3L also features many communication interfaces for communication intensive
applications like USART, SPI, or TWI.
A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The
ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering
up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel.
The analog comparators can be paired to detect when the sensing voltage is within or outside
the defined reference window.
The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using
the QTouch technology. Capacitive touch sensors use no external mechanical components,
unlike normal push buttons, and therefore demand less maintenance in the user application.
The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced.
One touch sensor can be configured to operate autonomously without software interaction,
allowing wakeup from sleep modes when activated.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.
The AT32UC3L integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intru-
sive real-time trace, full-speed read/write memory access, in addition to basic runtime control.
The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The sin-
gle-pin aWire interface allows all features available through the JTAG interface to be accessed
through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals.
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2. Overview
2.1
Block Diagram
Figure 2-1. Block Diagram
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
LOCAL BUS
LOCAL BUS
INTERFACE
AVR32UC CPU
EVTO_N
NEXUS
CLASS 2+
OCD
TCK
MEMORY PROTECTION UNIT
JTAG
TDO
16/8 KB
SRAM
TDI
TMS
INTERFACE
INSTR
DATA
INTERFACE
INTERFACE
DATAOUT
aWire
RESET_N
M
M
M
S
64/32/16 KB
FLASH
HIGH SPEED
BUS MATRIX
S/M
SAU
S
M
S
S
CONFIGURATION
REGISTERS BUS
PERIPHERAL
DMA
HSB-PB
HSB-PB
BRIDGE A
BRIDGE B
CONTROLLER
CSA[16:0]
CSB[16:0]
POWER MANAGER
CAPACITIVE TOUCH
MODULE
CLOCK
SMP
SYNC
PA
PB
CONTROLLER
SLEEP
USART0
USART1
USART2
USART3
CONTROLLER
RXD
TXD
CLK
RESET
RTS, CTS
CONTROLLER
SCK
MISO, MOSI
GCLK[4..0]
SPI
NPCS[3..0]
RCSYS
RC32K
RC120M
OSC32K
OSC0
TWCK
PA
PB
TWI MASTER 0
TWI MASTER 1
TWD
SYSTEM CONTROL
INTERFACE
XIN32
TWALM
XOUT32
XIN0
XOUT0
TWCK
TWI SLAVE 0
TWI SLAVE 1
TWD
DFLL
TWALM
BOD
INTERRUPT
AD[8..0]
8-CHANNEL ADC
INTERFACE
CONTROLLER
ADVREFP
EXTINT[5..1]
NMI
EXTERNAL INTERRUPT
CONTROLLER
A[2..0]
B[2..0]
TIMER/COUNTER 0
TIMER/COUNTER 1
PWM[35..0]
PWM CONTROLLER
CLK[2..0]
ASYNCHRONOUS
TIMER
ACBP[3..0]
ACBN[3..0]
ACAP[3..0]
ACAN[3..0]
ACREFN
AC INTERFACE
WATCHDOG
TIMER
FREQUENCY METER
OUT[1:0]
IN[7..0]
GLUE LOGIC
CONTROLLER
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2.2
Configuration Summary
Table 2-1.
Feature
Configuration Summary
AT32UC3L064
AT32UC3L032
AT32UC3L016
16KB
Flash
64KB
16KB
32KB
SRAM
16KB
36
5
8KB
GPIO
High-drive pins
External Interrupts
TWI
6
2
USART
4
Peripheral DMA Channels
12
1
Peripheral Event System
SPI
1
Asynchronous Timers
Timer/Counter Channels
PWM channels
1
6
36
1
Frequency Meter
Watchdog Timer
Power Manager
1
1
Secure Access Unit
Glue Logic Controller
1
1
Digital Frequency Locked Loop 40-150 MHz (DFLL)
Crystal Oscillator 3-16 MHz (OSC0)
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 120MHz (RC120M)
RC Oscillator 115 kHz (RCSYS)
Oscillators
RC Oscillator 32 kHz (RC32K)
ADC
8-channel 12-bit
Temperature Sensor
Analog Comparators
Capacitive Touch Module
JTAG
1
8
1
1
aWire
1
Max Frequency
Package
50 MHz
TQFP48/QFN48/TLLGA48
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3. Package and Pinout
3.1
Package
The device pins are multiplexed with peripheral functions as described in Section 3.2.
Figure 3-1. TQFP48/QFN48 Pinout
PA15
PA16
PA17
PA19
PA18
VDDIO
GND
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PA21
PB10
RESET_N
PB04
PB05
GND
VDDCORE
VDDIN
PB01
PB11
GND
PA10
PA12
VDDIO
PA07
PA01
PA02
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Figure 3-2. TLLGA48 Pinout
24
23
22
21
20
19
18
17
16
15
14
PA21
PA16
PA17
PA19
PA18
VDDIO
GND
38
39
40
41
42
43
44
45
46
47
48
PB10
RESET_N
PB04
PB05
GND
VDDCORE
VDDIN
PB01
PB11
GND
PA10
PA12
VDDIO
PA07
PA01
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3.2
Peripheral Multiplexing on I/O lines
3.2.1
Multiplexed signals
Each GPIO line can be assigned to one of the peripheral functions.The following table describes
the peripheral signals multiplexed to the GPIO lines.
Table 3-1.
GPIO Controller Function Multiplexing
Q
F
P
GPIO Function
G
PI
O
Pad
Type
48
PIN
Supply
A
B
C
D
E
F
G
H
Normal
I/O
USART0-
TXD
USART1-
RTS
SPI-
NPCS[2]
PWMA-
PWMA[0]
SCIF-
GCLK[0]
11
PA00
0
1
2
3
4
VDDIO
CAT-CSA[2]
Normal
I/O
USART0-
RXD
USART1-
CTS
SPI-
NPCS[3]
USART1-
CLK
PWMA-
PWMA[1]
ACIFB-
ACAP[0]
TWIMS0-
TWALM
14
13
4
PA01
PA02
PA03
PA04
VDDIO
VDDIO
VDDIO
VDDIO
CAT-CSA[1]
CAT-CSA[3]
CAT-CSB[3]
CAT-CSA[7]
High-
drive I/O
USART0-
RTS
ADCIFB-
TRIGGER
USART2-
TXD
PWMA-
PWMA[2]
ACIFB-
ACBP[0]
USART0-
CLK
TC0-A0
TC0-B0
TC0-B1
Normal
I/O
USART0-
CTS
SPI-
NPCS[1]
USART2-
TXD
PWMA-
PWMA[3]
ACIFB-
ACBN[3]
USART0-
CLK
Normal
I/O
TWIMS0-
TWCK
USART1-
RXD
PWMA-
PWMA[4]
ACIFB-
ACBP[1]
28
SPI-MISO
SPI-MOSI
TWI,
Normal
I/O
TWIMS1-
TWCK
USART1-
TXD
PWMA-
PWMA[5]
ACIFB-
ACBN[0]
TWIMS0-
TWD
12
10
15
PA05
PA06
PA07
5
6
7
VDDIO
VDDIO
VDDIO
TC0-A1
TC0-B0
CAT-CSB[7]
CAT-CSB[1]
CAT-CSB[2]
High-
drive I/O,
5V
USART2-
TXD
USART1-
CLK
PWMA-
PWMA[6]
SCIF-
GCLK[1]
SPI-SCK
tolerant
TWI,
Normal
I/O
SPI-
NPCS[0]
USART2-
RXD
TWIMS1-
TWALM
TWIMS0-
TWCK
PWMA-
PWMA[7]
ACIFB-
ACAN[0]
NMI
High-
drive I/O
USART1-
TXD
SPI-
NPCS[2]
ADCIFB-
ADP[0]
PWMA-
PWMA[8]
3
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
PA16
8
VDDIO
VDDIO
VDDIO
VDDIN
VDDIO
VDDIN
VDDIO
VDDIO
VDDIO
TC0-A2
TC0-B2
TC0-A0
CAT-CSA[4]
CAT-CSB[4]
CAT-CSA[5]
High-
drive I/O
USART1-
RXD
SPI-
NPCS[3]
ADCIFB-
ADP[1]
PWMA-
PWMA[9]
EIC-
EXTINT[1]
2
9
SCIF-GCLK[2]
Normal
I/O
TWIMS0-
TWD
PWMA-
PWMA[10]
ACIFB-
ACAP[1]
SCIF-
GCLK[2]
46
27
47
26
36
37
38
10
11
12
13
14
15
16
Normal
I/O
PWMA-
PWMA[11]
Normal
I/O
ADCIFB-
PRND
USART2-
CLK
PWMA-
PWMA[12]
ACIFB-
ACAN[1]
SCIF-
GCLK[3]
TC0-CLK1
TC0-A0
CAT-SMP
CAT-CSB[5]
CAT-CSA[0]
CAT-CSA[6]
CAT-CSB[6]
CAT-CSA[8]
Normal
I/O
GLOC-
OUT[0]
SCIF-
GCLK[2]
PWMA-
PWMA[13]
EIC-
EXTINT[2]
GLOC-IN[7]
TC0-CLK2
TC0-CLK1
TC0-CLK0
CAT-SMP
Normal
I/O
ADCIFB-
AD[0]
USART2-
RTS
PWMA-
PWMA[14]
SCIF-
GCLK[4]
CAT-SMP
GLOC-IN[6]
GLOC-IN[5]
Normal
I/O
ADCIFB-
AD[1]
PWMA-
PWMA[15]
EIC-
EXTINT[3]
CAT-SYNC
Normal
I/O
ADCIFB-
AD[2]
PWMA-
PWMA[16]
ACIFB-
ACREFN
EIC-
EXTINT[4]
TWI,
Normal
I/O
USART2-
CTS
TWIMS1-
TWD
PWMA-
PWMA[17]
39
PA17
17
VDDIO
TC0-A1
CAT-SMP
CAT-DIS
CAT-CSB[8]
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Table 3-1.
GPIO Controller Function Multiplexing
Normal
I/O
ADCIFB-
AD[4]
PWMA-
PWMA[18]
EIC-
EXTINT[5]
41
40
25
PA18
18
19
20
VDDIO
VDDIO
VDDIN
TC0-B1
GLOC-IN[4]
CAT-SYNC
CAT-CSB[0]
Normal
I/O
ADCIFB-
AD[5]
TWIMS1-
TWALM
PWMA-
PWMA[19]
CAT-
CSA[10]
PA19
PA20
TC0-A2
TC0-A1
CAT-SYNC
Normal
I/O
USART2-
TXD
PWMA-
PWMA[20]
SCIF-
RC32OUT
CAT-
CSA[12]
GLOC-IN[3]
TWI, 5V
tolerant,
SMBus,
Normal
I/O
USART2-
RXD
TWIMS0-
TWD
ADCIFB-
TRIGGER
PWMA-
PWMA[21]
PWMA-
PWMAOD[21]
SCIF-
GCLK[0]
24
PA21
21
VDDIN
TC0-B1
TC0-B2
CAT-SMP
Normal
I/O
USART0-
CTS
USART2-
CLK
PWMA-
PWMA[22]
ACIFB-
ACBN[2]
CAT-
CSB[10]
9
6
PA22
PB00
PB01
PB02
PB03
22
32
33
34
35
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
CAT-SMP
TC0-A1
TC0-B1
TC0-A2
TC0-B2
Normal
I/O
USART3-
TXD
ADCIFB-
ADP[0]
SPI-
NPCS[0]
PWMA-
PWMA[23]
ACIFB-
ACAP[2]
TC1-A0
TC1-A1
CAT-CSA[9]
CAT-CSB[9]
High-
drive I/O
USART3-
RXD
ADCIFB-
ADP[1]
PWMA-
PWMA[24]
16
7
SPI-SCK
SPI-MISO
SPI-MOSI
Normal
I/O
USART3-
RTS
USART3-
CLK
PWMA-
PWMA[25]
ACIFB-
ACAN[2]
SCIF-
GCLK[1]
CAT-
CSB[11]
Normal
I/O
USART3-
CTS
USART3-
CLK
PWMA-
PWMA[26]
ACIFB-
ACBP[2]
CAT-
CSA[11]
8
TC1-A2
TWI, 5V
tolerant,
SMBus,
Normal
I/O
USART1-
RTS
USART1-
CLK
TWIMS0-
TWALM
PWMA-
PWMA[27]
PWMA-
PWMAOD[27]
TWIMS1-
TWCK
CAT-
CSA[14]
21
20
PB04
PB05
36
37
VDDIN
VDDIN
TC1-A0
TC1-B0
TWI, 5V
tolerant,
SMBus,
Normal
I/O
USART1-
CTS
USART1-
CLK
TWIMS0-
TWCK
PWMA-
PWMA[28]
PWMA-
PWMAOD[28]
SCIF-
GCLK[3]
CAT-
CSB[14]
Normal
I/O
USART3-
TXD
ADCIFB-
AD[6]
PWMA-
PWMA[29]
ACIFB-
ACAN[3]
CAT-
CSB[13]
30
31
32
29
23
44
5
PB06
PB07
PB08
PB09
PB10
PB11
PB12
38
39
40
41
42
43
44
VDDIO
VDDIO
VDDIO
VDDIO
VDDIN
VDDIO
VDDIO
TC1-A1
TC1-B1
GLOC-IN[2]
GLOC-IN[1]
GLOC-IN[0]
NMI
Normal
I/O
USART3-
RXD
ADCIFB-
AD[7]
PWMA-
PWMA[30]
ACIFB-
ACAP[3]
EIC-
EXTINT[1]
CAT-
CSA[13]
Normal
I/O
USART3-
RTS
ADCIFB-
AD[8]
PWMA-
PWMA[31]
EIC-
EXTINT[2]
CAT-
CSB[12]
TC1-A2
CAT-SYNC
Normal
I/O
USART3-
CTS
USART3-
CLK
PWMA-
PWMA[32]
ACIFB-
ACBN[1]
EIC-
EXTINT[3]
CAT-
CSB[15]
TC1-B2
Normal
I/O
USART1-
TXD
USART3-
CLK
GLOC-
OUT[1]
PWMA-
PWMA[33]
EIC-
EXTINT[4]
CAT-
CSB[16]
TC1-CLK0
TC1-CLK1
TC1-CLK2
Normal
I/O
USART1-
RXD
ADCIFB-
TRIGGER
PWMA-
PWMA[34]
EIC-
EXTINT[5]
CAT-
CSA[16]
CAT-VDIVEN
Normal
I/O
TWIMS1-
TWALM
PWMA-
PWMA[35]
ACIFB-
ACBP[3]
SCIF-
GCLK[4]
CAT-
CSA[15]
CAT-SYNC
See Section 3.3 for a description of the various peripheral signals.
Signals are prioritized according to the function priority listed in Table 3-2 on page 11 if multiple
functions are enabled simultaneously.
Refer to ”Electrical Characteristics” on page 41 for a description of the electrical properties of the
pad types used.
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3.2.2
Peripheral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions are enabled.
Table 3-2.
Peripheral Functions
Function
Description
A
B
C
D
E
F
GPIO peripheral selection A
GPIO peripheral selection B
GPIO peripheral selection C
GPIO peripheral selection D
GPIO peripheral selection E
GPIO peripheral selection F
GPIO peripheral selection G
GPIO peripheral selection H
G
H
3.2.3
JTAG Port Connections
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
Table 3-3.
JTAG Pinout
48TQFP/QFN/TLLGA
Pin
JTAG Function
11
14
13
4
PA00
PA01
PA02
PA03
TCK
TMS
TDO
TDI
3.2.4
Nexus OCD AUX Port Connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the I/O Controller configuration. Two different OCD trace pin mappings are
possible, depending on the configuration of the OCD AXS register. For details, see the AVR32
UC Technical Reference Manual.
Table 3-4.
Pin
Nexus OCD AUX Port Connections
AXS=1
PA05
PA10
PA18
PA17
AXS=0
PB08
PB00
PB04
PB05
EVTI_N
MDO[5]
MDO[4]
MDO[3]
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Table 3-4.
Pin
Nexus OCD AUX Port Connections
AXS=1
PA16
PA15
PA14
PA04
PA06
PA07
PA11
AXS=0
PB03
PB02
PB09
PA04
PB01
PB11
PB12
MDO[2]
MDO[1]
MDO[0]
EVTO_N
MCKO
MSEO[1]
MSEO[0]
3.2.5
Oscillator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more
information about this.
Table 3-5.
Oscillator Pinout
48TQFP/QFN/TLLGA
Pin
Oscillator Function
XIN0
3
PA08
PA10
PA13
PA09
PA12
PA20
46
26
2
XIN32
XIN32_2
XOUT0
47
25
XOUT32
XOUT32_2
3.2.6
Other Functions
The functions listed in Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA
pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be actice
after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is
always enabled. Please refer to Section 6.1.4 on page 40 for constraints on the WAKE_N pin.
Table 3-6.
Other Functions
48TQFP/TQFN/TLLGA
Pin
PA11
Function
WAKE_N
27
22
11
RESET_N
PA00
aWire DATA
aWire DATAOUT
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3.3
Signal Descriptions
The following table gives details on signal name classified by peripheral.
Table 3-7.
Signal Descriptions List
Function
Active
Level
Signal Name
Type
Comments
Analog Comparator Interface - ACIFB
ACAN3 - ACAN0
ACAP3 - ACAP0
ACBN3 - ACBN0
ACBP3 - ACBP0
ACREFN
Negative inputs for comparators "A"
Positive inputs for comparators "A"
Negative inputs for comparators "B"
Positive inputs for comparators "B"
Common negative reference
Analog
Analog
Analog
Analog
Analog
ADC Interface - ADCIFB
AD8 - AD0
ADP1 - ADP0
PRND
Analog Signal
Analog
Output
Output
Input
Drive Pin for resistive touch screen
Pseudorandom output signal
External trigger
TRIGGER
aWire - AW
DATA
aWire data
I/O
I/O
DATAOUT
aWire data output for 2-pin mode
Capacitive Touch Module - CAT
CSA16 - CSA0
CSB16 - CSB0
SMP
Capacitive Sense A
Capacitive Sense B
SMP signal
I/O
I/O
Output
SYNC
Synchronize signal
Voltage divider enable
Input
Output
VDIVEN
External Interrupt Controller - EIC
NMI
Non-Maskable Interrupt
External interrupt
Input
EXTINT5 - EXTINT1
Input
Glue Logic Controller - GLOC
Input
IN7 - IN0
Inputs to lookup tables
OUT1 - OUT0
Outputs from lookup tables
Output
JTAG module - JTAG
TCK
TDI
Test Clock
Input
Input
Test Data In
TDO
TMS
Test Data Out
Test Mode Select
Output
Input
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Table 3-7.
Signal Descriptions List
Reset
Power Manager - PM
Input
Pulse Width Modulation Controller - PWMA
RESET_N
Low
PWMA35 - PWMA0
PWMA channel waveforms
Output
Output
PWMAOD35 -
PWMAOD0
PWMA channel waveforms, open drain
mode
Not all channels support open
drain mode
System Control Interface - SCIF
GCLK4 - GCLK0
RC32OUT
Generic Clock Output
Output
RC32K output at startup
Crystal 0 Input
Output
Analog/
Digital
XIN0
Analog/
Digital
XIN32
XIN32_2
Crystal 32 Input (primary location)
Crystal 32 Input (secondary location)
Analog/
Digital
XOUT0
Crystal 0 Output
Analog
Analog
Analog
XOUT32
XOUT32_2
Crystal 32 Output (primary location)
Crystal 32 Output (secondary location)
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
Master Out Slave In
I/O
I/O
MOSI
NPCS3 - NPCS0
SCK
SPI Peripheral Chip Select
Clock
I/O
Low
I/O
Timer/Counter - TC0, TC1
A0
Channel 0 Line A
Channel 1 Line A
Channel 2 Line A
Channel 0 Line B
Channel 1 Line B
Channel 2 Line B
I/O
I/O
I/O
I/O
I/O
I/O
A1
A2
B0
B1
B2
CLK0
CLK1
CLK2
Channel 0 External Clock Input
Channel 1 External Clock Input
Channel 2 External Clock Input
Input
Input
Input
Two-wire Interface - TWIMS0, TWIMS1
TWALM
TWCK
TWD
SMBus SMBALERT
I/O
I/O
I/O
Low
Two-wire Serial Clock
Two-wire Serial Data
Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3
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Table 3-7.
CLK
Signal Descriptions List
Clock
I/O
CTS
Clear To Send
Request To Send
Receive Data
Input
Low
RTS
Output
Input
Low
RXD
TXD
Transmit Data
Output
Note:
1. ADCIFB: AD3 does not exist.
Table 3-8.
Signal Description List, continued
Active
Level
Signal Name
Function
Type
Comments
Power
Power
Input/Output
VDDCORE
VDDIO
Core Power Supply / Voltage Regulator Output
I/O Power Supply
1.62V to 1.98V
1.62V to 3.6V. VDDIO should
always be equal to or lower than
VDDIN.
Power Input
VDDANA
ADVREFP
VDDIN
Analog Power Supply
Analog Reference Voltage
Voltage Regulator Input
Analog Ground
Power Input
Power Input
Power Input
Ground
1.62V to 1.98V
TBD to 1.98V
1.62V to 3.6V (1)
GNDANA
GND
Ground
Ground
Auxiliary Port - AUX
MCKO
Trace Data Output Clock
Trace Data Output
Trace Frame Control
Event In
Output
Output
Output
Input
MDO5 - MDO0
MSEO1 - MSEO0
EVTI_N
Low
Low
EVTO_N
Event Out
Output
General Purpose I/O pin
PA22 - PA00
PB12 - PB00
Parallel I/O Controller I/O Port 0
Parallel I/O Controller I/O Port 1
I/O
I/O
1.
See Section 6.1 on page 36
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3.4
I/O Line Considerations
3.4.1
JTAG Pins
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. The TCK pin always have pull-up enabled
during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG
pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.
Please refer to Section 3.2.3 on page 11 for the JTAG port connections.
3.4.2
3.4.3
PA00
Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the
application.
RESET_N Pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
3.4.4
TWI0 Pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the characteristics indicated in the Electrical Characteristics section. Selected pins are also
SMBus compliant (refer to Section 3.2 on page 9). As required by the SMBus specification,
these pins provide no leakage path to ground when the AT32UC3L is powered down. This
allows other devices on the SMBus to continue communicating even though the AT32UC3L is
not powered. This feature is only available when pins PA21/PB04/PB05 are used for TWI0.
3.4.5
3.4.6
TWI1 Pins
GPIO Pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins.
All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed
independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as
inputs with pull-up resistors disabled, except PA00. PA20 selects SCIF-RC32OUT (GPIO Func-
tion F) as default enabled after reset.
3.4.7
High-Drive Pins
The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to
Section 7. on page 41 for electrical characteristics.
3.4.8
RC32OUT Pin
3.4.8.1
Clock output at startup
After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20,
even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by
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the system to start other devices or to clock a switching regulator to rise the power supply volt-
age up to an acceptable value.
The clock will be available on PA20 until one of the following conditions are true:
•PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT)
•PA20 is configured as a General Purpose Input/Output (GPIO)
•The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power
Manager chapter)
The maximum amplitude of the clock signal will be defined by VDDIN.
3.4.8.2
XOUT32_2 function
PA20 selects RC32OUT as default enabled after reset. This function is not automatically dis-
abled when the user enables the XOUT32_2 function on PA20. This disturbes the oscillator and
may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2
is enabled.
3.4.9
ADC Input Pins
These pins are regular I/O pins powered from the VDDIO. However, when these pins are used
for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures
that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins
are not used for ADC inputs, the pins may be driven to the full I/O voltage range.
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4. Processor and Architecture
Rev: 2.1.0.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
4.1
Features
• 32-bit load/store AVR32A RISC architecture
– 15 general-purpose 32-bit registers
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file
– Fully orthogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure operating systems
– Innovative instruction set together with variable instruction length ensuring industry leading
code density
– DSP extension with saturating arithmetic, and a wide variety of multiply instructions
• 3-stage pipeline allowing one instruction per clock cycle for most instructions
– Byte, halfword, word, and double word memory access
– Multiple interrupt priority levels
• MPU allows for operating systems with memory protection
• Secure State for supporting FlashVaultTM technology
4.2
AVR32 Architecture
AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-
sensitive embedded applications, with particular emphasis on low power consumption and high
code density. In addition, the instruction set architecture has been tuned to allow a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core’s low power characteris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
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The register file is organized as sixteen 32-bit registers and includes the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
4.3
The AVR32UC CPU
The AVR32UC CPU targets low- and medium-performance applications, and provides an
advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU).
Java acceleration hardware is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.
Also, power consumption is reduced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a
one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data
between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated
memory range allocated to it, and data transfers are performed using regular load and store
instructions. Details on which devices that are mapped into the local bus space is given in the
CPU Local Bus section in the Memories chapter.
Figure 4-1 on page 20 displays the contents of AVR32UC.
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Figure 4-1. Overview of the AVR32UC CPU
Power/
Reset
OCD
system
control
AVR32UC CPU pipeline
MPU
Data memory controller
Instruction memory controller
High Speed Bus master
High
Speed
Bus
High
Speed
CPU Local
Bus
CPU RAM
Bus slave
master
master
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages.
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Figure 4-2. The AVR32UC Pipeline
MUL
Multiply unit
ALU unit
Regfile
Read
Regfile
write
IF
ID
ALU
LS
Prefetch unit
Decode unit
Load-store
unit
4.3.2
AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers and return status registers. Instead, all this information is stored on the system
stack. This saves chip area at the expense of slower interrupt handling.
4.3.2.1
Interrupt Handling
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.
4.3.2.2
4.3.2.3
Java Support
AVR32UC does not provide Java hardware acceleration.
Memory Protection
The MPU allows the user to check all memory accesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
4.3.2.4
Unaligned Reference Handling
AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
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address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
Table 4-1.
Instruction
ld.d
Instructions with Unaligned Reference Support
Supported Alignment
Word
Word
st.d
4.3.2.5
Unimplemented Instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
• All SIMD instructions
• All coprocessor instructions if no coprocessors are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
4.3.2.6
CPU and Architecture Revision
Three major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 3.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
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4.4
Programming Model
4.4.1
Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3. The AVR32UC Register File
Supervisor
INT0
Bit 31
INT1
Bit 31
INT2
Bit 31
INT3
Bit 31
Exception
NMI
Secure
Bit 31
Application
Bit 31
Bit 0
Bit 31
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 31
Bit 0
Bit 31
Bit 0
Bit 0
PC
LR
SP_APP
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SYS
R12
PC
LR
SP_SEC
R12
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R11
R10
R9
R8
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R7
R6
R5
R4
R3
R2
R2
R2
R2
R2
R2
R2
R2
R2
R1
R1
R1
R1
R1
R1
R1
R1
R1
R0
R0
R0
R0
R0
R0
R0
R0
R0
SR
SR
SR
SR
SR
SR
SR
SR
SR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
4.4.2
Status Register Configuration
The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4
and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,
and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4. The Status Register High Halfword
Bit 31
Bit 16
-
SS
-
-
DM
0
D
0
-
M2
0
M1
0
M0
1
EM
1
I3M I2M I1M I0M GM
Bit name
0
0
0
0
0
0
0
0
0
1
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Secure State
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Figure 4-5. The Status Register Low Halfword
Bit 15
Bit 0
-
T
0
-
-
-
-
-
-
-
-
L
0
Q
0
V
0
N
0
Z
0
C
0
Bit name
0
0
0
0
0
0
0
0
0
Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
4.4.3
Processor States
4.4.3.1
Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2.
Table 4-2.
Overview of Execution Modes, their Priorities and Privilege Levels.
Priority
Mode
Security
Description
1
Non Maskable Interrupt
Exception
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Unprivileged
Non Maskable high priority interrupt mode
Execute exceptions
2
3
Interrupt 3
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
Runs supervisor calls
4
Interrupt 2
5
Interrupt 1
6
Interrupt 0
N/A
N/A
Supervisor
Application
Normal program execution mode
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
4.4.3.2
Debug State
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
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Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
4.4.3.3
Secure State
The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with
higher security levels. The rest of the code can not access resources reserved for this secure
code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Techni-
cal Reference Manual for details.
4.4.4
System Registers
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 4-3.
System Registers
Reg #
0
Address
0
Name
Function
SR
Status Register
1
4
EVBA
Exception Vector Base Address
Application Call Base Address
CPU Control Register
Exception Cause Register
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Return Status Register for Debug mode
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
Return Address Register for Debug mode
Unused in AVR32UC
Unused in AVR32UC
Unused in AVR32UC
2
8
ACBA
3
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
CPUCR
4
ECR
5
RSR_SUP
RSR_INT0
RSR_INT1
RSR_INT2
RSR_INT3
RSR_EX
RSR_NMI
RSR_DBG
RAR_SUP
RAR_INT0
RAR_INT1
RAR_INT2
RAR_INT3
RAR_EX
RAR_NMI
RAR_DBG
JECR
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
JOSP
JAVA_LV0
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Table 4-3.
Reg #
24
System Registers (Continued)
Address
96
Name
Function
JAVA_LV1
JAVA_LV2
JAVA_LV3
JAVA_LV4
JAVA_LV5
JAVA_LV6
JAVA_LV7
JTBA
Unused in AVR32UC
25
100
104
108
112
116
120
124
128
132-252
256
260
264
268
272
276
280
284
288
292
296
300
304
308
312
316
320
324
328
332
336
340
344
348
352
356
Unused in AVR32UC
26
Unused in AVR32UC
27
Unused in AVR32UC
28
Unused in AVR32UC
29
Unused in AVR32UC
30
Unused in AVR32UC
31
Unused in AVR32UC
32
JBCR
Unused in AVR32UC
33-63
64
Reserved
CONFIG0
CONFIG1
COUNT
Reserved for future use
Configuration register 0
Configuration register 1
Cycle Counter register
65
66
67
COMPARE
TLBEHI
Compare register
68
Unused in AVR32UC
69
TLBELO
PTBR
Unused in AVR32UC
70
Unused in AVR32UC
71
TLBEAR
MMUCR
TLBARLO
TLBARHI
PCCNT
Unused in AVR32UC
72
Unused in AVR32UC
73
Unused in AVR32UC
74
Unused in AVR32UC
75
Unused in AVR32UC
76
PCNT0
Unused in AVR32UC
77
PCNT1
Unused in AVR32UC
78
PCCR
Unused in AVR32UC
79
BEAR
Bus Error Address Register
MPU Address Register region 0
MPU Address Register region 1
MPU Address Register region 2
MPU Address Register region 3
MPU Address Register region 4
MPU Address Register region 5
MPU Address Register region 6
MPU Address Register region 7
MPU Privilege Select Register region 0
MPU Privilege Select Register region 1
80
MPUAR0
MPUAR1
MPUAR2
MPUAR3
MPUAR4
MPUAR5
MPUAR6
MPUAR7
MPUPSR0
MPUPSR1
81
82
83
84
85
86
87
88
89
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Table 4-3.
Reg #
90
System Registers (Continued)
Address
360
Name
Function
MPUPSR2
MPUPSR3
MPUPSR4
MPUPSR5
MPUPSR6
MPUPSR7
MPUCRA
MPUCRB
MPUBRA
MPUBRB
MPUAPRA
MPUAPRB
MPUCR
MPU Privilege Select Register region 2
MPU Privilege Select Register region 3
MPU Privilege Select Register region 4
MPU Privilege Select Register region 5
MPU Privilege Select Register region 6
MPU Privilege Select Register region 7
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
MPU Access Permission Register A
MPU Access Permission Register B
MPU Control Register
91
364
92
368
93
372
94
376
95
380
96
384
97
388
98
392
99
396
100
101
102
103
104
105
106
107
108
109
110
111
112-191
192-255
400
404
408
412
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
Secure State Status Register
416
Secure State Address Flash Register
Secure State Address RAM Register
Secure State Address 0 Register
Secure State Address 1 Register
Secure State Stack Pointer System Register
Secure State Stack Pointer Application Register
Secure State Return Address Register
Secure State Return Status Register
Reserved for future use
420
424
428
432
436
440
444
SS_RSR
448-764
768-1020
Reserved
IMPL
IMPLEMENTATION DEFINED
4.5
Exceptions and Interrupts
In the AVR32 architecture, events are used as a common term for exceptions and interrupts.
AVR32UC incorporates a powerful event handling scheme. The different event sources, like Ille-
gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined
behavior when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execution is passed
to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are
placed sequentially in the code space starting at the address specified by EVBA, with four bytes
between each handler. This gives ample space for a jump instruction to be placed there, jump-
ing to the event routine itself. A few critical handlers have larger spacing between them, allowing
the entire event routine to be placed directly at the address specified by the EVBA-relative offset
generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR)
addresses. This allows the interrupt controller to directly specify the ISR address as an address
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relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384
bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),
not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up
appropriately. The same mechanisms are used to service all different types of events, including
interrupt requests, yielding a uniform event handling scheme.
An interrupt controller does the priority handling of the interrupts and provides the autovector off-
set to the CPU.
4.5.1
System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
4.5.2
Exceptions and Interrupt Requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status
Register ensures that the core is returned to the previous execution mode when the
current event handling is completed. When exceptions occur, both the EM and GM bits
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address uniquely identifies the exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown in Table 4-4 on
page 31, is loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
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4.5.3
4.5.4
4.5.5
Supervisor Calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
Debug Requests
The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the
Debug Exception handler. By default, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to the previous context.
Entry Points for Events
Several different event handler entry points exist. In AVR32UC, the reset address is
0x80000000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All interrupt requests have entry points located at an offset relative to EVBA. This autovector off-
set is specified by an interrupt controller. The programmer must make sure that none of the
autovector offsets interfere with the placement of other code. The autovector offset has 14
address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on the same instruction, they are handled in a prioritized way. The priority
ordering is presented in Table 4-4 on page 31. If events occur on several instructions at different
locations in the pipeline, the events on the oldest instruction are always handled before any
events on any younger instruction, even if the younger instruction has events of higher priority
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than the oldest instruction. An instruction B is younger than an instruction A if it was sent down
the pipeline later than A.
The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of
the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-
point unit.
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Table 4-4.
Priority and Handler Addresses for Events
Priority
1
Handler Address
0x80000000
Provided by OCD system
EVBA+0x00
EVBA+0x04
EVBA+0x08
EVBA+0x0C
EVBA+0x10
Autovectored
Autovectored
Autovectored
Autovectored
EVBA+0x14
EVBA+0x50
EVBA+0x18
EVBA+0x1C
EVBA+0x20
EVBA+0x24
EVBA+0x28
EVBA+0x2C
EVBA+0x30
EVBA+0x100
EVBA+0x34
EVBA+0x38
EVBA+0x60
EVBA+0x70
EVBA+0x3C
EVBA+0x40
EVBA+0x44
Name
Event source
External input
OCD system
Internal
Stored Return Address
Reset
Undefined
2
OCD Stop CPU
Unrecoverable exception
TLB multiple hit
First non-completed instruction
PC of offending instruction
PC of offending instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
3
4
MPU
5
Bus error data fetch
Bus error instruction fetch
NMI
Data bus
Data bus
External input
External input
External input
External input
External input
CPU
6
7
8
Interrupt 3 request
Interrupt 2 request
Interrupt 1 request
Interrupt 0 request
Instruction Address
ITLB Miss
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MPU
ITLB Protection
MPU
Breakpoint
OCD system
Instruction
Instruction
Instruction
UNUSED
Instruction
Instruction
CPU
Illegal Opcode
Unimplemented instruction
Privilege violation
Floating-point
Coprocessor absent
Supervisor call
PC of offending instruction
PC(Supervisor Call) +2
Data Address (Read)
Data Address (Write)
DTLB Miss (Read)
DTLB Miss (Write)
DTLB Protection (Read)
DTLB Protection (Write)
DTLB Modified
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
CPU
MPU
MPU
MPU
MPU
UNUSED
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5. Memories
5.1
Embedded Memories
• Internal High-Speed Flash
– 64Kbytes (AT32UC3L064)
– 32Kbytes (AT32UC3L032)
– 16Kbytes (AT32UC3L016)
• 0 Wait State Access at up to 25MHz in Worst Case Conditions
• 1 Wait State Access at up to 50MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
to only 8% compared to 0 wait state operation
• 100 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
• Internal High-Speed SRAM, Single-cycle access at full speed
– 16Kbytes (AT32UC3L064, AT32UC3L032)
– 8Kbytes (AT32UC3L016)
5.2
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1.
AT32UC3L Physical Memory Map
Size
Start Address
Device
AT32UC3L064
AT32UC3L032
16Kbytes
32Kbytes
64Kbytes
64Kbytes
AT32UC3L016
8Kbytes
Embedded SRAM
Embedded Flash
HSB-PB Bridge B
HSB-PB Bridge A
0x00000000
0x80000000
0xFFFE0000
0xFFFF0000
16Kbytes
64Kbytes
64Kbytes
64Kbytes
16Kbytes
64Kbytes
64Kbytes
Table 5-2.
Flash Memory Parameters
Number of pages
Page size
Part Number
AT32UC3L064
AT32UC3L032
AT32UC3L016
Flash Size (FLASH_PW)
64Kbytes
(FLASH_P)
(FLASH_W)
256 bytes
256 bytes
256 bytes
256
128
64
32Kbytes
16Kbytes
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5.3
Peripheral Address Map
Table 5-3.
Peripheral Address Mapping
Address
Peripheral Name
Bus
0xFFFE0000
FLASHCDW
Flash Controller - FLASHCDW
HSB Matrix - HMATRIX
0xFFFE0400
0xFFFE0800
0xFFFF0000
0xFFFF1000
0xFFFF1400
0xFFFF1800
0xFFFF1C00
0xFFFF2000
0xFFFF2400
0xFFFF2800
0xFFFF2C00
0xFFFF3000
0xFFFF3400
0xFFFF3800
0xFFFF3C00
0xFFFF4000
0xFFFF4400
HMATRIX
SAU
Secure Access Unit - SAU
PDCA
INTC
Peripheral DMA Controller - PDCA
Interrupt controller - INTC
PM
Power Manager - PM
SCIF
System Control Interface - SCIF
Asynchronous Timer - AST
Watchdog Timer - WDT
AST
WDT
EIC
External Interrupt Controller - EIC
Frequency Meter - FREQM
General Purpose Input/Output Controller - GPIO
FREQM
GPIO
Universal Synchronous/Asynchronous
Receiver/Transmitter - USART0
USART0
USART1
USART2
USART3
SPI
Universal Synchronous/Asynchronous
Receiver/Transmitter - USART1
Universal Synchronous/Asynchronous
Receiver/Transmitter - USART2
Universal Synchronous/Asynchronous
Receiver/Transmitter - USART3
Serial Peripheral Interface - SPI
TWIM0
Two-wire Master Interface - TWIM0
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Table 5-3.
Peripheral Address Mapping
0xFFFF4800
TWIM1
Two-wire Master Interface - TWIM1
0xFFFF4C00
0xFFFF5000
0xFFFF5400
0xFFFF5800
0xFFFF5C00
0xFFFF6000
0xFFFF6400
0xFFFF6800
0xFFFF6C00
0xFFFF7000
TWIS0
TWIS1
PWMA
TC0
Two-wire Slave Interface - TWIS0
Two-wire Slave Interface - TWIS1
Pulse Width Modulation Controller - PWMA
Timer/Counter - TC0
TC1
Timer/Counter - TC1
ADCIFB
ACIFB
CAT
ADC Interface - ADCIFB
Analog Comparator Interface - ACIFB
Capacitive Touch Module - CAT
Glue Logic Controller - GLOC
aWire - AW
GLOC
AW
5.4
CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
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The following GPIO registers are mapped on the local bus:
Table 5-4.
Local Bus Mapped GPIO Registers
Local Bus
Port
Register
Mode
WRITE
SET
Address
Access
0
Output Driver Enable Register (ODER)
Output Value Register (OVR)
0x40000040
0x40000044
0x40000048
0x4000004C
0x40000050
0x40000054
0x40000058
0x4000005C
0x40000060
0x40000240
0x40000244
0x40000248
0x4000024C
0x40000250
0x40000254
0x40000258
0x4000025C
0x40000260
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Read-only
CLEAR
TOGGLE
WRITE
SET
CLEAR
TOGGLE
-
Pin Value Register (PVR)
1
Output Driver Enable Register (ODER)
WRITE
SET
CLEAR
TOGGLE
WRITE
SET
Output Value Register (OVR)
Pin Value Register (PVR)
CLEAR
TOGGLE
-
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6. Supply and Startup Considerations
6.1
Supply Considerations
6.1.1
Power Supplies
The AT32UC3L has several types of power supply pins:
•VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal.
•VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal.
•VDDANA: Powers the ADC. Voltage is 1.8V nominal.
•VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDANA is
GNDANA.
Refer to Section 7. on page 41 for power consumption on the various supply pins.
6.1.2
Voltage Regulator
The AT32UC3L embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load
of up to 60 mA. The regulator supplies the output voltage on VDDCORE. The regulator may only
be used to drive internal circuitry in the device. VDDCORE should be externally connected to the
1.8V domains. See Section 6.1.3 for regulator connection figures.
Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid
oscillations. The best way to achieve this is to use two capacitors in parallell between
VDDCORE and GND as close to the chip as possible. Please refer to Section 7.9.1 on page 50
for decoupling capacitors values and regulator characteristics.
Figure 6-1. Supply Decoupling
3.3V
VDDIN
C
C
C
C
IN1
IN3
IN2
1.8V
Regulator
1.8V
VDDCORE
C
OUT2
OUT1
6.1.3
Regulator Connection
The AT32UC3L supports three power supply configurations:
• 3.3V single supply mode
• 1.8V single supply mode
• 3.3V supply mode, with 1.8V regulated I/O lines
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6.1.3.1
3.3V Single Supply Mode
In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin)
and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V sin-
gle supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO).
Figure 6-2. 3.3V Single Power Supply mode
+
1.98-3.6V
-
VDDIN
VDDIO
GND
I/O Pins
I/O Pins
OSC32K
RC32K
AST
Linear
VDDCORE
VDDANA
Wake
POR33
SM33
CPU,
Peripherals,
Memories,
SCIF, BOD,
RCSYS,
ADC
DFLL
GNDANA
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6.1.3.2
1.8V Single Supply Mode
In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are
powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the
same power (VDDIN = VDDIO = VDDCORE).
Figure 6-3. 1.8V Single Power Supply Mode.
+
1.62-1.98V
-
VDDIN
VDDIO
GND
I/O Pins
I/O Pins
OSC32K
RC32K
AST
Linear
VDDCORE
VDDANA
Wake
POR33
SM33
CPU,
Peripherals,
Memories,
SCIF, BOD,
RCSYS,
ADC
DFLL
GNDANA
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6.1.3.3
3.3V Supply Mode with 1.8V Regulated I/O Lines
In this mode, the internal regulator is connected to the 3.3V source and its output is connected
to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to
use Shutdown mode.
Figure 6-4. 3.3V Power with 1.8V Regulated I/O Lines
1.98-3.6V
+
VDDIN
VDDIO
GND
-
I/O Pins
I/O Pins
Linear
OSC32K
RC32K
AST
VDDCORE
Wake
POR33
SM33
CPU,
Peripherals,
Memories,
SCIF, BOD,
RCSYS,
VDDANA
ADC
DFLL
GNDANA
In this mode, some I/O lines are powered by VDDIN while others I/O lines are powered by
VDDIO. Refer to Section 3.2 on page 9 for description of power supply for each I/O line.
Refer to the Power Manager chapter for a description of what parts of the system are powered in
Shutdown mode.
Important note: As the regulator has a maximum output current of 60mA, this mode can only be
used in applications where the maximum I/O current is known and compatible with the core and
peripheral power consumption. Typically, great care must be used to ensure that only a few I/O
lines are toggling at the same time and drive very small loads.
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6.1.4
Power-up Sequence
6.1.4.1
Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 7-3 on page 42.
Recommended order for power supplies is also described in this chapter.
6.1.4.2
Minimum Rise Rate
The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a mini-
mum rise rate for the VDDIN power supply.
See Table 7-3 on page 42 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, one of the following configuration can be used:
• A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V.
• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
6.2
Startup Considerations
This chapter summarizes the boot sequence of the AT32UC3L. The behavior after power-up is
controlled by the Power Manager. For specific details, refer to the Power Manager chapter.
6.2.1
Starting of Clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a
short time to allow the power to stabilize throughout the device. After reset, the device will use
the System RC Oscillator (RCSYS) as clock source. Please refer to Table 7-17 on page 49 for
the frequency for this oscillator.
On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have
a divided frequency; all parts of the system receive a clock with the same frequency as the Sys-
tem RC Oscillator.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR threshold, and before the supply is stable. Before switching to a high-speed
clock source, the user should use the BOD to make sure the VDDCORE is above the minimum
level (1.62V).
6.2.2
Fetching of Initial Instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x80000000. This address points to the first address in the internal Flash.
The code read from the internal Flash is free to configure the system to use for example the
DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
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7. Electrical Characteristics
7.1
Disclaimer
All values in this chapter are preliminary and subject to change without further notice.
7.2
Absolute Maximum Ratings*
Table 7-1.
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional opera-
tion of the device at these or other condi-
tions beyond those indicated in the
operational sections of this specification is
not implied. Exposure to absolute maxi-
mum rating conditions for extended peri-
ods may affect device reliability.
Operating temperature..................................... -40°C to +85°C
Storage temperature...................................... -60°C to +150°C
Voltage on input pins (except for 5V pins) with respect to ground
.................................................................-0.3V to VVDD(2)+0.3V
Voltage on 5V tolerant(1) pins with respect to ground ...............
.............................................................................-0.3V to 5.5V
Total DC output current on all I/O pins - VDDIO ........... 120mA
Total DC output current on all I/O pins - VDDIN ............. 36mA
Maximum operating voltage VDDCORE......................... 1.98V
Maximum operating voltage VDDIO, VDDIN .................... 3.6V
Notes: 1. 5V tolerant pins, see Section 3.2 ”Peripheral Multiplexing on I/O lines” on page 9
2. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
7.3
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to
85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C.
Table 7-2.
Supply Characteristics(1)
Voltage
Max
Symbol
Parameter
Min
Unit
VVDDIO
DC supply peripheral I/Os
1.62
3.6
V
DC supply peripheral I/Os, 1.8V
single supply mode
1.62
1.98
1.98
3.6
V
V
VVDDIN
DC supply peripheral I/Os and
internal regulator, 3.3V single
supply mode
VVDDCORE
VVDDANA
VADVREFP
DC supply core
1.62
1.62
1.62
1.98
1.98
V
V
V
Analog supply voltage
Analog reference voltage
VVDDANA
Note:
1. VDDANA = VDDCORE
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Table 7-3.
Supply Rise Rates and Order
Rise Rate
Symbol
Parameter
Min
Max
Unit
Comment
VVDDIO
DC supply peripheral I/Os
0
2.5
V/µs
DC supply peripheral I/Os
and internal regulator
VVDDIN
0.002(1)
2.5
2.5
2.5
V/µs
V/µs
V/µs
Rise before or at the same
time as VDDIO
VVDDCORE
VVDDANA
Note:
DC supply core
0
0
Rise together with
VDDCORE
Analog supply voltage
1. Slower rise time requires external power-on reset circuit.
7.4
Maximum Clock Frequencies
These parameters are given in the following conditions:
• VVDDCORE = 1.62 to 1.98V
• Temperature = -40°C to 85°C
Table 7-4.
Symbol
fCPU
Clock Frequencies
Parameter
Conditions
Min
Max
50
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CPU clock frequency
PBA clock frequency
PBB clock frequency
GCLK0 clock frequency
GCLK1 clock frequency
GCLK2 clock frequency
GCLK3 clock frequency
GCLK4 clock frequency
GCLK5 clock frequency
fPBA
50
fPBB
50
fGCLK0
fGCLK1
fGCLK2
fGCLK3
fGCLK4
fGCLK5
150
150
80
110
110
80
7.5
Power Consumption
The values in Table 7-5 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions internal core supply (Figure 7-1) - this is the default configuration
– VVDDIN = 3.0V
– VVDDCORE = 1.62V
– TA = 25°C
• Operating conditions external core supply (Figure 7-2) - used only when noted
– VVDDIN = VVDDCORE = 1.8V
– TA = 25°C
• Oscillators
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– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– DFLL running at 50MHz with OSC32K as reference
• Clocks
– DFLL used as main clock source
– CPU, HSB, and PBB clocks undivided
– PBA clock divided by 4
– The following peripheral clocks running
• PM, SCIF, AST, FLASHCDW, PBA bridge
– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• Flash enabled in high speed mode
• POR33 disabled
Table 7-5.
Mode
Power Consumption for Different Modes
Conditions
Measured on
Consumption Typ
Unit
-CPU running a recursive Fibonacci algorithm
-CPU running a division algorithm
260
165
92
Active
Idle
µA/MHz
Frozen
Standby
Stop
58
47
37
DeepStop
23
-OSC32K and AST stopped
-Internal core supply
10
5.3
4.7
Amp0
µA
-OSC32K running
Static
-AST running at 1KHz
-External core supply (Figure 7-2)
-OSC32K and AST stopped
-External core supply (Figure 7-2)
-OSC32K running
600
9
-AST running at 1KHz
Shutdown
nA
-AST and OSC32K stopped
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Figure 7-1. Measurement Schematic, Internal Core Supply
VDDIN
VDDIO
Amp0
VDDCORE
VDDANA
Figure 7-2. Measurement Schematic, External Core Supply
VDDIN
Amp0
VDDIO
VDDCORE
VDDANA
7.6
I/O Pad Characteristics
Table 7-6.
Symbol
Normal I/O Pad Characteristics(1)
Parameter
Condition
Min
75
Typ
Max
Units
RPULLUP
Pull-up resistance
100
145
kOhm
VVDD = 3.0V
-0.3
0.3*VVDD
0.3*VVDD
VVDD + 0.3
VVDD + 0.3
VIL
VIH
Input low-level voltage
Input high-level voltage
V
V
VVDD = 1.62V
-0.3
VVDD = 3.6V
0.7*VVDD
0.7*VVDD
VVDD = 1.98V
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Table 7-6.
Symbol
Normal I/O Pad Characteristics(1)
Parameter
Condition
VDD = 3.0V, IOL = 3mA
VVDD = 1.62V, IOL = 2mA
VDD = 3.0V, IOH = 3mA
Min
Typ
Max
0.4
Units
V
VOL
Output low-level voltage
V
0.4
V
VVDD - 0.4
VVDD - 0.4
VOH
Output high-level voltage
Input leakage current
V
VVDD = 1.62V, IOH = 2mA
Pull-up resistors disabled
ILEAK
1
µA
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
Table 7-7.
Symbol
High-drive I/O Pad Characteristics(1)
Parameter
Condition
Min
30
Typ
50
Max
110
Units
PA06
RPULLUP
Pull-up resistance
PA02, PB01, RESET
PA08, PA09
75
100
20
145
kOhm
10
45
V
VDD = 3.0V
-0.3
0.3*VVDD
0.3*VVDD
VVDD + 0.3
VVDD + 0.3
0.4
VIL
Input low-level voltage
Input high-level voltage
Output low-level voltage
V
V
V
VVDD = 1.62V
-0.3
VVDD = 3.6V
0.7*VVDD
0.7*VVDD
VIH
VVDD = 1.98V
V
VDD = 3.0V, IOL = 6mA
VVDD = 1.62V, IOL = 4mA
VDD = 3.0V, IOH = 6mA
VOL
0.4
V
VVDD-0.4
VVDD-0.4
VOH
Output high-level voltage
Input leakage current
V
VVDD = 1.62V, IOH = 4mA
Pull-up resistors disabled
ILEAK
1
µA
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
Table 7-8.
Symbol
5V Tolerant Normal I/O Pad Characteristics(1)
Parameter
Condition
Min
75
Typ
Max
145
Units
RPULLUP
Pull-up resistance
100
kOhm
V
VDD = 3.0V
VVDD = 1.62V
VDD = 3.6V
-0.3
0.3*VVDD
0.3*VVDD
5.5
VIL
Input low-level voltage
Input high-level voltage
Output low-level voltage
V
V
V
-0.3
V
0.7*VVDD
0.7*VVDD
VIH
VVDD = 1.98V
5.5
VVDD = 3.0V, IOL = 3mA
VVDD = 1.62V, IOL = 2mA
VVDD = 3.0V, IOH = 3mA
VVDD = 1.62V, IOH = 2mA
5.5V, pull-up resistors disabled
0.4
VOL
0.4
VVDD-0.4
VVDD-0.4
VOH
Output high-level voltage
Input leakage current
V
ILEAK
1
µA
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
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Table 7-9.
Symbol
5V Tolerant High-drive I/O Pad Characteristics(1)
Parameter
Condition
Min
30
Typ
Max
110
Units
RPULLUP
Pull-up resistance
50
kOhm
V
VDD = 3.0V
VVDD = 1.62V
VDD = 3.6V
VVDD = 1.98V
VDD = 3.0V, IOL = 6mA
VVDD = 1.62V, IOL = 4mA
VDD = 3.0V, IOH = 6mA
-0.3
0.3*VVDD
0.3*VVDD
5.5
VIL
Input low-level voltage
Input high-level voltage
Output low-level voltage
V
V
V
-0.3
V
0.7*VVDD
0.7*VVDD
VIH
5.5
V
0.4
VOL
0.4
V
VVDD-0.4
VVDD-0.4
VOH
Output high-level voltage
Input leakage current
V
VVDD = 1.62V, IOH = 4mA
ILEAK
5.5V, pull-up resistors disabled
1
µA
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
Table 7-10. TWI Pad Characteristics(1)
Symbol
Parameter
Condition
Min
25
Typ
Max
Units
RPULLUP
Pull-up resistance
35
50
kOhm
VVDD = 3.0V
-0.3
0.3*VVDD
VIL
VIH
Input low-level voltage
Input high-level voltage
V
V
VVDD = 1.62V
-0.3
0.3*VVDD
VVDD = 3.6V
0.7*VVDD
0.7*VVDD
VVDD + 0.3
VVDD = 1.98V
VVDD + 0.3
VOL
ILEAK
IIL
Output low-level voltage
Input leakage current
Input low leakage
Input high leakage
Max frequency
IOL = 3mA
0.4
1
V
Pull-up resistors disabled
µA
µA
µA
kHz
1
IIH
1
fMAX
Cbus = 400pF, VVDD > 2.0V
400
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details.
7.7
Oscillator Characteristics
Oscillator 0 (OSC0) Characteristics
Digital Clock Characteristics
7.7.1
7.7.1.1
The following table describes the characteristics for the oscillator when a digital clock is applied
on XIN.
Table 7-11. Digital Clock Characteristics
Symbol
fCPXIN
Parameter
Conditions
Min
Typ
Max
50
60
Units
MHz
%
XIN clock frequency
XIN clock duty cycle
tCPXIN
40
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7.7.1.2
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected
between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator
where the crystal load capacitance CL is within the range given in the table. The exact value of CL
can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
CLEXT = 2(CL – Ci) – CPCB
where CPCB is the capacitance of the PCB.
Table 7-12. Crystal Oscillator Characteristics
Symbol
1/(tCPMAIN
CL
Parameter
Conditions
Min
3
Typ
Max
16
Unit
MHz
pF
)
Crystal oscillator frequency
Crystal load capacitance
Internal equivalent load capacitance
Startup time
6
18
Ci
2
pF
tSTARTUP
SCIF.OSCCTRL.GAIN = 2(1)
30 000(2)
cycles
Notes: 1. Please refer to the SCIF chapter for details.
2. Nominal crystal cycles.
Figure 7-3. Oscillator Connection
CLEXT
XOUT
XIN
UC3L
Ci
CL
CLEXT
7.7.2
32KHz Crystal Oscillator (OSC32K) Characteristics
Figure 7-3 and the equation above also applies to the 32KHz oscillator connection. The user
must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can then be found in the crystal datasheet.
Table 7-13. 32 KHz Crystal Oscillator Characteristics
Symbol
1/(tCP32KHz
tST
Parameter
Conditions
Min
Typ
Max
Unit
Hz
)
Crystal oscillator frequency
Startup time
32 768
30 000(1)
RS = 60kOhm, CL = 9pF
cycles
pF
CL
Crystal load capacitance
6
12.5
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Table 7-13. 32 KHz Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
2
Max
Unit
Internal equicalent load
capacitance
Ci
pF
IOSC
RS
Current consumption
0.9
µA
Equivalent series resistance
32 768Hz
35
85
kOhm
Note:
7.7.3
Table 7-14. Digital Frequency Locked Loop Characteristics
1. Nominal crystal cycles.
Digital Frequency Locked Loop (DFLL) Characteristics
Symbol
fOUT
Parameter
Conditions
Min
40
8
Typ
Max
150
150
Unit
MHz
kHz
%
Output frequency
Reference frequency
FINE resolution
fREF
FINE>100, all COARSE values
0.25
0.1
Fine lock, fREF=32kHz, SSG disabled
0.5
0.5
1
Accurate lock, fREF=32kHz, dither clk
RCSYS/2, SG disabled
0.06
0.2
0.1
22
Accuracy
%
Fine lock, fREF=8-150kHz, SSG disabled
Accurate lock, fREF=8-150kHz, dither clk
RCSYS/2, SSG disabled
1
Power consumption
Startup time
µA/MHz
µs
tSTARTUP
Within 90% of final values
100
fREF = 32kHz, fine lock, SSG disabled
600
tLOCK
Lock time
µs
f
REF = 32kHz, accurate lock, dithering
1100
clock = RCSYS/2, SSG disabled
Note:
1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
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7.7.4
120MHz RC Oscillator (RC120M) Characteristics
Table 7-15. Internal 120MHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
120
+/-5
50
Max
Unit
MHz
%
fOUT
Output frequency
Temperature drift
Duty cycle
T = 25°C, VVDDCORE = 1.8V
88
152
Duty
40
60
%
7.7.5
32kHz RC Oscillator (RC32K) Characteristics
Table 7-16. 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOUT
Output frequency
T = 25°C, VVDDIO = 3.3V
20
32
44
kHz
7.7.6
System RC Oscillator (RCSYS) Characteristics
Table 7-17. System RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOUT
Output frequency
Calibrated at 85°C
115
kHz
7.8
Flash Characteristics
Table 7-18 gives the device maximum operating frequency depending on the number of flash
wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the
number of wait states used when accessing the flash memory.
Table 7-18. Maximum Operating Frequency
Flash Wait States
Read Mode
Maximum Operating Frequency
1
0
1
0
50MHz
25MHz
30MHz
15MHz
High speed read mode
Normal read mode
Table 7-19. Flash Characteristics
Symbol
TFPP
Parameter
Conditions
Min
Typ
5
Max
Unit
Page programming time
Page erase time
TFPE
5
f
CLK_HSB= 50MHz
TFFP
Fuse programming time
Full chip erase time (EA)
JTAG chip erase time (CHIP_ERASE)
1
ms
TFEA
5
TFCE
fCLK_HSB= 115kHz
300
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Table 7-20. Flash Endurance and Data Retention
Symbol
NFARRAY
NFFUSE
tRET
Parameter
Conditions
Min
100k
10k
15
Typ
Max
Unit
cycles
cycles
years
Array endurance (write/page)
General Purpose fuses endurance (write/bit)
Data retention
7.9
Analog Characteristics
Voltage Regulator Characteristics
Electrical Characteristics
7.9.1
7.9.1.1
Table 7-21. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
3.3
1.8
Max
Units
VVDDIN
Input voltage range
1.98
3.6
V
V
VVDDCORE Output voltage
VVDDIN > 1.98V
OUT = 0.1mA to 60mA,
I
2
4
VVDDIN>2.2V
Output voltage accuracy
%
IOUT = 0.1mA to 60mA,
VVDDIN=1.98V to 2.2V
Normal mode
60
1
mA
mA
µA
IOUT
DC output current
Low power mode
Normal mode
20
6
ISCR
Static current of internal regulator
Low power mode
µA
7.9.1.2
Decoupling Requirements
Table 7-22. Decoupling Requirements
Symbol Parameter
Condition
Typ
33
Techno.
Units
nF
CIN1
Input regulator capacitor 1
Input regulator capacitor 2
Input regulator capacitor 3
Output regulator capacitor 1
CIN2
100
10
nF
CIN3
µF
COUT1
100
nF
Tantalum
COUT2
Output regulator capacitor 2
2.2
µF
0.5<ESR<10
Note:
1. Refer to Section 6.1.2 on page 36.
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7.9.2
ADC Characteristics
Table 7-23. Channel Conversion Time and ADC Clock
Symbol
fADC
Parameter
Conditions
Min
Typ
Max
6
Units
10-bit resolution mode
8-bit resolution mode
Return from Idle Mode
ADC clock frequency
MHz
6
tSTARTUP
Startup time
15
µs
ns
Sample and hold acquisition time
Conversion time (latency)
500
11
tCONV
fADC = 6MHz
26
cycles
fADC = 6MHz, 10-bit resolution
mode, low impedance source
460
Throughput rate
kSPS
fADC = 6MHz, 8-bit resolution
mode, low impedance source
460
Table 7-24. External Voltage Reference Input
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VADVREFP
Reference voltage range
VADVREFP = VVDDANA
1.62
1.98
V
On 13 samples with ADC Clock =
5MHz
Current consumption on VVDDANA
Average current
mA
µA
IADVREFP
fADC = 6MHz
250
Table 7-25. Analog Inputs
Symbol
Parameter
Conditions
Min
Typ
Max
Units
10-bit mode
8-bit mode
VADn
Input Voltage Range
0
VADVREFP
V
7.9.2.1
Applicable Conditions and Derating Data
Table 7-26. Transfer Characteristics 10-bit Resolution Mode
Parameter
Conditions
Min
Typ
10
Max
Units
Resolution
Bit
Integral non-linearity
Differential non-linearity
Offset error
+/-2
-0.9
1
ADC clock frequency = 6MHz
LSB
+/-4
+/-4
Gain error
Table 7-27. Transfer Characteristics 8-bit Resolution Mode
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
Bit
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Table 7-27. Transfer Characteristics 8-bit Resolution Mode
Parameter
Conditions
Min
Typ
Max
Units
Integral non-linearity
Differential non-linearity
Offset error
+/-0.5
-0.23
0.25
ADC clock frequency = 6MHz
LSB
+/-1
+/-1
Gain error
7.9.3
Analog Comparator Characteristics
Table 7-28. Analog Comparator Characteristics
Symbol
Parameter
Condition
Min
Typ
20
Max
VVDDIO + 0.3
VDDIO - 0.6
Units
Positive input voltage range
Negative input voltage range
-0.2
-0.2
V
V
V
VACREFN = 1.0V, fAC= 12MHz,
filter length=2, hysteresis=0.(1)
Statistical offset
mV
fAC
Clock frequency for GCLK4
Startup time
12
MHz
cycles
tSTARTUP
3
Input current per pin
0.2
µA/MHz(2)
Notes: 1. AC.CONFn.FLEN and AC.CONFn.HYS fields, refer to the Analog Comparator Interface chapter.
2. Referring to fAC
.
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7.9.4
POR18
Table 7-29. Power-on Reset Characteristics
Symbol
VPOT+
Parameter
Condition
Min
Typ
1.45
1.32
Max
Units
Voltage threshold on VVDDCORE rising T=25°C
Voltage threshold on VVDDCORE falling T=25°C
V
V
VPOT-
Figure 7-4. POR18 Operating Principles
VPOT+
VPOT-
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7.9.5
POR33
Table 7-30. POR33 Characteristics
Symbol
VPOT+
Parameter
Condition
Min
Typ
1.49
1.45
Max
Units
Voltage threshold on VVDDIN rising
Voltage threshold on VVDDIN falling
T=25°C
V
VPOT-
Figure 7-5. POR33 Operating Principles
VPOT+
VPOT-
7.9.6
Temperature Sensor
Table 7-31. Temperature Sensor Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Gradient
1
mV/°C
7.10 Timing Characteristics
7.10.1
RESET_N Characteristics
Table 7-32. RESET_N Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
ns
tRESET
RESET_N minimum pulse length
10
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8. Mechanical Characteristics
8.1
Thermal Considerations
8.1.1
Thermal Data
Table 8-1 summarizes the thermal resistance data depending on the package.
Table 8-1.
Symbol
θJA
Thermal Resistance Data
Parameter
Condition
Package
TQFP48
TQFP48
QFN48
Typ
63.2
21.8
28.3
2.5
Unit
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
°C/W
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
°C/W
°C/W
θJC
QFN48
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
TLLGA48
TLLGA48
30.06
TBD
θJC
8.1.2
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. = T + (P × θ
T
)
J
A
D
JA
2. TJ = TA + (PD × (θHEATSINK + θJC ))
where:
• θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1.
• θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 8-1.
• θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• PD = device power consumption (W) estimated from data provided in the Section 7.5 on page
42.
• TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation should be used to compute the resulting average chip-junction temperature TJ in °C.
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8.2
Package Drawings
Figure 8-1. TQFP-48 Package Drawing
Table 8-2.
Device and Package Maximum Weight
140
mg
Table 8-3.
Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-4.
Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Figure 8-2. QFN-48 Package Drawing
Note:
The exposed pad is not connected to anything.
Table 8-5.
Device and Package Maximum Weight
140
mg
Table 8-6.
Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-7.
Package Reference
JEDEC Drawing Reference
JESD97 Classification
M0-220
E3
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Figure 8-3. TLLGA-48 Package Drawing
Table 8-8.
Device and Package Maximum Weight
39.3
mg
Table 8-9.
Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-10. Package Reference
JEDEC Drawing Reference
JESD97 Classification
M0-220
E4
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8.3
Soldering Profile
Table 8-11 gives the recommended soldering profile from J-STD-20.
Table 8-11. Soldering Profile
Profile Feature
Green Package
3°C/s max
150-200°C
60-150 s
Average Ramp-up Rate (217°C to Peak)
Preheat Temperature 175°C ±25°C
Time Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
30 s
260°C
Ramp-down Rate
6°C/s max
8 minutes max
Time 25°C to Peak Temperature
A maximum of three reflow passes is allowed per component.
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9. Ordering Information
Table 9-1.
Ordering Information
Temperature Operating
Device
Ordering Code
Carrier Type
ES
Package
Package Type
Range
AT32UC3L064-AUTES
AT32UC3L064-AUT
AT32UC3L064-AUR
AT32UC3L064-ZAUES
AT32UC3L064-ZAUT
AT32UC3L064-ZAUR
AT32UC3L064-D3HES
AT32UC3L064-D3HT
AT32UC3L064-D3HR
AT32UC3L032-AUT
AT32UC3L032-AUR
AT32UC3L032-ZAUT
AT32UC3L032-ZAUR
AT32UC3L032-D3HT
AT32UC3L032-D3HR
AT32UC3L016-AUT
AT32UC3L016-AUR
AT32UC3L016-ZAUT
AT32UC3L016-ZAUR
AT32UC3L016-D3HT
AT32UC3L016-D3HR
Tray
TQFP 48
Tape & Reel
ES
JESD97 Classification E3
JESD97 Classification E4
AT32UC3L064
Tray
QFN 48
Tape & Reel
ES
Tray
TLLGA 48
Tape & Reel
Tray
TQFP 48
QFN 48
Tape & Reel
Tray
Industrial (-40°C to 85°C)
JESD97 Classification E3
JESD97 Classification E4
JESD97 Classification E3
JESD97 Classification E4
AT32UC3L032
Tape & Reel
Tray
TLLGA 48
TQFP 48
QFN 48
Tape & Reel
Tray
Tape & Reel
Tray
AT32UC3L016
Tape & Reel
Tray
TLLGA 48
Tape & Reel
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10. Errata
10.1 Rev. E
10.1.1
Processor and Architecture
1. Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
2. Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
10.1.2
FLASHCDW
1. Flash Selfprogramming may fail in one wait state mode
Writes in flash and user pages may fail if executing code located in the address space
mapped to the flash and if the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is 1).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the
maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
10.1.3
Power Manager
1. Clock sources will not be stopped in Static mode if the difference between CPU and
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
Before going to sleep modes where RCSYS is stopped, make sure the division factor
between the CPU/HSB and PBx frequencies is less than or equal to 4.
2. Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
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Solution 2: Only turn off the CFD while running the main clock on RCSYS.
10.1.4
SCIF
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
10.1.5
AST
1. Reset may set status bits in the AST
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter-
ing sleep mode.
2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
10.1.6
WDT
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the the WDT counter is cleared after the first half of the timeout
period, you will get a Watchdog reset immediately. If the WDT counter is not cleared at all,
the time before the reset will be twice as long as needed.
10.1.7
GPIO
1. Clearing GPIO interrupt may fail
Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is
enabled for the corresponding port.
Fix / Workaround
Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the
interrupt.
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10.1.8
SPI
1. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and
NCPHA==0
When multiple chip selects are in use, if one of the baudrates is equal to 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
4. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
5. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
10.1.9
TWI
1. TWIM.SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
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10.1.10 PWMA
1. BUSY bit is never cleared after writes to the Control Register (CR)
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
2. Incoming peripheral events are discarded during duty cycle register update
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
10.1.11 CAT
1. CAT asynchronous wake will be delayed by one AST peripheral event period
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
10.1.12 aWire
1. aWire CPU clock speed robustness
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
2. The aWire debug interface is reset after leaving Shutdown mode
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wake-up either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
10.1.13 I/O Pins
1. PA17 has low ESD tolerance
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
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10.2 Rev. D
10.2.1
Processor and Architecture
1. Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
2. Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
10.2.2
FLASHCDW
1. Flash Selfprogramming may fail in one wait state mode
Writes in flash and user pages may fail if executing code located in the address space
mapped to the flash and if the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is 1).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the
maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
10.2.3
Power Manager
1. Clock sources will not be stopped in Static mode if the difference between CPU and
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
Before going to sleep modes where RCSYS is stopped, make sure the division factor
between the CPU/HSB and PBx frequencies is less than or equal to 4.
2. External reset in Shutdown mode
If an external reset is asserted while the chip is in Shutdown mode, the Power Manager will
register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause reg-
ister (RCAUSE).
Fix/Workaround
None.
3. Disabling POR33 may generate spurious resets
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
- When POR33 is disabled from the user interface.
- When SM33 supply monitor is enabled.
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- When entering Shutdown mode while debugging the chip using JTAG or aWire interface.
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective.
Fix/Workaround
- Do not disable POR33 using the user interface.
- Do not use the SM33 supply monitor.
- Do not enter Shutdown mode if a debugger is connected to the chip.
4. Instability when exiting sleep walking
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
-The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
-A sleep mode where the OSC0 is automatically disabled is entered
-The chip enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleep walking is expected to be used.
5. Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
10.2.4
SCIF
1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
10.2.5
AST
1. Reset may set status bits in the AST
If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may
be set.
Fix/Workaround
If the part is reset and the AST is used, clear all bits in the Status Register (SR) before enter-
ing sleep mode.
2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
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10.2.6
WDT
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter s not cleared at all, the time
before the reset will be twice as long as needed.
10.2.7
GPIO
1. Clearing GPIO interrupt may fail
Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is
enabled for the corresponding port.
Fix / Workaround
Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the
interrupt.
10.2.8
SPI
1. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and
NCPHA==0
When multiple chip selects are in use, if one of the baudrates is equal to 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
4. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
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5. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
10.2.9
TWI
1. TWIM.SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
10.2.10 PWMA
1. BUSY bit is never cleared after writes to the Control Register (CR)
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
2. Incoming peripheral events are discarded during duty cycle register update
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
10.2.11 CAT
1. CAT asynchronous wake will be delayed by one AST peripheral event period
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
10.2.12 aWire
1. aWire CPU clock speed robustness
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
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2. The aWire debug interface is reset after leaving Shutdown mode
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wakeup either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
10.2.13 I/O Pins
1. PA17 has low ESD tolerance
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
10.2.14 Chip
1. Increased Power Consumption in VDDIO in sleep modes
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Solution 1: Disable the OSC0 bt writing a zero to the Oscillator Enable bit in the System
Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before
going to any sleep mode where the OSC0 is disabled
Solution 2: Pull down or up XIN0 and XOUT0 with 1Mohm resistor.
2. In 3.3V Single Supply Mode the Analog Comparator inputs affects the device’s ability
to start
When using the 3.3V Single Supply Mode the state of the Analog Comparator input pins can
affect the device’s ability to release POR reset.
This is due to an interaction between the Analog Comparator input pins and the POR cir-
cuitry. The issue is not present in the 1.8V Single Supply Mode or the 3.3V Supply mode
with 1.8V Regulated I/O Lines.
Fix/Workaround:
ACREFN (pin PA16) must be connected to GND until the POR reset is released and the
Analog Comparator inputs should not be driven higher than 1.0V until the POR reset is
released.
10.3 Rev. C
10.4 Rev. B
Not sampled.
10.4.1
Processor and Architecture
1. Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
2. Hardware breakpoints may corrupt MAC results
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Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
3. RETS behaves incorrectly when MPU is enabled
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not readable in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
atomically. Even if this step is described in general as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
10.4.2
FLASHCDW
1. Flash Selfprogramming may fail in one wait state mode
Writes in flash and user pages may fail if executing code located in the address space
mapped to the flash and if the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is 1).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the
maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
2. Chip Erase
When performing a chip erase, the device may report that it is protected (IR=0x11) and that
chiperase failed, even if the chip erase was succesful.
Fix/Workaround
Perform a reset before any further read and programming.
3. Fuse Programming
Programming of fuses does not work.
Fix/Workaround
Do not program fuses. All fuses will be erased during chiperase command.
4. Wait 500ns before reading from the flash after switching read mode
After switching between normal read mode and high-speed read mode, the application must
wait at least 500ns before attempting any access to the flash.
Fix/Workaround
Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a
waiting-loop is executed from RAM waiting 500ns or more before executing from flash.
Solution 2: Execute from flash with a clock with period longer than 500ns. This guarantees
that no new read access is attempted before the flash has had time to settle in the new read
mode.
5. VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
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10.4.3
10.4.4
HMATRIX
1. In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
SAU
1. The SR.IDLE bit reads as zero
The IDLE bit in the Status Register (SR.IDLE) reads as zero.
Fix/Workaround
None.
2. Open Mode is not functional
The Open Mode is not functional.
Fix/workaround
None.
3. VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x110.
Fix/Workaround
None.
10.4.5
PDCA
1. PCONTROL.CHxRES is nonfunctional
PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
SW needs to keep history of performance counters.
2. Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/workaround
Disable and then enable the peripheral after the transfer error.
3. VERSION register reads 0x120
The VERSION register reads 0x120 instead of 0x122.
Fix/Workaround
None.
10.4.6
Power Manager
1. Clock sources will not be stopped in Static mode if the difference between CPU and
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
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Before going to sleep modes where RCSYS is stopped, make sure the division factor
between the CPU/HSB and PBx frequencies is less than or equal to 4.
2. Disabling POR33 may generate spurious resest
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
- When POR33 is disabled from the user interface.
- When SM33 supply monitor is enabled.
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface.
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective.
Fix/Workaround
- Do not disable POR33 using the user interface.
- Do not use the SM33 supply monitor.
- Do not enter Shutdown mode if a debugger is connected to the chip.
3. CONFIG register reads 0x4F
The CONFIG register reads 0x4F instead of 0x43.
Fix/Workaround
None.
4. PB writes via debugger in sleep modes are blocked during sleepwalking
During sleepwalking, PB writes performed by a debugger will be discarded by all PB mod-
ules except the module that is requesting the clock.
Fix/Workaround
None.
5. VERSION register reads 0x400
The VERSION register reads 0x400 instead of 0x411.
Fix/Workaround
None.
6. WCAUSE register should not be used
The WCAUSE register should not be used.
Fix/Workaround
None.
7. Static mode cannot be entered if the WDT is using OSC32K
If the WDT is using OSC32K as clock source and the user tries to enter Static mode, the
Deepstop mode will be entered instead.
Fix/Workaround
None.
8. It is not possible to mask the request clock requests
It is not possible to mask the request clock requests using PPCR.
Fix/Workaround
None.
9. Clock failure detector (CFD) does not work
The clock failure detector does not work.
Fix/Workaround
None.
10. Instability when exiting sleep walking
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If all the following operating conditions are true, exiting sleep walking might lead to
instability:
-The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
-A sleep mode where the OSC0 is automatically disabled is entered
-The chip enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleep walking is expected to be used.
10.4.7
SCIF
1. The DFLL should be slowed down before disabled
The frequency of the DFLL should be set to minimum before disabled.
Fix/Workaround
Before disabling the DFLL the value of the COARSE register should be set to zero.
2. Writing to ICR masks new interrupts received in the same clock cycle
Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of
write value.
Fix/Workaround
For every interrupt except BODDET, SM33DET, and VREGOK the CLKSR register can be
read to detect new interrupts. BODDET, SM33DET, and VREGOK interrupts will not be gen-
erated if they occur when writing to ICR.
3. FINE value for DFLL is not correct when dithering is disabled
In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the
value written to the DFLL0CONF.FINE field. I.e. the value to the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001, or 0x002 the
value to the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.
Fix/Workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
4. BODVERSION register reads 0x100
The BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
5. BRIFA is non-functional
BRIFA is non-functional.
Fix/Workaround
None.
6. VREGCR.DEEPMODEDISABLE bit is not readable
VREGCR.DEEPMODEDISABLE bit is not readable.
Fix/Workaround
None.
7. DFLL step size should be 7 or lower below 30 MHz
If max step size is above 7, the DFLL might not lock at the correct frequency if the target fre-
quency is below 30 MHz.
Fix/Workaround
If the target frequency is below 30 MHz, use max step size (DFLL0MAXSTEP.MAXSTEP) of
7 or lower.
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8. Generic clock sources are kept running in sleep modes
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to the
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
9. DFLL clock is unstable with a fast reference clock
The DFLL clock can be unstable when a fast clock is used as reference clock in closed loop
mode.
Fix/Workaround
Use the 32 KHz crystal oscillator clock or a clock with similar frequency as DFLLIF reference
clock.
10. DFLLIF indicates coarse lock too early
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
11. DFLLIF dithering does not work
The DFLLIF dithering does not work.
Fix/Workaround
None.
12. SCIF VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
13. DFLLVERSION register reads 0x200
The DFLLVERSION register reads 0x200 instead of 0x201.
Fix/Workaround
None.
14. RCCRVERSION register reads 0x100
The RCCRVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
15. OSC32VERSION register reads 0x100
The OSC32VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
16. VREGVERSION register reads 0x100
The VREGVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
17. RC120MVERSION register reads 0x100
The RC120MVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
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None.
18. GCLK5 is non-functional
GCLK5 is non-functional.
Fix/Workaround
None.
19. DFLLIF might loose fine lock when dithering is disabled
When dithering is disabled, and fine lock has been acquired the DFLL might loose the fine
lock resulting in a up to 20% over-/undershoot.
Fix/Workaround
Solution 1: When the DFLL is used as main clock source the target frequency of the DFLL
should be 20% below the maximum operating frequency of the CPU. Don’t use the DFLL as
clock source for frequency sensitive applications.
Solution 2: Do not use the DFLL in closed loop mode.
20. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures.
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.
10.4.8
AST
1. AST wake signal is released one AST clock cycle after the BUSY bit is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
10.4.9
WDT
1. Clearing of the WDT in window mode
In window mode, if the WDT is cleared 2TBAN CLK_WDT cycles after entering the window,
the counter will be cleared, but will not exit the window. If this occurs, the SR.WINDOW bit
will not be cleared after clearing the WDT.
Fix/Workaround
Check SR.WINDOW immediately after clearing the WDT. If set then clear the WDT once
more.
2. VERSION register reads 0x400
The VERSION register reads 0x400 instead of 0x402.
Fix/Workaround
None.
3. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
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If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the the WDT counter is cleared after the first half of the timeout
period, you will get a Watchdog reset immediately. If the WDT coutner s not cleared at all,
the time before the reset will be twice as long as needed.
10.4.10 FREQM
1. Measured clock (CLK_MSR) sources 15-17 are shifted
CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and
CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR).
Fix/Workaround
None.
2. GCLK5 can not be used as source for the CLK_MSR
The frequency for GCLK5 can not be measured by the FREQM.
Fix/Workaround
None.
10.4.11 GPIO
1. GPIO interrupt can not be cleared when interrupts are disabled
The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin.
Fix/Workaround
Enable interrupt for the corresponding pin, then clear the interrupt.
2. VERSION register reads 0x210
The VERSION register reads 0x210 instead of 0x211.
Fix/Workaround
None.
10.4.12 USART
1. The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
10.4.13 SPI
1. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
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Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and
NCPHA==0
When multiple chip selects are in use, if one of the baudrates is equal to 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
4. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
6. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
10.4.14 TWI
1. TWIM Version Register reads zero
TWIM Version Register (VR) reads zero instead of 0x101.
Fix/Workaround
None.
2. TWIS Version Register reads zero
TWIS Version Register (VR) reads zero instead of 0x112.
Fix/Workaround
None.
3. TWIS CR.STREN does not work in deep sleep modes
When the device is in Stop, DeepStop, or Static mode, address reception will not wake the
device if both CR.SOAM and CR.STREN are one.
Fix/Workaround
Do not write both CR.STREN and CR.SOAM to one if the device needs to wake from deep
sleep modes.
4. TWI pins are not SMBus compliant
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The TWI pins draws current when the pins are supplied with 3.3V and the part is left
unpowered.
Fix/Workaround
None.
5. PA21, PB04, and PB05 are not 5V tolerant
Pins PA21, PB04, and PB05 are only 3.3V tolerant, not 5V tolerant.
Fix/Workaround
None.
6. PB04 SMBALERT function should not be used
The SMBALERT function from TWIMS0 should not be selected on pin PB04.
Fix/Workaround
None.
7. TWIMS0.TWCK on PB05 is non-functional
TWIMS0.TWCK on PB05 is non-functional.
Fix/Workaround
Use TWI0.TWCK on other pins.
8. TWIM STOP bit in IMR always read as zero
The STOP bit in IMR always reads as zero.
Fix/Workaround
None.
9. TWIM.SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
10. Disabled TWIM drives TWD and TWCK low
When the TWIM is disabled, it drives the TWD and TWCK signals with logic level zero. This
can lead to communication problems with other devices on the TWI bus.
Fix/Workaround
Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO
controller. If it is necessary to disable the TWIM, first disable the TWD and TWCK periph-
eral pins in the GPIO controller and then disable the TWIM.
10.4.15 PWMA
1. PARAMETER register reads 0x2424
The PARAMETER register reads 0x2424 instead of 0x24.
Fix/Workaround
None.
2. Open drain mode does not work
The open drain mode does not work.
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Fix/Workaround
None.
3. VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
4. Writing to the duty cycle registers when the timebase counter overflows can give an
undefined result
The duty cycle registers will be corrupted if written when the timebase counter overflows. If
the duty cycle registers are written exactly when the timebase counter overflows at TOP, the
duty cycle registers may become corrupted.
Fix/Workaround
Write to the duty cycle registers only directly after the Timebase Overflow bit in the status
register is set.
5. BUSY bit is never cleared after writes to the Control Register (CR)
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
6. Incoming peripheral events are discarded during duty cycle register update
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
10.4.16 TC
1. When the main clock is RCSYS, TIMER_CLOCK5 is equal to CLK_PBA
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to CLK_PBA and
not CLK_PBA/128.
Fix/Workaround
None.
10.4.17 ADCIFB
1. Pendetect in sleep modes without CLK_ADCIFB will not wake the system
The pendetect will not wake the system from a sleep mode if the clock for the
ADCIFB (CLK_ADCIFB) is turned off.
Fix/Workaround
Use a sleep mode where CLK_ADCIFB is not turned off to wake the part using
pendetect.
2. 8-bit mode is not working
Do not use the 8-bit mode of the ADCIFB.
Fix/Workaround
Use the 10-bit mode and shift right by 2 bits.
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3. ADC channels six to eight are non-functional
ADC channels six to eight are non-functional.
Fix/Workaround
None.
4. VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
10.4.18 ACIFB
1. Negative offset
The static offset of the analog comparator is appriximately -50mV.
Fix/Workaround
None.
2. Generic clock sources in sleep modes
The ACIFB should not use RC32K or CLK_1K as generic clock source if the chip uses sleep
modes.
Fix/Workaround
None.
3. VERSION register reads 0x200
The VERSION register reads 0x200 instead of 0x212.
Fix/Workaround
None.
4. CONFW.WEVSRC and CONFW.WEVEN are not correctly described in the user
interface
CONFW.WEVSRC is only two bits instead of three bits wide. Only values 0, 1, and 2 can be
written to this register. CONFW.WEVEN is in bit position 10 instead of 11.
Fix/Workaround
Only write values 0, 1, and 2 to CONFW.WEVSRC. When reading CONFW.WEVSRC, dis-
regard the third bit. Read/write bit 10 to access CONFW.WEVEN.
10.4.19 CAT
1. Switch off discharge current when reaching 0V
The discharge current will switch off when reaching MGCFG1.MAX, not when reaching 0V.
Fix/Workaround
None.
2. CAT external capacitors are not clamped to ground when CAT is idle
The CAT module does not clamp the external capacitors to ground when it is idle. The
capacitors are left floating, so they could accumulate small amounts of charge.
Fix/workaround
None.
3. DISHIFT field is stuck at zero
The DISHIFT field in the MGCFG1, TGACFG1, TGBCFG1, and ATCFG1 registers is stuck
at zero and cannot be written to a different value. Capacitor discharge time will be deter-
mined only by the DILEN field.
Fix/Workaround
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None.
4. MGCFG2.ACCTRL bit is stuck at zero
The ACCTRL bit in the MGCFG2 register is stuck at zero and cannot be written to one. The
analog comparators will be constantly enabled.
Fix/Workaround
None.
5. MGCFG2.CONSEN field is stuck at zero
The CONSEN field in the MGCFG2 register is stuck at zero and cannot be written to a differ-
ent value. The CAT consensus filter does not function properly, so termination of QMatrix
data acquisition is controlled only by the MAX field in MGCFG1.
Fix/Workaround
None.
6. VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x200.
Fix/Workaround
None.
1. CAT asynchronous wake will be delayed by one AST peripheral event period
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
10.4.20 GLOC
1. GLOC is non-functional
Glue Logic Controller (GLOC) is non-functional.
Fix/Workaround
None.
10.4.21 aWire
1. aWire PB mapping and PB clock mask number
The aWire PB has a different PB address and PB clock mask number.
Fix/Workaround
Use aWire PB address 0xFFFF6C00 and PB clock (PBAMASK) 24.
2. SAB multiaccess reads are not working
Reading more than one word, halfword, or byte in one command is not working correctly.
Fix/Workaround
Split the access into several single word, halfword, or byte accesses.
3. If a reset happens during the last SAB write, the aWire will stall
If a reset happens during the last word, halfword, or byte write the aWire will wait forever for
an acknowledge from the SAB.
Fix/Workaround
Reset the aWire by keeping the RESET_N line low for 100ms.
4. aWire enable does not work in Static mode
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aWire enable does not work in Static mode.
Fix/Workaround
None.
5. VERSION register reads 0x200
The VERSION register reads 0x200 instead of 0x210.
Fix/Workaround
None.
6. The aWire debug interface is reset after leaving Shutdown mode
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wakeup either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
10.4.22 I/O Pins
1. PB10 is not 3.3V tolerant
PB10 should be grounded on the PCB and left unused.
Fix/Workaround
None.
2. Analog multiplexing consumes extra power
Current consumption on VDDIO increases when the voltage on analog inputs is close to
VDDIO/2.
Fix/Workaround
None.
3. PA02, PB01, PB04, PB05, and RESET_N have half of the pull-up strength
Pins PA02, PB01, PB04, PB05, and RESET_N have half of the specified pull-up strength.
Fix/Workaround
None.
4. OCD MCKO and MDO[3] are swapped in the AUX1 mapping
When using the OCD AUX1 mapping of trace signals MDO[3] is located on pin PB05
and MCKO is located on PB01.
Fix/Workaround
Swap pins PB01 and PB05 if using OCD AUX1.
5. The JTAG is enabled at power up
The JTAG function on pins PA00, PA01, PA02, and PA03, are enabled after startup. Normal
I/O module functionality is not possible on these pins.
Fix/Workaround
Add a 10kOhm pullup on the reset line.
10.4.23 Chip
1. Power consumption in static mode is too high
Power consumption in static mode is too high when PA21 is high.
Fix/Workaround
Ensure PA21 is low.
2. Shutdown mode is not functional
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Do not enter Shutdown mode.
Fix/Workaround
None.
3. VDDIN current consumption increase above 1.8V
When VDDIN increases above 1.8V, current on VDDIN increases with up to 40µA.
Fix/Workaround
None.
4. Increased Power Consumption in VDDIO in sleep modes
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Solution 1: Disable the OSC0 bt writing a zero to the Oscillator Enable bit in the System
Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before
going to any sleep mode where the OSC0 is disabled
Solution 2: Pull down or up XIN0 and XOUT0 with 1Mohm resistor.
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11. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
11.1 Rev. D - 06/2010
1.
Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to
AT32UC3L064-AUTES. TLLGA48 Tray option added.
11.2 Rev. C - 06/2010
1.
Features and Description: Added QTouch library support.
USART: Description of unimplemented features removed.
2.
3.
Electrical Characteristics: Power Consumption numbers updated. Flash timing numbers
added.
11.3 Rev. B - 05/2010
1.
2.
Package and Pinout: Added pinout figure for TLLGA48 package.
Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFB-
AD[3] on PA17 removed, number of ADC channels are 8, not 9.
3.
I/O Lines Considerations: Added: Following pins have high-drive capability: PA02, PA06,
PA08, PA09, and PB01.
Some TWI0 pins are SMBUS compliant (PA21, PB04, PB05).
HMATRIX Masters: PDCA is master 4, not master 3. SAU is master 3, not master 4.
SAU: IDLE bit added in the Status Register.
4.
5.
6.
7.
8.
PDCA: Number of PDCA performance monitors is device dependent.
Peripheral Event System: Chapter updated.
PM: Bits in RCAUSE registers removed and renamed (JTAGHARD and AWIREHARD renamed
to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed).
9.
PM: RCAUSE.BOD33 bit removed. SM33 reset will be detected as a POR reset.
PM: WDT can be used as wake-up source if WDT is clocked from 32KHz oscillator.
PM: Entering Shutdown mode description updated.
10.
11.
12.
13.
14.
15.
SCIF: DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz.
SCIF: Temperature sensor is connected to ADC channel 9, not 7.
SCIF: Updated the oscillator connection figure for OSC0
GPIO: Removed unimplemented features (pull-down, buskeeper, drive strength, slew rate,
schmitt trigger, open drain).
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16.
17.
18.
SPI: RDR.PCS field removed (RDR[19:16]).
TWIS: Figures updated.
ADCIFB: The sample and hold time and the startup time formulas have been corrected (ADC
Configuration Register).
19.
20.
ADCIFB: Updated ADC signal names.
ACIFB: CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit 11. CONF.EVENP and
CONF.EVENN bits are swapped.
21.
22.
23.
24.
CAT: Matrix size is 16 by 8, not 18 by 8.
Electrical Characteristics: General update.
Mechanical Characteristics: Added numbers for package drawings.
Mechanical Characteristics: In the TQFP-48 package drawing the Lead Coplanarity is
0.102mm, not 0.080mm.
25.
Ordering Information: Ordering code for TLLGA-48 package updated.
11.4 Rev. A – 06/2009
1.
Initial revision.
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Table of Contents
Features..................................................................................................... 1
Description ............................................................................................... 3
Overview ................................................................................................... 5
1
2
2.1
2.2
Block Diagram ...................................................................................................5
Configuration Summary .....................................................................................6
3
4
Package and Pinout ................................................................................. 7
3.1
3.2
3.3
3.4
Package .............................................................................................................7
Peripheral Multiplexing on I/O lines ...................................................................9
Signal Descriptions ..........................................................................................13
I/O Line Considerations ...................................................................................16
Processor and Architecture .................................................................. 18
4.1
4.2
4.3
4.4
4.5
Features ..........................................................................................................18
AVR32 Architecture .........................................................................................18
The AVR32UC CPU ........................................................................................19
Programming Model ........................................................................................23
Exceptions and Interrupts ................................................................................27
5
Memories ................................................................................................ 32
5.1
5.2
5.3
5.4
Embedded Memories ......................................................................................32
Physical Memory Map .....................................................................................32
Peripheral Address Map ..................................................................................33
CPU Local Bus Mapping .................................................................................34
6
7
Supply and Startup Considerations ..................................................... 36
6.1
6.2
Supply Considerations .....................................................................................36
Startup Considerations ....................................................................................40
Electrical Characteristics ...................................................................... 41
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Disclaimer ........................................................................................................41
Absolute Maximum Ratings* ...........................................................................41
Supply Characteristics .....................................................................................41
Maximum Clock Frequencies ..........................................................................42
Power Consumption ........................................................................................42
I/O Pad Characteristics ....................................................................................44
Oscillator Characteristics .................................................................................46
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7.8
Flash Characteristics .......................................................................................49
Analog Characteristics .....................................................................................50
Timing Characteristics .....................................................................................54
7.9
7.10
8
9
Mechanical Characteristics ................................................................... 55
8.1
8.2
8.3
Thermal Considerations ..................................................................................55
Package Drawings ...........................................................................................56
Soldering Profile ..............................................................................................59
Ordering Information ............................................................................. 60
10 Errata ....................................................................................................... 61
10.1
10.2
10.3
10.4
Rev. E ..............................................................................................................61
Rev. D ..............................................................................................................65
Rev. C ..............................................................................................................69
Rev. B ..............................................................................................................69
11 Datasheet Revision History .................................................................. 84
11.1
11.2
11.3
11.4
Rev. D - 06/2010 .............................................................................................84
Rev. C - 06/2010 .............................................................................................84
Rev. B - 05/2010 ..............................................................................................84
Rev. A – 06/2009 .............................................................................................85
Table of Contents....................................................................................... i
ii
32099DS–06/2010
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