AT28BV64B-25JI [ATMEL]
64K (8K x 8) Battery-Voltage⑩ Parallel EEPROM with Page Write and Software Data Protection; 64K （ 8K ×8 ）电池Voltage⑩并行EEPROM与页写入和软件数据保护
| 型号： | AT28BV64B-25JI |
| 厂家： | 
ATMEL |
| 描述： | 64K (8K x 8) Battery-Voltage⑩ Parallel EEPROM with Page Write and Software Data Protection |
| 文件： | 总12页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single 2.7V to 3.6V Supply
• Hardware and Software Data Protection
• Low Power Dissipation
– 15 mA Active Current
– 20 µA CMOS Standby Current
• Fast Read Access Time - 200 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
64K (8K x 8)
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
• DATA Polling for End of Write Detection
• High-reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges
Battery-Voltage™
Parallel EEPROM
with Page Write
and Software
Description
Data Protection
The AT28BV64B is a high-performance electrically erasable programmable read only
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20 µA.
AT28BV64B
(continued)
Pin Configurations
PDIP, SOIC
Top View
Pin Name
A0 - A12
CE
Function
Addresses
NC
A12
A7
1
2
3
4
5
6
7
8
9
28 VCC
27 WE
26 NC
25 A8
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A6
OE
A5
24 A9
A4
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
A3
WE
A2
A1
I/O0 - I/O7
NC
3-Volt, 64K
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
E2PROM with
Data Protection
DC
Don’t Connect
PLCC
Top View
TSOP
Top View
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
NC
WE
VCC
NC
A12
A7
5
A1 10
A0 11
6
7
NC 12
I/O0 13
8
9
10
11
12
13
14
A6
A5
A4
A1
Rev. 0299F–05/28/99
A3
A2
Note:
PLCC package pins 1 and 17
are DON’T CONNECT.
The AT28BV64B is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 64 byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will automat-
ically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA polling of
I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high
quality and manufacturability. A software data protection
mechanism guards against inadvertent writes. The device
also includes an extra 64 bytes of EEPROM for device
identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28BV64B
2
AT28BV64B
Device Operation
READ: The AT28BV64B is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention in their systems.
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling opera-
tion.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28BV64B in the follow-
ing ways: (a) VCC power-on delay—once VCC has reached
1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibit holding
any one of OE low, CE high or WE high inhibits write
cycles; and (c) noise filter pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
PAGE WRITE: The page write operation of the
AT28BV64B allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 100 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded, the AT28BV64B will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs. For
each WE high to low transition during the page write opera-
tion, A6 to A12 must be the same.
SOFTWARE DATA PROTECTION: A software-controlled
data protection feature has been implemented on the
AT28BV64B. Software data protection (SDP) helps prevent
inadvertent writes from corrupting the data in the device.
SDP can prevent inadvertent writes during power-up and
power-down as well as any other potential periods of sys-
tem instability.
The AT28BV64B can only be written using the software
data protection feature. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera-
tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the
addresses in the command sequence can be utilized just
like any other location in the device.
The A0 to A5 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING: The AT28BV64B features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
Any attempt to write to the device without the 3-byte
sequence will start the internal write timers. No data will be
written to the device; however, for the duration of tWC, read
operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH, the additional bytes may be written to or
read from in the same manner as the regular memory
array.
TOGGLE BIT: In addition to DATA Polling, the AT28BV64B
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
3
DC and AC Operating Range
AT28BV64B-20
0°C - 70°C
AT28BV64B-25
0°C - 70°C
Operating
Temperature (Case)
Com.
Ind.
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
µA
µA
µA
µA
mA
V
ILO
10
Com.
Ind.
20
CE = VCC - 0.3V to
VCC + 1V
ISB
VCC Standby Current CMOS
50
ICC
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
f = 5 MHz; IOUT = 0 mA
15
VIL
0.6
VIH
VOL
VOH
2.0
2.0
V
IOL = 1.6 mA
IOH = -100 µA
0.45
V
V
AT28BV64B
4
AT28BV64B
AC Read Characteristics
AT28BV64B-20
AT28BV64B-25
Symbol
Parameter
Min
Max
200
200
80
Min
Max
250
250
100
60
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
ns
(2)
tOE
0
0
0
0
ns
(3)(4)
tDF
55
ns
Output Hold from OE, CE or Address, whichever
occurred first
tOH
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
100
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
200
100
0
ns
tDS
ns
tDH, tOEH
tDV
Data, OE Hold Time
Time to Data Valid
ns
NR(1)
tWPH
Write Pulse Width High
100
ns
Notes: 1. NR = No Restriction
2. All byte write operations must be preceded by the SDP command sequence.
AC Write Waveforms
WE Controlled
CE Controlled
AT28BV64B
6
AT28BV64B
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
ns
tBLC
tWPH
100
µs
100
ns
Write Algorithm(1)
LOAD DATA AA
TO
ADDRESS 1555
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD DATA A0
TO
ADDRESS 1555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(3)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex).
2. Data protect state will be re-activated at the end of the write cycle.
3. 1 to 64 bytes of data are loaded.
7
Software Data Protection Write Cycle Waveforms(1)(2)(3)
Notes: 1. A0 - A12 must conform to the addressing sequence for the first three bytes as shown above.
2. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
3. OE must be high only when WE and CE are both low.
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
0
ns
OE to Output Delay(2)
ns
tWR
Write Recovery Time
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
AT28BV64B
8
AT28BV64B
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used, but the address should not vary.
9
Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
200
15
15
15
15
0.05
0.05
0.05
0.05
AT28BV64B-20JC
AT28BV64B-20PC
AT28BV64B-20SC
AT28BV64B-20TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28BV64B-20JI
AT28BV64B-20PI
AT28BV64B-20SI
AT28BV64B-20TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
250
AT28BV64B-25JC
AT28BV64B-25PC
AT28BV64B-25SC
AT28BV64B-25TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28BV64B-25JI
AT28BV64B-25PI
AT28BV64B-25SI
AT28BV64B-25TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
Note:
1. See Valid Part Number table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28BV64B
Speed
20
Package and Temperature Combinations
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
AT28BV64B
25
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28S
28T
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
AT28BV64B
10
AT28BV64B
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
28P6, 28-lead, 0.600" Wide,
Plastic Dual In-Line Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
1.47(37.3)
1.44(36.6)
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
PIN
1
.012(.305)
.008(.203)
IDENTIFY
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.553(14.0)
.547(13.9)
.595(15.1)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.585(14.9)
.090(2.29)
MAX
1.300(33.02) REF
.030(.762)
.220(5.59)
MAX
.050(1.27) TYP
.005(.127)
MIN
.300(7.62) REF
.430(10.9)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
SEATING
PLANE
.390(9.90)
AT CONTACT
POINTS
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
.022(.559) X 45˚ MAX (3X)
0
15
.453(11.5)
.447(11.4)
REF
.012(.305)
.008(.203)
.495(12.6)
.485(12.3)
.690(17.5)
.610(15.5)
28S, 28-lead, 0.300" Wide,
Plastic Gull Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
13.7 (0.539)
13.1 (0.516)
11.9 (0.469)
11.7 (0.461)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
REF
5
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
11
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FAX (81) 3-3523-7581
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
Terms and product names in this document may be trademarks of others.
0299F–05/28/99/xM
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