AT28BV64B-20TU [ATMEL]
64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection; 64K （ 8K ×8 ）电池电压并行EEPROM与页写入和软件数据保护
| 型号： | AT28BV64B-20TU |
| 厂家： | 
ATMEL |
| 描述： | 64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection |
| 文件： | 总17页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
Single 2.7V to 3.6V Supply
Hardware and Software Data Protection
Low Power Dissipation
– 15 mA Active Current
– 20 µA CMOS Standby Current
Fast Read Access Time – 200 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
•
•
64K (8K x 8)
Battery-Voltage
Parallel
•
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
– Endurance: 100,000 Cycles
•
•
EEPROM
– Data Retention: 10 Years
with Page Write
and Software
Data Protection
•
•
•
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
1. Description
The AT28BV64B is a high-performance electrically erasable programmable read only-
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20 µA.
AT28BV64B
The AT28BV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64 byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high quality and manufactura-
bility. A software data protection mechanism guards against inadvertent writes. The
device also includes an extra 64 bytes of EEPROM for device identification or
tracking.
0299H–PEEPR–10/06
2.2
32-lead PLCC Top View
2. Pin Configurations
Pin Name
A0 - A12
CE
Function
Addresses
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
A1 10
A0 11
NC 12
I/O0 13
DC
Don’t Connect
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2.1
28-lead PDIP/SOIC Top View
2.3
28-lead TSOP Top View
NC
A12
A7
1
2
3
4
5
6
7
8
9
28 VCC
27 WE
26 NC
25 A8
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
A6
NC
WE
5
A5
24 A9
6
A4
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
VCC
NC
A12
A7
7
8
A3
9
A2
10
11
12
13
14
A1
A6
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
A5
A4
A1
A3
A2
2
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
3. Block Diagram
4. Device Operation
4.1
Read
The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of tWC, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100 µs (tBLC) of the previous byte. If the
t
BLC limit is exceeded, the AT28BV64B will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
3
0299H–PEEPR–10/06
4.4
4.5
DATA Polling
Toggle Bit
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
In addition to DATA Polling, the AT28BV64B provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Reading the toggle bit may begin at any time during the
write cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect
the memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
(a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically
time out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low,
CE high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
4.6.2
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV64B. Soft-
ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature. A series of
three write commands to specific addresses with specific data must be presented to the
device before writing in the byte or page mode. The same three write commands must begin
each write operation. All software write commands must obey the page mode write timing
specifications. The data in the 3-byte command sequence is not written to the device; the
addresses in the command sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write tim-
ers. No data will be written to the device; however, for the duration of tWC, read operations will
effectively be polling operations.
4.7
Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes
may be written to or read from in the same manner as the regular memory array.
4
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
5. DC and AC Operating Range
AT28BV64B-20
-40° C - 85°C
2.7V to 3.6V
Operating Temperature (Case)
V
CC Power Supply
6. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
VIL
VIH
X(1)
X
Standby/Write Inhibit
Write Inhibit
High Z
VIH
X
Write Inhibit
X
VIL
VIH
Output Disable
Chip Erase
X
X
High Z
High Z
(3)
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
7. Absolute Maximum Ratings*
Temperature Under Bias............................... -55°C to +125° C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature.................................... -65°C to +150° C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
10
ISB
CE = VCC - 0.3V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
50
ICC
15
VIL
0.6
VIH
2.0
2.0
V
VOL
VOH
IOL = 1.6 mA
IOH = -100 µA
0.45
V
V
5
0299H–PEEPR–10/06
9. AC Read Characteristics
AT28BV64B-20
Symbol
Parameter
Min
Max
Units
ns
tACC
Address to Output Delay
200
200
80
(1)
tCE
CE to Output Delay
ns
(2)
tOE
OE to Output Delay
0
0
0
ns
(3)(4)
tDF
CE or OE to Output Float
Output Hold from OE, CE or Address, Whichever Occurred First
55
ns
tOH
ns
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0299H–PEEPR–10/06
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
100
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
200
100
0
ns
tDS
ns
t
DH, tOEH
Data, OE Hold Time
Time to Data Valid
ns
tDV
NR(1)
tWPH
Write Pulse Width High
100
ns
Notes: 1. NR = No Restriction
2. All byte write operations must be preceded by the SDP command sequence.
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
8
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
16. Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
ns
tBLC
tWPH
100
µs
100
ns
17. Write Algorithm(1)
LOAD DATA AA
TO
ADDRESS 1555
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD DATA A0
TO
ADDRESS 1555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(3)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex).
2. Data protect state will be re-activated at the end of the write cycle.
3. 1 to 64 bytes of data are loaded.
9
0299H–PEEPR–10/06
18. Software Data Protection Write Cycle Waveforms(1)(2)(3)
Notes: 1. A0 - A12 must conform to the addressing sequence for the first three bytes as shown above.
2. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
3. OE must be high only when WE and CE are both low.
19. Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
0
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
20. Data Polling Waveforms
10
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
21. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
22. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used, but the address should not vary.
11
0299H–PEEPR–10/06
23. Ordering Information(1)
23.1 Standard Package
I
CC (mA)
Standby
0.05
tACC
(ns)
Active
15
Ordering Code
Package
Operation Range
200
AT28BV64B-20JI
AT28BV64B-20PI
AT28BV64B-20SI
AT28BV64B-20TI
32J
Industrial
28P6
28S
28T
(-40° C to 85°C)
Note:
1. See “Valid Part Numbers” below.
23.2 Green Package Option (Pb/Halide-free)
I
CC (mA)
Standby
0.05
tACC
(ns)
Active
15
Ordering Code
Package
Operation Range
200
AT28BV64B-20JU
AT28BV64B-20TU
AT28BV64B-20SU
32J
28T
28S
Industrial
(-40° C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28S
28T
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
24. Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
Speed
Package and Temperature Combinations
JI, JU, PI, SI, SU, TI, TU
AT28BV64B
20
12
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
25. Packaging Information
25.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
13
0299H–PEEPR–10/06
25.2 28P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
36.703
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
37.338 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
28P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
14
AT28BV64B
0299H–PEEPR–10/06
AT28BV64B
25.3 28S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
PIN 1
1.27(0.50) BSC
TOP VIEW
18.10(0.7125)
17.70(0.6969)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
0º ~ 8º
1.27(0.050)
0.40(0.016)
8/4/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
28S
B
R
15
0299H–PEEPR–10/06
25.4 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
16
AT28BV64B
0299H–PEEPR–10/06
Atmel Corporation
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