AT25040B [ATMEL]
f serial electrically erasable able programmable read-only memory; F串行电可擦除可编程能够只读存储器
| 型号： | AT25040B |
| 厂家： | 
ATMEL |
| 描述： | f serial electrically erasable able programmable read-only memory |
| 文件： | 总27页 (文件大小：1417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– VCC = 1.8V to 5.5V
• 20 MHz Clock Rate (5V)
• 8-byte Page Mode
• Block Write Protection
SPI Serial
EEPROM
1K (128x8)
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
2K (256x8)
• Green (Pb/Halogen-free/Rohs Compliant) Packaging Options
• Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
4K (512x8)
Description
AT25010B
AT25020B
AT25040B
The AT25010B/020B/040B provides 1024/2048/4096 bits of serial electrically eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words
of 8 bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The
AT25010B/020B/040B is available in space saving, JEDEC SOIC, UDFN, TSSOP,
XDFN and VFBGA packages.
Preliminary
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 0-1.
Pin Configuration
SOIC, TSSOP
Pin Name
CS
Function
CS
SO
VCC
1
2
3
4
8
7
6
5
Chip Select
HOLD
SCK
SI
WP
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
GND
SO
8-lead UDFN, XDFN
8-ball VFBGA
GND
VCC
8
7
6
5
1
2
3
4
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
VCC
HOLD
SCK
SI
CS
Power Supply
Write Protect
SO
SO
WP
WP
GND
WP
GND
HOLD
Suspends Serial Input
8707B–SEEPR–3/10
Bottom View
Bottom View
1.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under
Operating Temperature40°C to + 125°C
Storage Temperature65°C to + 150°C
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional opera-
tion of the device at these or any other
conditions beyond those indicated in the
operational sections of this specification
is not implied. Exposure to absolute max-
imum rating conditions for extended peri-
ods may affect device reliability.
Voltage on Any Pin
with Respect to Ground1.0V to + 7.0V
Maximum Operating Voltage6.25V
DC Output Current5.0 mA
Figure 1-1. Block Diagram
VCC
MEMORY ARRAY
128/256/512 X 8
ADDRESS
DECODER
STATUS
REGISTER
DATA
REGISTER
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
2
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
Table 1-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 1-2.
Applicable over recommended operating range from: TAI = 40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted)
DC Characteristics(1)
Symbol
VCC1
VCC2
VCC3
ICC1
ICC2
ICC3
ISB1
Parameter
Test Condition
Min
1.8
2.5
4.5
Typ
Max
5.5
5.5
5.5
10.0
5.0
3.0
0.5
1.0
3.5
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
V
V
VCC = 5.0V at 20 MHz, SO = Open, Read
VCC = 5.0V at 10 MHz, SO = Open, Read, Write
VCC = 5.0V at 1 MHz, SO = Open, Read, Write
VCC = 1.8V, CS = VCC
8.5
4.5
2.0
0.1
0.2
2.0
mA
mA
mA
µA
µA
µA
µA
µA
V
ISB2
VCC = 2.5V, CS = VCC
ISB3
VCC = 5.0V, CS = VCC
IIL
VIN = 0V to VCC
3.0
3.0
IOL
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
IOL = 3.0 mA
3.6V VCC 5.5V
V
IOH = 1.6 mA
VCC 0.8
VCC 0.2
V
IOL = 0.15 mA
1.8V VCC 3.6V
0.2
V
IOH = 100 µA
V
Note:
1. VIL min and VIH max are reference only and are not tested.
3
8707B–SEEPR–3/10
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = 40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
tFI
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
CS Setup Time
CS Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
4.5 5.5
2.5 5.5
1.85.5
20
40
80
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 5.5
2.5 - 5.5
1.8 - 5.5
20
40
80
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
tHD
tCD
tV
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
40
80
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
tHO
Output Hold Time
Hold to Output Low Z
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
25
50
100
tLZ
4
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
Table 1-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = 40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
tHZ
Hold to Output High Z
ns
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
tDIS
Output Disable Time
ns
4.5 5.5
2.5 5.5
1.8 5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
5.0V, 25C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
2.
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25010B/020B/040B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte con-
tains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both
the read and write instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010B/020B/040B, and
the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This
will reinitialize the serial communication.
CHIP SELECT: The AT25010B/020B/040B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When the device
is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK
pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still
toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010B/020B/040B. If the internal write cycle has
already been initiated, WP going low will have no effect on any write operation.
5
8707B–SEEPR–3/10
Figure 2-1. SPI Serial Interface
AT25010B/020B/040B
6
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
3.
Functional Description
The AT25010B/020B/040B is designed to interface directly with the synchronous serial peripheral interface (SPI) of
the 6805 and 68HC11 series of microcontrollers.
The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes
are contained in Figure 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Table 3-1.
Instruction Set for the AT25010B/020B/040B
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 A011
WRITE
0000 A010
Note:
“A” represents MSB address bit A8.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during
a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 0 (RDY)
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
Bit 2 (BP0)
Bit 3 (BP1)
See Table 3-4.
See Table 3-4.
Bits 4–7 are “0”s when device is not in an internal write cycle.
Bits 0–7 are “1”s during an internal write cycle.
7
8707B–SEEPR–3/10
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-
tion. The AT25010B/020B/040B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4.
Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells
(e.g., WREN, tWC, RDSR).
Table 3-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25010B
AT25020B
None
AT25040B
0
0
1
1
0
1
0
1
None
607F
407F
007F
None
1 (1/4)
2 (1/2)
3 (All)
C0FF
80FF
180FF
1001FF
0001FF
00FF
READ SEQUENCE (READ): Reading the AT25010B/020B/040B via the SO pin requires the following sequence.
After the CS line is pulled low to select a device, the read op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address to be read (A7A0). Upon completion, any data on the SI line will be ignored. The data
(D7D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010B/020B/040B, the Write Protect pin (WP) must be
held high and two separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be
programmed must be outside the protected address field location selected by the block write protection level. Dur-
ing an internal write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code (including A8) is transmitted via the SI line followed by the byte address (A7A0) and the data (D7D0) to
be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The ready/busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If
Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is
enabled during the write programming cycle.
The AT25010B/020B/040B is capable of an 8-byte page write operation. After each byte of data is received, the
three low-order address bits are internally incremented by one; the six high-order bits of the address will remain
constant. If more than 8 bytes of data are transmitted, the address counter will roll over and the previously written
data will be overwritten. The AT25010B/020B/040B is automatically returned to the write disable state at the com-
pletion of a write cycle.
Note:
If the WP pin is brought low or if the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
8
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
4.
Timing Diagrams
Figure 4-1. Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
VALID IN
SI
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 4-2. WREN Timing
CS
SCK
SI
WREN OP-CODE
HI-Z
SO
Figure 4-3. WRDI Timing
CS
SCK
SI
WRDI OP-CODE
HI-Z
SO
9
8707B–SEEPR–3/10
Figure 4-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Figure 4-5. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
DATA IN
INSTRUCTION
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 4-6. READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
8
7
6
5
4
3
2
1
0
9th BIT OF ADDRESS
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
10
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
Figure 4-7. WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA IN
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
9th BIT OF ADDRESS
HIGH IMPEDANCE
SO
Figure 4-8. HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
11
8707B–SEEPR–3/10
5.
Ordering Code Detail
A T 2 5 0 1 0 B - S S H L - B
Atmel Designator
Product Family
Device Density
Shipping Carrier Option
B or blank = Bulk (tubes)
T
= Tape and reel
Operating Voltage
L
= 1.8V to 5.5V
Package Device Grade or
Wafer/Die Thickness
010 = 1k
020 = 2k
040 = 4k
H
=
Green, NiPdAu lead finish,
Industrial Temperature Range
(-40˚C to +85˚C)
Device Revision
U
=
Green, matte Sn lead finish,
Industrial Temperature range
(-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
SS = JEDEC SOIC
X
= TSSOP
MA = UDFN
ME = XDFN
C
= VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
12
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
6.
Part Markings
AT25010B-SSHL
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 1 B L
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
AT25010B-XHL
PIN 1 INDICATOR(DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 1 B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
AT25010B-CUL
|---|---|---|---|
5 1 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
LINE 1: 51B=AT25010B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
13
8707B–SEEPR–3/10
AT25010B-MAHL
|---|---|---|
5 1 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 51B=AT25010B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 3: Y=DATE CODE, XX=TRACE CODE
AT25010B-MEHL
|---|---|---|
5 1 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 51B=AT25010B
LINE 2: Y=DATE CODE, XX=TRACE CODE
AT25020B-SSHL
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
5 2 B
L
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 52B=AT25020B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
14
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
AT25020B-XHL
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 2 B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 52B=AT25020B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
AT25020B-CUL
|---|---|---|---|
5 2 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
LINE 1: 52B=AT25020B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
AT25020B-MAHL
|---|---|---|
5 2 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 52B=AT25020B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 3: Y=DATE CODE, XX=TRACE CODE
15
8707B–SEEPR–3/10
AT25020B-MEHL
|---|---|---|
5 2 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 52B=AT25020B
LINE 2: Y=DATE CODE, XX=TRACE CODE
AT25040B-SSHL
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 4 B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 54B=AT25040B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
AT25040B-XHL
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
5 4 B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 54B=AT25040B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
LINE 3: ATMEL LOT NUMBER
16
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
AT25040B-CUL
|---|---|---|---|
5 4 B U
|---|---|---|---|
Y M X X
|---|---|---|---|
|<-- PIN 1 THIS CORNER
LINE 1: 54B=AT25040B, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=TRACE CODE
AT25040B-MAHL
|---|---|---|
5 4 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
PIN 1 INDICATOR (DOT)
LINE 1: 54B=AT25040B
LINE 2: H=MATERIAL SET/GRADE, L=1.8 to 5.5V, @=COUNTRY OF ORIGIN
LINE 2: Y=DATE CODE, XX=TRACE CODE
AT25040B-MEHL
|---|---|---|
5 4 B
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 54B=AT25040B
LINE 2: Y=DATE CODE, XX=TRACE CODE
17
8707B–SEEPR–3/10
7.
Ordering Codes
AT25010B Ordering Information(1)
Ordering Code
Voltage
Package
Operation Range
AT25010B-SSHL-B(1) (NiPdAu Lead Finish)
AT25010B-SSHL-T(2) (NiPdAu Lead Finish)
AT25010B-XHL-B(1) (NiPdAu Lead Finish)
AT25010B-XHL-T(2) (NiPdAu Lead Finish)
AT25010B-MAHL-T(2) (NiPdAu Lead Finish)
AT25010B-MEHL-T(2) (NiPdAu Lead Finish)
AT25010B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/
Industrial Temperature
8MA2
8ME1
8U3-1
(40 to 85C)
Industrial Temperature
AT25010B-WWU11L(3)
1.8V to 5.5V
Die Sale
(40 to 85C)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Package Type
8S1
8A2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8-lead (1.80x2.20mm body) Extra Thin DFN (XDFN)
8MA2
8ME1
8U3-1
8-ball die Ball Grid Array (VFBGA)
18
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
AT25020B Ordering Information(1)
Ordering Code
Voltage
Package
Operation Range
AT25020B-SSHL-B(1) (NiPdAu Lead Finish)
AT25020B-SSHL-T(2) (NiPdAu Lead Finish)
AT25020B-XHL-B(1) (NiPdAu Lead Finish)
AT25020B-XHL-T(2) (NiPdAu Lead Finish)
AT25020B-MAHL-T(2) (NiPdAu Lead Finish)
AT25020B-MEHL-T(2) (NiPdAu Lead Finish)
AT25020B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/
Industrial Temperature
8MA2
8ME1
8U3-1
(40 to 85C)
Industrial Temperature
AT25020B-WWU11L(3)
1.8V to 5.5V
Die Sale
(40 to 85C)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Package Type
8S1
8A2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8-lead (1.80x2.20mm body) Extra Thin DFN (XDFN)
8-ball die Ball Grid Array (VFBGA)
8ME1
8U3-1
19
8707B–SEEPR–3/10
AT25040B Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT25040B-SSHL-B(1) (NiPdAu Lead Finish)
AT25040B-SSHL-T(2) (NiPdAu Lead Finish)
AT25040B-XHL-B(1) (NiPdAu Lead Finish)
AT25040B-XHL-T(2) (NiPdAu Lead Finish)
AT25040B-MAHL-T(2) (NiPdAu Lead Finish)
AT25040B-MEHL-T(2) (NiPdAu Lead Finish)
AT25040B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8A2
8A2
Lead-free/Halogen-free/
Industrial Temperature
8MA2
8ME1
8U3-1
(40 to 85C)
Industrial Temperature
AT25040B-WWU11L(3)
1.8V to 5.5V
Die Sale
(40 to 85C)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube).
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel).
3. Contact Atmel Sales for Wafer sales.
Package Type
8S1
8A2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
8-lead, 1.80mm x 2.20mm Body, Extra Thin DFN (XDFN)
8-ball die Ball Grid Array (VFBGA)
8MA2
8ME1
8U3-1
20
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
8.
Packaging Information
8S1 – JEDEC SOIC
C
GND
4
NC
3
NC
2
NC
1
E
E1
L
5
6
7
8
SDA
SCL
NC
VCC
Ø
Top View
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
1.35
0.10
0.31
0.17
4.80
3.81
5.79
NOM
MAX
1.75
0.25
0.51
0.25
5.05
3.99
6.20
NOTE
A1
A
–
A1
b
–
–
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
Notes: 1. These drawings are for general information only. Refer
to JEDEC Drawing MS-012, Variation AA for proper
dimensions, tolerances, datums, etc.
1.27
8˚
L
0.40
0˚
–
–
θ
12/11/09
TITLE
GPC
SWB
DRAWING NO.
REV.
8S1, 8-lead, (0.150” Wide Body),
packagedrawings@atmel.com Plastic Gull Wing Outline (JEDEC SOIC)
Package Drawing Contact:
8S1
E
21
8707B–SEEPR–3/10
8A2 – TSSOP
4
3
2 1
GND NC NC NC
A
Pin 1 indicator
this corner
b
E1
E
e
A2
L1
D
Side View
SDA SCL NC VCC
5
6
7 8
L
Top View
End View
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
COMMON DIMENSIONS
(Unit of Measure = mm)
2. Dimension
D
does not include mold Flash,
protrusions or gate burrs. Mold Flash, protrusions and
gate burrs shall not
exceed 0.15 mm (0.006 in) per side.
SYMBOL
MIN
NOM
3.00
MAX
NOTE
13.10
2, 5
D
2.90
3. Dimension E1 does not include inter-lead Flash or
protrusions. Inter-lead Flash and protrusions shall not
exceed 0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion
and adjacent lead is 0.07 mm.
E
6.40 BSC
4.40
4.50
1.20
1.05
0.30
3, 5
4
E1
A
4.30
–
–
A2
b
0.80
0.19
1.00
–
e
0.65 BSC
0.60
0.75
L
0.45
5. Dimension D and E1 to be determined at Datum
Plane H.
L1
1.00 RE3
12/11/09
TITLE
GPC
TNR
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8A2, 8-lead, 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
8A2
D
22
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
8MA2 – UDFN
E
1
2
3
4
8
7
Pin 1 ID
D
6
5
C
A2
A1
A
E2
b (8x)
8
7
6
1
COMMON DIMENSIONS
(Unit of Measure = mm)
Pin#1 ID
(R0.10)
2
3
4
0.35
D2
SYMBOL
MIN
NOM
2.00 BSC
3.00 BSC
1.50
MAX
NOTE
D
E
5
1.60
1.40
0.60
0.05
0.55
D2
E2
A
1.40
1.20
0.50
0.00
–
e (6x)
1.30
L (8x)
K
0.55
A1
A2
C
0.02
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229 for proper dimensions,
tolerances, datums, etc.
–
0.152 REF
0.35
2. The terminal #1 ID is a laser-marked feature.
3. Dimensions b applies to metalized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should not
be measured in that radius area.
0.40
L
0.30
e
0.50 BSC
0.25
0.30
–
3
b
0.18
0.20
K
–
4/15/08
TITLE
GPC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
YNZ
8MA2
A
23
8707B–SEEPR–3/10
8ME1 – XDFN
e1
D
b
8
7
6
5
L
E
PIN #1 ID
0.10
PIN #1 ID
0.15
1
2
3
4
A1
b
e
A
Top View
Side View
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
NOM
–
MAX
0.40
0.05
1.90
2.30
0.25
NOTE
A
A1
D
E
0.00
1.70
2.10
0.15
–
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.35
0.26
8/3/09
TITLE
GPC
DRAWING NO.
REV.
8ME1, 8-lead (1.80 x 2.20 mm Body)
Extra Thin DFN (XDFN)
Package Drawing Contact:
packagedrawings@atmel.com
DTP
8ME1
A
24
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
AT25010B/020B/040B [Preliminary]
8U3-1 – VFBGA
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
Top View
A2
A
End View
PIN 1 BALL PAD CORNER
1
2
3
4
(d1)
d
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
0.73
0.09
0.40
0.20
NOM
0.79
MAX
0.85
0.19
0.50
0.30
NOTE
A
A1
A2
b
0.14
8
7
6
5
0.45
e
2
0.25
Bottom View
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
(e1)
(8 SOLDER BALLS)
E
e
Notes: 1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder
ball diameter.
e1
d
d1
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu
9/19/07
TITLE
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
VFBGA Package (dBGA2)
PO8U3-1
C
25
8707B–SEEPR–3/10
9.
Revision History
Doc. Rev.
8707B
Date
Comments
3/2010
2/2010
Replace 8Y6 with 8MA2
Initial document release
8707A
26
AT25010B/020B/040B [Preliminary]
8707B–SEEPR–3/10
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International
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trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
8707B–SEEPR–3/10
相关型号：
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EEPROM, 512X8, Serial, CMOS, PBGA8, 1.50 X 2 MM, 0.50 MM PITCH, GREEN, VFBGA-8
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EEPROM, 512X8, Serial, CMOS, PDSO8, 2 X 3 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MO-229, UDFN-8
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