APA3175 [ANPEC]
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC;
| 型号： | APA3175 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC |
| 文件： | 总46页 (文件大小：811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APA3175
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
·
·
Operating Voltage: 4.5V~24V for PVDD
The APA3175 is a digital input, stereo, high efficiency,
Class-D audio amplifier available in a TQFP7x7-48P
package.
– 3.0V~3.6V for DVDD and AVDD
High Efficiency Class-D Operation Eliminate the
Need of Heatsinks
The APA3175 accepts the digital serial audio data and
using the digital audio processor to convert the audio
data becomes the stereo Class-D output speaker
amplifier. This provides the seamless integration between
the codec and the speaker amplifier.
·
·
·
·
·
·
Digital Serial Audio Input (Stereo Output)
I2C Control Interface
Sampling Rate can Support from 32kHz to 192kHz
Separated Volume Control from 24dB to Mute
Soft Mute (50% Duty Cycle)
The APA3175 is a slave device receiving clocks from ex-
ternal source, and the Class-D’s PWM switching fre-
quency is 352.8kHz for the sampling rate 44.1kHz or 384
kHz for sampling 48kHz, depend on the input signal’s
sampling rate.
Programmable Dynamic Range Compression
– Power Limiter
– Speaker Protection
– Night-Mode Listening
·
·
·
Programmable Biquads for Speaker EQ
Shutdown and Mute Function
Thermal and Over-Current Protections with Auto-
Recovery
Pin Configuration
·
·
Space Saving Package TQFP7x7-48P
Lead Free and Green Devices Available
(RoHS Compliant)
OUT_A 1
PVDD_A 2
PVDD_A 3
ABS 4
36 OUT_D
35 PVDD_D
34 PVDD_D
33 DBS
Applications
GDREG 5
NC 6
32 GDREG
31 DVREG
30 AGND
29 GND
·
LCD TV
TOP VIEW
(APA3175)
NC 7
TM 8
AVSS 9
PLL_LF 10
28 DVSS
27 DVDD
26 TP3
Simplified Application Circuit
NC 11
NC 12
25 /RST
OUT_A
OUT_B
MCLK
LRCLK
SCLK
SDIN
Left
Channel
Speaker
Digital Audio
Source
APA3175
OUT_C
Right
I2C
Control
SDA
SCL
Channel
Speaker
OUT_D
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Aug., 2016
APA3175
Ordering and Marking Information
Package Code
APA3175
QCA : TQFP7x7-48P
Operating Ambient Temperature Range
I : -40 to 85 oC
Assembly Material
Handling Code
Handling Code
TR : Tape & Reel
Assembly Material
Temperature Range
Package Code
G : Halogen and Lead Free Device
APA3175
XXXXX
APA3175 QCA :
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Supply Voltage (PVDD_X to PGND_XX)
Supply Voltage (DVDD to DVSS)
Rating
-0.3 to 26
Unit
-0.3 to 3.6
Supply Voltage (AVDD to AVSS)
-0.3 to 3.6
Input Voltage (MCLK to AVSS)
-0.5 to AVDD+2.5
V
Input Voltage (SD, RST, LRCLK, SCLK, SDIN, SDA, SCL to DVSS)
Input Voltage (OUT_X to PGND_XX)
Input Voltage (XBS to PGND_XX)
-0.5 to DVDD+2.5
-0.3 to +26
-0.3 to +31
-0.3 to +0.3
150
Input Voltage (AVSS, DVSS, AGND to PGND_XX)
Maximum Junction Temperature
oC
oC
oC
W
TJ
TSTG
TSDR
PD
Storage Temperature Range
-65 to +150
260
Soldering Temperature Range, 10 seconds
Power Dissipation
Internally Limited
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air (Note 2)
25
qJA
°C/W
TQFP7x7-48P
TQFP7x7-48P
Thermal Resistance Junction-to-Case (Note 3)
3
qJC
°C/W
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFP7X7-48P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFP7X7-48P package.
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APA3175
Recommended Operating Conditions
Range
Symbol
Parameter
Unit
Min.
3
Max.
3.6
VDD
Supply Voltage
Full Bridge Stage Supply Voltage (PVDD_X)
PVDD
4.5
24
SD, MCLK, LRCLK, SCLK, SDIN,
V
VIH
VIL
High Level Threshold Voltage
Low Level Threshold Voltage
2
0
5
1
SDA, SCL, RST
SD, MCLK, LRCLK, SCLK, SDIN,
SDA, SCL, RST
TA
TJ
Ambient Temperature Range
Junction Temperature Range
-40
-40
4.8
3.2
10
85
oC
125
PVDD>15V
-
-
-
RL
LO
Speaker Resistance
W
PVDD<15V
Output Low Pass Filter Inductance
mH
PWM Operating Conditions
Symbol
Parameter
Test Conditions
Value
256
Unit
32 kHz Data Rate ±2%
fS
Output Sample Rate
44.1k/88.2k/176.4 kHz Data Rate ±2%
48k/96k/192 kHz Data Rate ±2%
352.8
384
kHz
PLL Input Parameters and External Filter Components
APA3175
Symbol
Parameter
Test Conditions
Unit
Min.
2.8224
40
Typ.
Max.
fMCLK
MCLK Frequency
-
50
-
24.576
MHz
%
MCLK Duty Cycle
60
5
tr/tf (MCLK)
Rise/Fall Time for MCLK
-
ns
LRCLK Allowable Drift before
LRCLK Reset
-
-
4
MCLKs
External PLL Filter Capacitor C1
External PLL Filter Capacitor C2
External PLL Filter Resistor R
SMD 0603 Y5V
SMD 0603 Y5V
-
-
-
47
4.7
470
-
-
-
nF
W
Electrical Characteristics
TA=25oC, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8W, BD Mode, fS=48kHz (unless otherwise noted)
APA3175
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
DC CHARACTERISTICS
Normal Mode (No load)
Reset (No load)
-
-
-
-
10
7.2
18
20
14.5
36
3.3V Supply Current (AVDD,
DVDD)
IDD
mA
Normal Mode (No load)
Reset (No load)
Full Bridge Stage Supply
Current (PVDD_X)
IPVDD
0.5
1
VI<VIL, VDD=3.6V (AVDD and
DVDD)
IIL
Low Level Input Current
-
150
-
m
A
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APA3175
Electrical Characteristics (Cont.)
TA=25oC, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8W, BD Mode, fS=48kHz (unless otherwise noted)
APA3175
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
DC CHARACTERISTICS (CONT.)
VI>VIH, VDD=3.6V (AVDD and
DVDD)
TJ=25oC, includes m etallization
resistance
TJ=25oC, includes m etallization
resistance
I
High Level Input Current
-
-
150
180
-
-
mA
IH
Drain to source resistance,LS
mW
mW
rDS(ON)
Drain to source resistance,HS
Thermal Protection Threshold
-
-
180
160
-
170
oC
TTP
Thermal Protection Threshold
Hysteresis
-
-
-
25
88
3
-
-
-
Efficiency
%
h
Stereo, RL=8W, PO=18W
Internal Pull-Down Resistance at
Each OUT_X
ROUT
kW
AC CHARACTERISTICS
PVDD=18V
14.5
6.5
2.9
0.9
16
7.2
3.2
1
-
-
-
-
THD+N=1%
PVDD=12V
fin=1kHz,
RL=8W
PVDD=8V
PVDD=4.5V
THD+N=1%
fin=1kHz,
RL=6W
PVDD=12V
8.1
9
-
PVDD=12V
PVDD=8V
8.9
10
4.6
1.4
20
-
-
-
-
-
-
-
THD+N=1%
fin=1kHz,
RL=4W
4.1
PVDD=4.5V
PVDD=18V
PVDD=12V
PVDD=8V
1.1
PO
Output Power
W
-
-
-
-
THD+N=10%
fin=1kHz,
RL=8W
9
4
PVDD=4.5V
1.25
THD+N=10%
fin=1kHz,
PVDD=12V
-
11
-
RL=6W
PVDD=12V
PVDD=8V
-
-
-
14.3
6.5
-
-
-
THD+N=10%
fin=1kHz,
RL=4W
PVDD=4.5V
2.08
PVDD=18V,
PO=1W
-
-
-
0.06
0.13
0.2
-
-
-
fin=1kHz,
RL=8W
Total Harmonic Distortion Plus
Noise
PVDD=12V,
PO=1W
THD+N
%
PVDD=8V,
PO=1W
Crosstalk
AttMute
Channel Separation
Mute Attenuation
PO=0.25W, RL=8W, fin=1kHz
fin=1kHz, RL=8W, VO=1Vrms
fin=1kHz, RL=8W, VO=1Vrms
-
-
-
-82
-70
-
-
-
dB
Attshutdown
Shutdown Attenuation
-110
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APA3175
Electrical Characteristics (Cont.)
TA=25oC, PVDD=18V, VDD=3.3V (AVDD and DVDD), RL=8W, BD Mode, fS=48kHz (unless otherwise noted)
APA3175
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
AC CHARACTERISTICS
RL=8W, PO=16W, With
A-Weighting Filter (AV=0dB)
S/N
Vn
Signal to Noise Ratio
Noise Output Voltage
-
-
97
-
-
dB
With A-Weighting Filter (AV=0dB)
150
mVrms
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
APA3175
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Vn
Noise Output Voltage
With A-Weighting Filter (AV=0dB)
CL=30pF
-
150
-
mVrms
Frequency, SCLK 32xfS, 48xfS,
64xfS
fSCLK
tSetup1
tHold1
1.024
10
-
-
-
12.288
MHz
Setup Time, LRCLK to SCLK
Rising Edge
-
-
ns
Hold Time, LRCLK to SCLK
Rising Edge
10
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
APA3175
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Setup Time, SDIN to SCLK
Rising Edge
tSetup2
tHold
10
-
-
-
ns
Hold Time, SDIN to SCLK Rising
Edge
10
-
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
8K
40
40
48K
50
48K
60
kHz
%
50
60
SCLK Rising Edges Between
LRCLK Riding Edges
SCLK
edges
32
-1/4
-
-
-
-
64
1/4
8
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
SCLK
period
t(edge)
tr/tf
(SCLK/LRCLK)
Rise/Fall Time for SCLK/LRCLK
ns
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
APA3175
Symbol
Parameter
Test Conditions
Unit
Min.
100
-
Typ.
Max.
-
tp(RST)
Pulse Duration, RST Active.
Time to Enable I2C
No Load
-
-
ms
td(12C_Ready)
13.5
ms
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APA3175
I2C Serial Control Port Operation
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
APA3175
Symbol
Parameter
Frequency, SCL
Test Conditions
No Wait States
Unit
kHz
ms
Min.
-
Typ.
Max.
fSCL
tW(H)
tW(L)
tr
-
-
-
-
-
-
-
400
Pulse Duration, SCL High
Pulse Duration, SCL Low
Rise Time, SCL and SDA
Fall Time, SCL and SDA
Setup Time, SCL to SDA
Hold Time, SCL to SDA
0.6
1.3
-
-
-
300
300
-
tf
-
ns
tsetup1
thold1
100
0
-
Bus Free Time Between Stop
and Start Condition
t(buf)
1.3
-
-
Setup Time, SCL to Start
Condition
tsetup2
thold2
0.6
0.6
0.6
-
-
-
-
-
-
ms
Hold Time, Start condition to SCL
Setup Time, SCL to Stop
Condition
tsetup3
Load Capacitance for Each Bus
Line
-
-
400
pF
CL
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APA3175
Typical Operating Characteristics
THD+N vs. Frequency
THD+N vs. Frequency
10
1
10
1
Po=2.5W
Po=0.5W
Po=5W
0.1
0.1
Po=1W
0.01 PVDD=12V
RL=8W
PVDD=18V
RL=8W
0.01
AUX-0025
AES-17(20kHz)
AUX-0025
AES-17(20kHz)
0.001
20
0.001
1k
50 100
500
2k
5k
20k
20
50
1k 2k
500
5k
20k
100
Frequency (Hz)
Frequency (Hz)
THD+N vs. Frequency
THD+N vs. Frequency
10
1
10
1
Po=1W
Po=2.5W
Po=1W
Po=0.1W
0.1
0.1
Po=0.5W
PVDD=4.5V
RL=8W
AUX-0025
AES-17(20kHz)
PVDD=8V
RL=8W
AUX-0025
AES-17(20kHz)
0.001
0.001
20
50
1k 2k
500
5k
20k
20
50
1k 2k
500
5k
20k
100
100
Frequency (Hz)
Frequency (Hz)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
1
Fin=10kHz
Fin=1kHz
Fin=20Hz
1
Fin=10kHz
Fin=1kHz
Fin=20Hz
0.
1
0.1
0.01
0.01 VDD=12V
RL=8W
VDD=18V
RL=8W
AUX-0025
AUX-0025
AES-17(20kHz)
AES-17(20kHz)
0.001
0.001
10m
2
5
10 20 50
2
5 10 20 50
10m
100m
1
100m
1
Output Power (W)
Output Power (W)
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APA3175
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
1
10
VDD=4.5V
RL=8W
AUX-0025
AES-17(20kHz)
VDD=8V
RL=8W
AUX-0025
AES-17(20kHz)
1
0.1
0.1
Fin=20Hz
Fin=1kHz
Fin=10kHz
0.01
0.01
0.001
0.001
10m
100m
1
5
2
5 10 20 50
10m
100m
1
Output Power (W)
Output Power (W)
Efficiency vs. Output Power
Output Power vs. Supply Voltage
100
90
20
18
RL=8W
Duty=97.7%
PVDD=24V
PVDD=18V
80
70
60
16
14
PVDD=12V
PVDD=8V
12
10
8
50
40
30
20
10
PVDD=4.5V
THD+N=10%
6
4
RL=8W
Duty=97.7%
THD+N=1%
2
0
4
0
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28
20
15
16 17 18 19
5
6
7
8
9 10 11
12
13 14
Supply Voltage(V)
Output Power / Per Channel (W)
Crosstalk vs. Frequency
Crosstalk vs. Frequency
0
0
PVDD=12V
Po=0.25W
RL=8W
AUX-0025
10~22kHz
PVDD=18V
Po=0.25W
RL=8W
AUX-0025
10~22kHz
-20
-20
-40
-60
-80
-40
-60
-80
Right to Left
Left to Right
Right to Left
Left to Right
-100
-120
-100
-120
500 1k 2k
5k
20k
20
50 100 200
2k
500 1k
5k
20k
20
50 100 200
Frequency (Hz)
Frequency (Hz)
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APA3175
Typical Operating Characteristics
Crosstalk vs. Frequency
Crosstalk vs. Frequency
0
0
PVDD=8V
Po=0.25W
RL=8W
AUX-0025
10~22kHz
PVDD=4.5V
Po=0.25W
RL=8W
AUX-0025
10~22kHz
-20
-40
-60
-80
-20
-40
-60
-80
Left to Right
Right to Left
Right to Left
Left to Right
-100
-120
-100
-120
500 1k 2k
5k
20k
50
200
100
20
500 1k 2k
5k
20k
20
50 100 200
Frequency (Hz)
Frequency (Hz)
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APA3175
Pin Description
PIN
I/O/P
FUNCTION
NO.
NAME
OUT_A
PVDD_A
ABS
1
O
P
Output of half bridge A.
2, 3
Power supply for half bridge A.
4
5, 32
6,7,11,12
8
I/O
O/P
-
High side bootstrap supply for half bridge A.
Internal regulator output of gate driver.
No connection.
GDREG
NC
TM
I
Test mode digital input pin.
10
PLL_LF
AVDD
O
PLL negative loop filter pin.
13
P
Analog powers supply and connects to 3.3V.
When over temperature, over current over voltage and under voltage occur, this pin will
be pull low; and it will be reset to high when the fault condition has be remove.
14
O
ERROR
15
16
17
18
MCLK
TP1
I
Master clock input.
I/O
I/O
O/P
Test mode digital input/output pin.
TP2
Test mode digital input/output pin.
1V8_DV
SD
Internal regulated 1.8V for digital block’s supply, Not for power external device.
19
20
21
22
23
24
I
I
Active LOW, Shutting down the noise shaper and initiating PWM stop sequence.
Input serial audio data left/right clock. (Sample rate clock), it’s weak pull down terminal.
Serial audio data clock (shift clock). SCLK is the serial audio port input data bit clock.
Serial audio data input.
I2C serial control data interface input/output.
I2C serial control clock input.
LRCLK
SCLK
SDIN
SDA
I
I
IO
I
SCL
Reset control, place a logic low to this pin, will reset the APA3175 to its default condition.
It’s weak pull-up terminal.
25
I
RST
26
27
TP3
DVDD
DVSS
I/O
P
Test mode digital input/output pin.
Digital powers supply and connects to 3.3V.
Digital power supply’s ground.
28
P
29
GND
P
Power stage’s analog ground.
30
AGND
DVREG
DBS
P
Power stage’s analog ground.
31
O/P
I/O
P
Digital voltage regulator’s output, only for internal used.
High side bootstrap supply for half bridge D.
Power supply for half bridge D.
33
34, 35
36
PVDD_D
OUT_D
PGND_CD
OUT_C
PVDD_C
CBS
O
Output of half bridge D.
37, 38
39
P
Power Ground connection for half bridge C and D.
Output of half bridge C.
O
40, 41
42
P
Power supply for half bridge C.
I/O
I/O
High side bootstrap supply for half bridge C.
High side bootstrap supply for half bridge B.
43
BBS
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APA3175
Pin Description (Cont.)
PIN
I/O/P
FUNCTION
NO.
44, 45
46
NAME
PVDD_B
OUT_B
P
O
P
Power supply for half bridge B.
Output of half bridge B.
47, 48
PGND_AB
Power Ground connection for half bridge A and B.
Block Diagram
PVDD_A
BS_A
OUT_A
DVDD
1V8_DV
Regulator
3.3V to 1.8V
Half Bridge
A FET
Output
PGND_A
EQ 7XBQ
EQ 7XBQ
PGND_B
OUT_B
Serial
Audio
Port
Half Bridge
B FET
Output
Inter
Polarization
DRC &
Volume
SDIN
BS_B
PVDD_B
Fifth Order
Noise
Shaper and
PWM
VCMP_AB
VCMP_CD
DGND
MCLK
SCLK
LRCLK
PVDD_C
BS_C
Sampling
Rate
Half Bridge
C FET
Output
OUT_C
PGND_C
PGND_D
OUT_D
Half Bridge
D FET
Output
BS_D
PVDD_D
Central Control
PLL
PLL_LF
AVCC
Analog
Power
Stage
SDA
SCL
Register
Bank
control logic
Serial Control
Regulator
3.3V to 1.8V
BYPASS
AVSS
AGND
AVDD
1V8_AV
RST SD ERROR
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APA3175
Typical Application Circuit
470 Ω 0.047 μF
1μF
0.033μF
4700 pF
PVDD
22μH
A
A
AVDD
F
G
_
_
A
L
E
_
0.68μF
0.68μF
S
D
D
_
220μF
0.1μF
R
T
S
S
D
D
L
10μF
0Ω
0.1μF
D
U
C
C
L
V
C
C
B
V
V
M
N
N
P
A
T
N
N
G
A
P
P
O
8Ω
AVDD
/ERROR
MCLK
TP1
TP2
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BBS
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
A_SEL
MCLK
22μH
10kΩ
0.1μF
PVDD
0.1μF
10kΩ 1V8_DV
0.033μF
0.033μF
APA3175
/SD
DBS
AVDD
4.7μF
0.1μF
/PDN
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
LRCLK
SCLK
SDIN
SDA
LRCK
SCLK
SDIN
22μH
SDA
SCL
0.68μF
0.68μF
SCL
PVDD
3
T
S
S
D
D
D
D
D
D
G
G
P
S
_
_
_
S
B
D
N
N
E
E
T
T
R
V
D
D
D
V
G
G
R
R
/
U
D
D
V
P
D
V
P
D
A
V
D
8Ω
O
D
0.1μF
220μF
G
22μH
/RESET
DVDD
0.1μF
0.033 μF
1μF
10μF
0.1μF
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Rev. A.3 - Aug., 2016
APA3175
Function Description
Clock And PLL
The APA3175 is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor
(DAP) provides all sample rates and MCLK rates which defined in the clock control register.
The APA3175 checks to verify that SCLK is a particular value of 32fS, 48fS, or 64fS. The DAP only provides a 1×fS LRCLK.
The timing relationship of these clocks to SDIN is shown in subsequent sections.
Serial Data Interface
Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3175 DAP
receives left-justified, right-justified, and I2S serial data formats with 16, 20, or 24 bit.
PWM Section
The APA3175 DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper
is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the
DAP and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff
frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and 48
kHz and can be enabled and disabled.
The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%.
I2C Compatible Serial Control Interface
The APA3175 DAP receives commands from a system controller through an I2C serial control slave interface. The
serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting
states. As an added feature, even though the MCLK is absent, the interface operates.
For status registers, the serial control interface provides both single-byte and multi-byte read and write operations;
and for the general control registers, they associated with the PWM.
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APA3175
Function Description (Cont.)
Serial Interface Control And Timing
I2S Timing
I2S timing uses LRCLK to define the data for the left channel and the right channel when the data being transmitted.
For the left channel, the LRCLK is low; for the right channel, the LRCLK is high. A bit clock running at 32, 48, or 64 × fS
is used to clock in the data. When the LRCLK signal changes state, there is a delay of one bit clock from the time which
the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP
masks unused trailing data bit positions.
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
SCLK
Left Channel
Right Channel
SCLK
MSB
LSB
MSB
LSB
24-Bit Mode
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
0
1
0
23 22
20-Bit Mode
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
19 18
16-Bit Mode
16-Bit Mode
15 14
15 14
Figure 1. I2S 64 fS Format
24 Clks
24 Clks
LRCLK (Note Reversed Phase)
SCLK
Left Channel
Right Channel
SCLK
MSB
24-Bit Mode
LSB
LSB
MSB
24-Bit Mode
23 22
17 16
13 12
9
5
1
8
4
0
5
1
4
0
3
2
1
0
23 22
17 16
13 12
9
5
1
8
4
0
5
4
0
3
2
1
20-Bit Mode
20-Bit Mode
19 18
19 18
1
16-Bit Mode
15 14
16-Bit Mode
15 14
9
8
9
8
Figure 2. I2S 48 fS Format
16 Clks
16Clks
Right Channel
LRCLK (Note Reversed Phase)
SCLK
Left Channel
SCLK
MSB
16-Bit Mode
LSB
LSB
MSB
16-Bit Mode
15 14 13 12 11 10
9
8
5
4
3
2
1
0
15 14 13 12 11 10
9
8
5
4
3
2
1
Figure 3. I2S 32 fS Format
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APA3175
Function Description (Cont.)
Left-Justified
Left-justified (LJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being
transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK is low. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines when LRCLK toggles. The data
is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.
32Clks
32Clks
LRCLK
SCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
LSB
MSB
24-Bit Mode
LSB
23 22
20-Bit Mode
19 18
9
5
1
8
4
0
5
1
4
0
1
0
23 22
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
16-Bit Mode
16-Bit Mode
15 14
15 14
Figure 4. Left-Justified 64 fS Format
24Clks
24 Clks
Right Channel
LRCLK
SCLK
Left Channel
SCLK
MSB
24-Bit Mode
LSB
LSB
MSB
24-Bit Mode
23 22
20-Bit Mode
19 18
17 16
13 12
9
5
1
8
4
0
5
4
0
3
2
1
0
23 22
20-Bit Mode
19 18
17 16
13 12
9
5
1
8
4
0
5
4
0
3
2
1
1
1
16-Bit Mode
15 14
16-Bit Mode
15 14
9
8
9
8
Figure 5. Left-Justified 48 fS Format
16Clks
16Clks
LRCLK
SCLK
Left Channel
Right Channel
SCLK
MSB
16-Bit Mode
LSB MSB
16-Bit Mode
LSB
13
15 14 13 12 11 10
9
8
5
4
3
2
1
0
15 14
12 11 10
9
8
5
4
3
2
1
0
Figure 6. Left-Justified 32 fS Format
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APA3175
Function Description (Cont.)
Right-Justified
Right-justified (RJ) timing uses LRCLK to define the data for the left channel and the right channel when the data
being transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK low. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. After LRCLK toggles, for 24bit data, the first bit of data appears on the data
8 bit-clock. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is
written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.
32 Clks
32 Clks
LRCLK
SCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
LSB
MSB
24-Bit Mode
LSB
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
0
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
0
20-Bit
Mode
20-Bit
Mode
0
0
0
0
16-Bit
Mode
16-Bit
Mode
Figure 7. Right-Justified 64 fS Format
24 Clks
24 Clks
LRCLK
SCLK
Right Channel
Left Channel
SCLK
LS
B
LS
B
MSB
24-Bit Mode
MSB
24-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
6
6
6
5
5
5
2
2
2
1
1
1
0
0
0
23 22
19 18
19 18
15 14
15 14
15 14
6
6
6
5
5
5
2
2
2
1
1
1
0
0
0
20-Bit
Mode
20-Bit
Mode
16-Bit
Mode
16-Bit
Mode
Figure 8. Right-Justified 48 fS Format
16Clks
16Clks
LRCLK
SCLK
Left Channel
Right Channel
SCLK
MSB
16-Bit Mode
LSB MSB
16-Bit Mode
LSB
15 14 13 12 11 10
9
8
5
4
3
2
1
0
15 14 13 12 11 10
9
8
5
4
3
2
1
0
Figure 9. Right-Justified 32 fS Format
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APA3175
Function Description (Cont.)
I2C Serial Control Interface
The APA3175 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol. Besides, it
provides both 100kHz and 400kHz data transfer rates to single and multiple bytes write and read operations.
This is a slave only device, and it doesn’t support a multi-master bus environment or wait state insertion. The function
of the control interface is to read device status and to program the registers of the device.
The DAP supports the standard-mode I2C bus operation (100kHz maximum) and the fast I2C bus operation (400kHz
maximum). Without I2C wait cycles, the DAP performs I2C operations.
General I2C Operation
The I2C bus uses SDA (data) and SCL (clock) to communicate between integrated circuits in a system. Data is
transferred on the bus serially one bit at a time. With the most significant bit (MSB) transferred first, the address and
data can be transferred in byte (8bit) format. In addition, each byte transferred on the bus is acknowledged by the
receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start
condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the SDA when the clock is high to indicate start and stop conditions. A high-to-low
transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must
occur within the low time of the clock. These conditions are shown in Figure 10. The master generates the 7bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The APA3175 holds SDA low during the acknowledge clock to indicate an acknowledgment. When this
occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA
and SCL signals to set the high level for the bus.
8-Bit Register Data for
Address (N)
8-Bit Register Data for
Address (N)
R/
W
SDA
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
SCL
Start
Stop
Figure 10. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word
transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in
Figure 10.
The 7bit address for APA3175 is 0011 010 (0x34). APA3175 address can be changed from 0x34 to 0x38 by writing 0x38
to device address register 0xF9.
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APA3175
Function Description (Cont.)
Single- and Multiple-Byte Transfers
The serial control interface supports single-byte and multiple-byte (R/W) operations for sub-addresses 0x00 to 0x1F.
However, for the sub-addresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write
operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the sub-address
assigned, as long as the master device continues to respond with acknowledges. If a particular sub-address does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that
are required for each specific sub-address.
Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APA3175
also supports sequential I2C addressing. For write transactions, if a sub-address is issued and followed by data for
that sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 sub-addresses is successfully received by the APA3175. For I2C sequential write transactions, the sub-
address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is
transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential
addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last sub-
address, the data for the last sub-address is discarded. However, if all other data written is accepted, only the
incomplete data is discarded.
Single-Byte Write
As shown in Figure 11, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer. For a write
data transfer, the R/W bit will be a 0. After receiving the correct I2C device address and the R/W bit, the DAP responds
with an acknowledge bit. And then, the master transmits the address byte or bytes corresponding to the APA3175
internal memory address being accessed. After receiving the address byte, the APA3175 responds with an acknowl-
edge bit again. Next, the master device transmits the data byte to be written to the memory address being accessed.
After receiving the data byte, the APA3175 again responds with an acknowledge bit. Finally, the master device trans-
mits a stop condition to complete the single-byte data write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/WACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Stop
Condition
I2C Device Address
and Read/ Write Bit
Data Byte
Sub-address
Figure 11. Single-Byte Write Transfer
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APA3175
Function Description (Cont.)
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are
transmitted by the master device to the DAP as shown in Figure 12. After receiving each data byte, the APA3175
responds with an acknowledge bit.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6
A2 A1 A0 ACK D7
D0 ACK D7
D0 ACK D7
Stop
Condition
I2C Device Address
and Read/ Write Bit
Sub-address
First Data Byte
Other Data Bytes
Last Data Byte
Figure 12. Multiple-Byte Write Transfer
Single-Byte Read
As shown in Figure 13, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. For the data read transfer, both a write followed by a read are
actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read.
As a result, the R/W bit becomes a 0. After receiving the APA3175 address and the read/write bit, APA3175 responds
with an acknowledge bit. Besides, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the APA3175 address and the read/write bit again. This time the read/
write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the APA3175 again
responds with an acknowledge bit. And then, the APA3175 transmits the data byte from the memory address being
read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to
complete the single byte data read transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Not Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6
A1 A0 ACK
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
Stop
Condition
I2C Device Address
and Read/ Write Bit
Sub-address
I2C Device Address
and Read/ Write Bit
Data Byte
Repeat Start
Condition
Figure 13. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are
transmitted by the APA3175 to the master device as shown in Figure 14. Except for the last data byte, the master device
responds with an acknowledge bit after receiving each data byte.
Repeat Start
Start
Condition
Condition
Acknowledge
Acknowledge
Acknowledge Acknowledge
A0 R/WACK D7 D0 ACK D7
Acknowledge
D0 ACK D7
Not Acknowledge
D0 ACK
A6
A0 R/WACK A7 A6
A1 A0 ACK
A6
Stop
Condition
I2C Device Address
and Read/ Write Bit
I2C Device Address
and Read/ Write Bit
Sub-
address
First Data
Byte
Other Data
Bytes
Last Data
Byte
Figure 14. Multiple-Byte Read Transfer
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Rev. A.3 - Aug., 2016
APA3175
Function Description (Cont.)
Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/
right channels.
The DRC input/output diagram is shown in Figure 15.
Limit Level
Time
Limit Level
Figure 15. Dynamic Range Control
Attack Time
Release
Time
Gain
Limit Level
Time
Limit Level
E
A
B
C
D
F
Figure 16. DRC Structure
Biquad Structure
All biquads use a 2nd order IIR filter structure as shown below. Each biquad has 3 coefficients on the direct path (b0,
b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram.
b0
y(n)
x(n)
Magnitude
Trunction
S
Z-1
Z-1
b1
b2
a1
a2
Z-1
Z-1
Figure 17. Biquad Filter
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Rev. A.3 - Aug., 2016
APA3175
Function Description (Cont.)
26Bit 3.23 Number Format
All mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. Numbers formatted as 3.23 numbers
means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown
in Figure 18.
2-23 Bit
2-5 Bit
2-1 Bit
20 Bit
21 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
Figure 18. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting and is shown in Figure 18. If the
MSB is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the MSB is a
logic 1, and then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result, and
then the weighting shown in Figure 19 applied to obtain the magnitude of the negative number.
21 Bit
20 Bit
2-1 Bit
2-4 Bit
2-23 Bit
(1 or 0) x21+ (1 or 0) x20+ (1 or 0) x2-1+
(1 or 0) x2-4+
(1 or 0) x2-23
Figure 19. Conversion Weighting Facroes 3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32 bit binary numbers. The format of the 32 bit number
(4 byte or 8 digit hexadecimal number) is shown in Figure 20.
Sign Bit
Integer
Digit 1
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
Fraction
Digit 6
u
u
u
u
u
u
S
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
Coefficient
digit 8
Coefficient
digit 7
Coefficient
digit 6
Coefficient
digit 5
Coefficient
digit 4
Coefficient
digit 3
Coefficient
digit 2
Coefficient
digit 1
Figure 20. Alignment of 3.23 Coefficient in 32Bit I2C Word
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APA3175
Function Description (Cont.)
Sample Calculation for 3.23 Format
dB
0
Linear
1
Decimal
8388608
Hex (3.23 Format)
00800000
5
1.7782794
0.5623413
L = 10(X/20)
14917288
00E39EA8
-5
X
4717260
0047FACC
D = 8388608 × L
H = dec2hex (D, 8)
Sample Calculation for 9.17 Format
dB
0
Linear
1
Decimal
131072
Hex (9.17 Format)
00020000
5
1.7782794
0.5623413
L = 10(X/20)
233082.6
00038E7A
-5
X
73707.2
00011FEB
D = 131072 × L
H = dec2hex (D, 8)
Recommended Use Model
Normal Operation
Shutdown
Power Down
Intialization
3V
3V
AVDD/DVDD
tDL-VDDH
tVDDH-DL
SD
tPOR
tPOR
Stable and Valid Clocks
MCLK
LRCLK
SCLK
Stable and
Valid Clocks
Clock Errors and
Rate Changes OK
I2S
SDIN
texitSD
tautodetect
tenterSD
SCL
I2C
DAP
Config
Other
Config
Volume and Mute
Commands
Reconfigure DAP After Shutdown
Enter
SD
Trim
Exit SD
SDA
tautodetect
Reconfigure DAP After Shutdown
tRH-I2C
tRL-DV
tDV-RH
RST
tRL-PVCCH
tPVCCH-I2C
tVDD-PVCCL
PVDD/AVCC
tPVCCL-VDDH
10V
7.5V
10V
7.5V
Figure 21. Recommended Command Sequence
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Rev. A.3 - Aug., 2016
APA3175
Function Description (Cont.)
Recommended Use Model (Cont.)
APA3175
Parameter
Description
Unit
Min.
0
Typ.
Max.
tVDDH-DL Time digital inputs must remain low after AVDD/DVDD goes above 3V
tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V
tVDDH-PVDDL Time PVDD/AVCC remains below 7.5V after AVDD/DVDD goes above 3V
tPVDDL-VDDH Time PVDD/AVCC must be below 7.5V before AVDD/DVDD goes below 3V
tPVDDH-I2C Time PVDD/AVCC must be above 10V before I2C commands may address device
-
-
-
-
-
-
-
-
-
-
0
100
0
ms
10
Time PVDD/AVCC must remain above 10V after RST goes low
tRL-PVDDH
tRH-I2C
tDV-RH
tRL-DV
2
-
-
-
-
Time RESET must be high before I2C commands may address device
Time digital inputs must be valid (driven as recommended) before RST goes high
Time digital inputs must remain valid (driven as recommended) after RST goes low
13.5
ms
100
2
-
-
-
-
ms
Auto-detect completion wait time (given stable and valid clocks) before issuing
further commands
tautodetect
texitSD
tenterSD
tPOR
50
-
-
-
-
-
-
-
-
Exit shutdown wait time before issuing further commands to device (t start given by 1+1.3 x
register 0x1A) tstart
ms
Enter shutdown wait time before issuing further commands to device (t stop given 1+1.3 x
by register 0x1A) tstop
Power-on-reset wait time after 1st trim following AVDD/DVDD power-up (tstart given 240 +
by register 0x1A) (does not apply to trim commands following subsequent resets) 1.3 x tstart
Sudden Power Loss (BD)
AVDD/DVDD
3V
tDL-VDDH
SD
MCLK
LRCLK
SCLK
I2S
SDIN
SCL
I2C
SDA
tPL-HL
RST
tRL-PVCCH
tPVCCL-VDDH
PVDD/AVCC
10V
7.5V
Figure 22. Power Loss Sequence
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APA3175
Function Description (Cont.)
Recommended Use Model (Cont.)
APA3175
Typ.
Parameter
Description
Unit
Min.
Max.
Time digital inputs must remain valid (driven as recommended) after RST goes low
tRL-DV
2
0
-
-
-
-
tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V
Time PVDD/AVCC must remain above 10V after RST goes low
ms
tRL-PVDDH
2
0
-
-
-
-
tPVDDL-VDDH Time PVDD/AVCC must be below 7.5V before AVDD/DVDD goes below 3V
Recommended Command Sequences
The DAP has two groups of commands. One set is for configuration and is intended for use only during initialization.
The other set has built-in click and pop protection and may be used during normal operation while audio is streaming.
The following supported command sequences illustrate how to initialize, operate, and shutdown the device.
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVDD supply as follows:
• Drive RST=0, SD=1, and other digital inputs to their desired state while ensuring that all are never more than 2.5V
above AVDD/DVDD. Provide stable and valid I2S clocks (MCLK, LRCLK, and SCLK). Wait at least 100ms, drive
RST=1, and wait at least another 13.5ms.
• Ramp up PVDD to at least 4.5V while ensuring that it remains below 3.5V for at least 100ms after AVDD/DVDD
reaches 3V. Then wait at least another 10ms.
3. Configure the DAP via I2C (see Users’s Guide for typical values): biquads (0x29-36)DRC parameters (0x3A-3C,
0x40-42, and 0x46) Bank select (0x50).
4. Configure remaining registers.
5. Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown (sequence defined below)
(d) Clock errors and rate changes
Note: Events (c) and (d) are not supported for 240ms+1.3xt0 0after trim following AVDD/DVDD power up ramp (where Tstart is
specified by register 0x1A).
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APA3175
Function Description (Cont.)
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3xtstop (where tstop is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step
4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following
AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3xtstart (where tstart is specified by register 0x1A).
4. Proceed with normal operation.
Power-down Sequence
Use the following sequence to power-down the device and its supplies:
1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert SD=0 and
wait at least 2ms.
2. Assert RST=0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
• Drive all digital inputs low after RST has been low for at least 2ms.
• Ramp down PVDD while ensuring that it remains above 8V until RST has been low for at least 2ms.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and that it is never more
than 2.5V below the digital inputs.
Table 1. Serial Control Interface Register Summary
Sub Address
Register Name
No. of Bytes
Contents
Initialization Values
A u indicates unused bits.
0x00
0x01
Clock control register
Device ID register
1
1
1
1
1
1
1
1
1
1
1
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Reserved (1)
0x6C
0x00
0x02
Error status register
System control register 1
Serial data interface
0x00
0x03
0x80
0x04
0x05
0x05
0x40
0x06
Soft mute register
Master volume
Channel 1 vol
0x00
0x07
0xFF (mute)
0x30 (0dB)
0x30 (0dB)
0x00 (0dB)
0x08
0x09
Channel 2 vol
0x0A
Fine master volume
0x0B - 0X0D
0x0E
Volume configuration register
1
Description shown in subsequent section
0x91
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APA3175
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
0x0F
Register Name
No. of Bytes
Contents
Initialization Values
1
1
1
1
1
1
1
4
4
4
4
Reserved (1)
0x10
Modulation limit register
Start/stop period register
Description shown in subsequent section
Reserved (1)
0x02
0x0A
0x15-0x19
0x1A
Description shown in subsequent section
Reserved (1)
0x1B
0x1C
Reserved (1)
Reserved (1)
0x1D–0x1F
0x20
Input MUX register
PWM MUX register
Description shown in subsequent section
Reserved (1)
0x 0089 777A
0x0102 1345
0x21-0x24
0x25
Description shown in subsequent section
Reserved (1)
0x26-0x28
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x29
0x2A
0x2B
0x2C
ch1_bq [0]
ch1_bq [1]
ch1_bq [2]
ch1_bq [3]
20
20
20
20
0x2D
0x2E
ch1_bq [4]
ch1_bq [5]
20
20
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APA3175
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
Register Name
No. of Bytes
Contents
u [31:26], b2 [25:0]
Initialization Values
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x2E
ch1_bq [5]
20
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
0x2F
0x30
0x31
0x32
0x33
ch1_bq [6]
ch2_bq [0]
ch2_bq [1]
ch2_bq [2]
ch2_bq [3]
20
20
20
20
20
0x34
0x35
ch2_bq [4]
ch2_bq [5]
20
20
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APA3175
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
Register Name
No. of Bytes
Contents
u [31:26], a2 [25:0]
Initialization Values
0x0000 0000
0x0080 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x35
ch2_bq [5]
20
u [31:26], b0 [25:0]
u [31:26], b1 [25:0]
0x36
ch2_bq [6]
20
u [31:26], b2 [25:0]
u [31:26], a1 [25:0]
u [31:26], a2 [25:0]
0x37~ 0x45
0x46
Reserved (2)
DRC Control
EQ Control
4
Description shown in subsequent section
Reserved (2)
Reserved (2)
0x0000 0000
0x0F70 8000
0x47-0x4F
0x50
0x51-0x5F
0x60
Reserved (2)
DRC attack threshold
DRC release threshold
DRC WinIdx
4
4
1
u [31:24], attackTh [23:0]
u [31:24], attackTh [23:0]
Description shown in subsequent section
Reserved (2)
0x0003 2D64
0x0002 FFE4
0x01
0x61
0x62
0x63-0xF8
0xF9
Update Device Address
4
u [31:8], New Dev Id[7:0] (New Dev Id=0x38)
Reserved (2)
0x00000034
0xFA-0xFF
Note (1): Reserved register should not be accessed.
Note (2): Reserved register should not be accessed.
Note (3): “ae” stands for a of energy filter, “aa” stands for a of attack filter and “ad” stands for a of decay filter and 1-a = w.
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APA3175
Function Description (Cont.)
Clock Control Register (0x00)
The clocks and data rates are automatically determined by the APA3175. The clock control register contains the auto-
detected clock status. Bits D7-D5 reflect the sample rate. Bits D4-D2 reflect the MCLK frequency.
Table 2. Clock Control Register (0x00)
D7
0
0
0
0
-
D6
0
0
1
1
-
D5
0
1
0
1
-
D4
-
D3
-
D2
-
D1
-
D0
-
FUNCTION
fS=32kHz sample rate
-
-
-
-
-
fS=88.2kHz/96kHz sample rate
fS=176.4kHz/192kHz sample rate
fS=44.1/48kHz sample rate (5)
-
-
-
-
-
-
-
-
-
-
(6)
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
-
-
-
MCLK frequency=64xfS
(6)
-
-
-
-
-
MCLK frequency=128xfS
(7)
-
-
-
-
-
MCLK frequency=192xfS
(5) (8)
-
-
-
-
-
MCLK frequency=256xfS
-
-
-
-
-
MCLK frequency=384xfS
MCLK frequency=512xfS
Reserved (4)
Reserved (4)
Reserved (4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
Reserved (4)
Note (4): Reserved registers should not be accessed.
Note (5): Italic is default.
Note (6): Only available for 44.1kHz and 48kHz rates.
Note (7): Rate only available for 32/44.1/48kHz sample rates.
Note (8): Not available at 8kHz.
Device Id Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 3. General Status Register (0x01)
D7
X
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
FUNCTION
Reserved
-
0
0
0
0
0
0
0
Identification code
Note: Italic is default.
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APA3175
Function Description (Cont.)
Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register
(write zeroes) and then read them to determine if they are persistent errors. Error Definitions:
MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
SCLK Error: The number of SCLKs per LRCLK is changing.
LRCLK Error: LRCLK frequency is changing.
Table 4. Error Status Register (0x02)
D7
D6
D5
D4
-
D3
D2
D1
D0
FUNCTION
1
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MCLK error
PLL auto clock error
SCLK error
-
-
1
-
-
-
-
-
-
1
-
-
-
LRCLK error
Reserved
-
-
-
1
-
-
-
-
-
-
1
Reserved
Over temperature warning (sets around 145OC) POR error, OCP,
thermal shutdown error
-
-
-
-
-
-
1
0
-
0
0
0
0
0
0
0
No errors
Note: Italic is default.
System Control Register 1 (0x03)
The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter ( -3dB cutoff < 1Hz ) for each
channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same time as volume
ramp defined in reg 0x0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single
step volume ramp Bits D1-D0: Select de-emphasis.
Table 5. System Control Register 1 (0x03)
D7
0
1
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
FUNCTION
PWM high-pass (dc blocking) disenabled
PWM high-pass (dc blocking) enabled
Reserved
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
Reserved
-
-
-
-
-
-
-
Reserved
-
-
0
-
-
-
-
-
Reserved
-
-
-
0
-
-
-
-
Reserved
-
-
-
-
0
-
-
-
Reserved
-
-
-
-
-
0
0
1
1
0
1
0
1
No de-emphasis
-
-
-
-
-
-
Reserved
-
-
-
-
-
-
De-emphasis for fS=44.1kHz
De-emphasis for fS=48kHz
-
-
-
-
-
-
Note: Italic is default.
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APA3175
Function Description (Cont.)
Serial Data Interface Register (0x04)
As shown in Table 6, the APA3175 supports 9 serial data modes. The default is 24bit, I2S mode.
Table 6. Serial Data Interface Control Register (0x04) Format
D7
0
0
0
0
0
0
0
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
0
0
0
0
D5
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
0
0
0
0
0
0
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
-
D1
0
0
1
1
0
0
1
1
0
1
-
D0
0
1
0
1
0
1
0
1
0
0
1
1
Word Length
Receive Serial Data Interface Format
16
20
24
16
20
24
16
20
24
-
Right-justified
Right-justified
Right-justified
I2S
I2S
I2S
Left-justified
Left-justified
Left-justified
Reserved
Reserved
Reserved
-
-
1
1
-
Note: Italic is default.
System Control Register 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are
shut down (hard mute).
Table 7. System Control Register 2 (0x05)
D7
0
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
-
FUNCTION
Reserved
1
0
-
-
-
-
-
-
-
Enter all channel shut down (hard mute)
Exit all channel shut down (Normal operation)
Reserved
-
-
-
-
-
-
-
-
0
0
0
0
0
0
Note: Italic is default.
Soft Mute Register (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 8. Soft Mute Register (0x06)
D7
D6
D5
D4
D3
D2
D1
-
D0
1
0
-
FUNCTION
-
-
-
-
-
-
-
-
-
-
-
-
Soft mute channel 1
Soft un-mute channel 1
Soft mute channel 2
Soft un-mute channel 2
Reserved
-
-
-
-
-
-
-
1
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
-
Note: Italic is default.
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APA3175
Function Description (Cont.)
Volume Registers (0x07, 0x08, 0x09)
Step size is 0.5 dB.
Master volume
- 0x07 (default is mute)
Channel-1 volume - 0x08 (default is 0 dB)
Channel-2 volume - 0x09 (default is 0 dB)
Table 9. Volume Registers (0x07, 0x08, 0x09)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
24dB
0dB
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
-78.5dB
-79.0dB
Values between 0xCF and 0xFE are Reserved
MUTE (default for master volume)
Note: Italic is default.
Master Fine Volume Register (0x0A)
This register can be used to provide precision tuning of master volume.
Table 10. Master Fine Volume Register (0x0A)
D7
D6
D5
D4
D3
D2
D1
0
0
1
1
-
D0
0
1
0
1
-
FUNCTION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0dB
0.125dB
0.25dB
-
-
0.345dB
Write enable bit
1
-
-
-
Ignore write to register 0x0A
Note: Italic is default.
Volume Configuration Register (0x0E)
Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the D2-D0: number
of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows.
Sample Rate (kHz)
8/16/32
Approximate Ramp Rate
125ms/step
11.025/22.05/44.1
12/24/48
90.7ms/step
83.3ms/step
Table 11. Volume Control Register (0x0E)
D7
1
D6
0
D5
0
D4
1
D3
0
D2
-
D1
-
D0
-
FUNCTION
Reserved
Volume slew 512 steps (43ms volume ramp time at 48kHz)
-
-
-
-
-
0
0
0
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APA3175
Function Description (Cont.)
Volume Configuration Register (0x0E) (Cont.)
Table 11. Volume Control Register (0x0E)
D7
D6
D5
D4
D3
D2
0
D1
0
D0
1
FUNCTION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Volume slew 1024 steps (85ms volume ramp time at 48kHz)
Volume slew 2048 steps (171ms volume ramp time at 48kHz)
Volume slew 256 steps (21ms volume ramp time at 48kHz)
Reserved
0
1
0
0
1
1
1
x
x
Note: Italic is default.
Modulation Limit Register (0x10)
Table 12. Modulation Limit Register (0x10)
D7
-
D6
-
D5
-
D4
-
D3
-
D2
0
0
0
0
1
1
1
1
-
D1
0
0
1
1
0
0
1
1
-
D0
0
1
0
1
0
1
0
1
-
MODULATION LIMIT
Reserved
98.4%
-
-
-
-
-
-
-
-
-
-
97.7%
-
-
-
-
-
96.9%
-
-
-
-
-
96.1%
-
-
-
-
-
95.3%
-
-
-
-
-
94.5%
-
-
-
-
-
93.8%
0
0
0
0
0
Reserved
Note: Italic is default.
Start/Stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the SD state. This helps reduce pops and clicks at start-up and shutdown. The times are only
approximate and vary depending on device activity level and I2S clock stability.
Table 13. Start/Stop Period Register (0x1A)
D7
0
-
D6
0
-
D5
0
-
D4
-
D3
-
D2
-
D1
-
D0
-
FUNCTION
Reserved
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-
-
-
No 50% duty cycle start/stop period
-
-
-
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16.5ms 50% duty cycle start/stop period
23.9ms 50% duty cycle start/stop period
31.4ms 50% duty cycle start/stop period
40.4ms 50% duty cycle start/stop period
53.9ms 50% duty cycle start/stop period
70.3ms 50% duty cycle start/stop period
94.2ms 50% duty cycle start/stop period
125.7ms 50% duty cycle start/stop period
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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Rev. A.3 - Aug., 2016
APA3175
Function Description (Cont.)
Start/Stop Period Register (0x1A) (Cont.)
Table 13. Start/Stop Period Register (0x1A)
D7
-
D6
-
D5
-
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
FUNCTION
164.6ms 50% duty cycle start/stop period
239.4ms 50% duty cycle start/stop period
314.2ms 50% duty cycle start/stop period
403.9ms 50% duty cycle start/stop period
538.6ms 50% duty cycle start/stop period
703.4ms 50% duty cycle start/stop period
942.5ms 50% duty cycle start/stop period
1256.6ms 50% duty cycle start/stop period
1728.1ms 50% duty cycle start/stop period
2513.6ms 50% duty cycle start/stop period
3299.1ms 50% duty cycle start/stop period
4241.7ms 50% duty cycle start/stop period
5655.6ms 50% duty cycle start/stop period
7383.7ms 50% duty cycle start/stop period
9897.3ms 50% duty cycle start/stop period
13196.4ms 50% duty cycle start/stop period
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: Italic is default.
Input Multiplexer Register (0x20)
This register controls the modulation scheme (BD mode) as well as the routing of I2S audio to the internal channels.
Table 14. Input Multiplexer Register (0x20)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
FUNCTION
0
0
0
0
0
0
0
0
Reserved
D23
D22
-
D21
-
D20
-
D19
D18
D17
D16
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
-
-
-
Channel 1 BD mode
SDIN-L to Channel 1
SDIN-R to Channel 1
Reserved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
-
-
-
-
-
-
-
-
Reserved
-
-
Reserved
-
-
Reserved
-
-
Ground (0) to channel 1
Reserved
-
-
-
0
1
Reserved
-
-
-
-
Channel-2 BD mode
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APA3175
Function Description (Cont.)
Input Multiplexer Register (0x20) (Cont.)
Table 14. Input Multiplexer Register (0x20)
D23
D22
D21
D20
D19
D18
0
D17
0
D16
0
FUNCTION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIN-L to Channel 2
SDIN-R to Channel 2
Reserved
0
0
1
0
1
0
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Ground (0) to channel 2
Reserved
1
1
1
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
FUNCTION
0
1
1
1
0
1
1
1
Reserved
Reserved
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
0
Note: Italic is default.
Pwm Output Mux Register (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to
any external output pin.
Bits D21-D20: Selects which PWM channel is output to OUT_A
Bits D17-D16: Selects which PWM channel is output to OUT_B
Bits D13-D12: Selects which PWM channel is output to OUT_C
Bits D09-D08: Selects which PWM channel is output to OUT_D
Note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03.
Table 15. PWM Output Mux Register (0x25)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
FUNCTION
0
0
0
0
0
0
0
0
Reserved
Reserved
D23
D22
D21
D20
D19
D18
D17
D16
0
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
1
Multiplex channel 1 to OUT_A
Multiplex channel 2 to OUT_A
Multiplex channel 1 to OUT_A
Multiplex channel 2 to OUT_A
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
1
1
-
0
1
-
-
-
-
-
-
-
-
-
0
-
0
-
-
-
-
-
0
0
0
1
Multiplex channel 1 to OUT_B
Multiplex channel 2 to OUT_B
Multiplex channel 1 to OUT_B
-
-
-
-
-
-
-
-
-
-
1
0
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Rev. A.3 - Aug., 2016
APA3175
Function Description (Cont.)
Pwm Output Mux Register (0x25) (Cont.)
Table 15. PWM Output Mux Register (0x25)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Multiplex channel 2 to OUT_B
-
-
-
-
-
-
1
1
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
0
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
0
0
0
1
Multiplex channel 1 to OUT_C
Multiplex channel 2 to OUT_C
Multiplex channel 1 to OUT_C
Multiplex channel 2 to OUT_C
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
1
1
-
0
1
-
-
-
-
-
-
-
-
-
0
-
0
-
-
-
-
-
0
0
0
1
Multiplex channel 1 to OUT_D
Multiplex channel 2 to OUT_D
Multiplex channel 1 to OUT_D
Multiplex channel 2 to OUT_D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
0
0
0
1
0
1
Reserved
Note: Italic is default.
DRC Control (0x46)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
FUNCTION
FUNCTION
FUNCTION
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
-
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
0
DRC turned OFF
DRC turned ON
Reserved
-
-
-
-
-
-
-
1
0
0
0
0
0
0
0
-
Note: Italic is default.
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APA3175
Function Description (Cont.)
Error Reporting
Any fault resulting in device shutdown is signaled by the ERROR pin going low (see Table 18). A sticky version of this
pin is available on D1 of register 0X02.
Table 16. ERROR Output States
Fault Description
Error
Over-Current (OC) or Under-Voltage (UVP) or Over-Temperature (OTP)
No faults (normal operation)
0
1
Over-Current (OC) Protection With Current-Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function,
rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load
impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second
protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z)
state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed.
Current limiting and overcurrent protection are not independent for half-bridges.
That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are
shut down.
Over-Temperature Protection
The APA3175 has over-temperatureprotection system. If the device junction temperature exceeds 150°C (nominal),
the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The APA3175 recovers automatically once the temperature drops approximately
30°.
Under-Voltage Protection (UVP) and Power-On-Reset (POR)
The UVP and POR circuits of the APA3175 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational
when the PVDD and AVDD supply voltages reach 4.2V and 2.7V, respectively. Although PVDD and AVDD are indepen-
dently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge
outputs immediately being set in the high-impedance (Hi-Z) state and ERROR being asserted low.
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Rev. A.3 - Aug., 2016
APA3175
Application Information
Layout Recommendation
Output & VDD traces width
≥40mil, should be as short as
they can, and symmetric.
Power stage block, please use
high voltage-bearing component .
470Ω 0.047μF
1μF
0.033 μF
4700 pF
PVDD
22μH
AVDD
0.68μF
0.68μF
220μF
0.1μF
10μF
0Ω
0.1μF
8Ω
AVDD
/ERROR
MCLK
TP1
TP2
PGND_AB
PGND_AB
OUT_B
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
A_SEL
MCLK
22μH
10kΩ
P
VDD_B
PVDD_B
BBS
CBS
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
0.1μF
PVDD
0.1μF
10kΩ 1V8_DV
0.033μF
0.033μF
/SD
LRCLK
SCLK
SDIN
SDA
AVDD
4.7μF
0.1μF
/PDN
LRCK
SCLK
SDIN
SDA
SCL
22μH
0.68μF
0.68μF
SCL
PVDD
8Ω
0.1μF
220 μF
22μH
/RESET
DVDD
0.1μF
0.1μF
0.033μF
1μF
10μF
AVDD cap. & DVDD cap.
should be close to the chip.
Thermal pad should be soldered
on ground plane of the PCB .
PVDD cap. and bootstrap cap .
should be close to the chip.
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APA3175
Application Information(Cont.)
Layout Recommendation
5.5mm
Via diameter
=0.3mm X16
1.7mm
0.28mm
5.0mm
0.5mm
Exposed for
thermal PAD
connected
Ground plane
for
ThermalPAD
TQFP7X7-48 Land Pattern Recommendation
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APA3175
Application Information(Cont.)
Layout Recommendation
PCB Referance (Top Layer)
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Rev. A.3 - Aug., 2016
APA3175
Application Information(Cont.)
Layout Recommendation
PCB Referance (Bottom Layer)
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Rev. A.3 - Aug., 2016
APA3175
Package Information
TQFP7x7-48P
D
D1
D2
EXPOSED
PAD
GAUGE PLANE
SEATING PLANE
L
b
e
TQFP7x7-48P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
1.20
0.15
1.05
0.27
0.20
9.20
7.10
5.50
9.20
7.10
5.50
0.047
0.006
0.041
0.011
0.008
0.362
0.280
0.177
0.362
0.280
0.177
0.002
0.037
0.007
0.004
0.346
0.272
0.118
0.346
0.272
0.118
A1
A2
0.05
0.95
0.17
0.09
8.80
6.90
3.00
8.80
6.90
3.00
b
c
D
D1
D2
E
E1
E2
e
0.50 BSC
0.020 BSC
0.45
0o
0.75
7o
0.018
0o
0.030
7o
L
Note : 1. Followed from JEDEC MS-026 ABC.
2. Dimension "D1" and "E1" do not include mold protrusions.
Allowable protrusions is 0.25 mm per side. "D1" and "E1" are
maximun plasticbody size dimensions including mold mismatch.
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APA3175
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
A
H
T1
16.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 16.0±0.30 1.75±0.10
7.5±0.10
K0
TQFP7x7-48P
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
12.0±0.10
2.0±0.10
1.5 MIN.
9.4±0.20
9.4±0.20
1.8±0.20
(mm)
Devices Per Unit
Package Type
TQFP7x7-48P
Unit
Quantity
2500
Tape & Reel
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APA3175
Taping Direction Information
TQFP7x7-48P
USER DIRECTION OF FEED
Classification Profile
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APA3175
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
Time (Tsmin to Tsmax) (ts)
)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
Volume mm3
<350
235 °C
220 °C
³ 2.5 mm
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
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APA3175
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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