APA3541KI-TR [ANPEC]
Class AB Stereo Headphone Driver with Mute; 静音与AB类立体声耳机驱动器
| 型号： | APA3541KI-TR |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Class AB Stereo Headphone Driver with Mute |
| 文件： | 总13页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APA3541/4
Class AB Stereo Headphone Driver with Mute
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
High Signal-to-Noise Ratio
High Slew Rate
•
Portable Digital Audio
Low Distortion
General Description
Large Output Voltage Swing
Flexible Mute Function
The APA3541/4 is an integrated class AB stereo
headphone driver contained in an SO-8 or a DIP-8
plastic package with Mute feature . Besides the com-
mon Mute feature , the APA3541/4 further integrates
a voltage divider inside the chip . Thus , the external
resistors can be eliminated . The APA3541 has a fixed
gain of 0dB and the APA3544 has a fixed gain of 6dB
so that external gain setting is unnecessary. The de-
vice is fabricated in a CMOS process and has been
primarily developed for portable digital audio appli-
cations .
Excellent Power Supply Ripple Rejection
Low Power Consumption
Short-circuit Elimination
Wide Temperature Range
No Switch ON/OFF Clicks
Integrated Voltage Divider (VDD/2) to Eliminate
External Resistors
Ordering and Marking Information
APA3541/4
Package Code
J : PDIP - 8
K : SOP - 8
Y : Chip From
Tem p. Range
Handling Code
Tem p. Range
Package Code
°
I : - 40 to 85
Handling Code
TU : Tube
C
TR : Tape & Reel
APA3541/4 J :
APA3541/4 K :
APA3541/4
XXXXX
XXXXX - Date Code
XXXXX - Date Code
APA3541/4
XXXXX
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. B.1 - Apr., 2003
1
www.anpec.com.tw
APA3541/4
Block Diagram
MUTE
8
1
2
3
4
VDD
Out A
Mute
0dB
0dB
(6dB)
(6dB)
A
+
B
+
7
6
5
Out B
BIAS
Input B
Input A
VSS
BIAS
180kΩ
180kΩ
(90kΩ ) (90kΩ )
* The values in parenthessis are for the APA3544.
Function Pin Description
Pin Name
Out A
Mute
I/O
Function Description
O
I
A channel output pin
Chip disable control input, low active and high for normal operating
A channel input terminal
Input A
VSS
I
Power ground pin
Input B
BIAS
I
I
B channel input terminal
Right channel bias input pin
B channel output pin
OUT B
VDD
O
Power input pin
Absolute Maximum Ratings
Symbol
VDD
Parameter
Rating
Unit
V
Supply Voltage
7
20
tSC(O)
TA
S
Output Short-circuit Duration, at T =25 C, P =1W
°
A
tot
Operating Ambient Temperature range
-40 to 85
150
C
°
C
°
C
°
C
°
TJ
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature,10 seconds
Electrostatic Discharge
TSTG
TS
-65 to +150
300
-3000 to 3000 *1
VESD
V
Note: 1. Human body model : C=100pF, R=1500Ω, 3 positive pulses plus 3 negative pulses
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
2
www.anpec.com.tw
APA3541/4
Thermal Characteristics
Symbol
Parameter
Rating
Unit
RTHJA
Thermal Resistance from Junction to Ambient in Free Air
DIP-8
SOP-8
108
210
K/W
RTHJC
Thermal Resistance from Junction to Case
DIP-8
SOP-8
45
40
K/W
Electrical Characteristics
VIN=0dBV, VCC=5V, TA=25°C, f=1kHz, RL=32Ω (unless otherwise noted)
APM3541/4
Min. Typ. Max.
Symbol
Parameter
Test Condition
Unit
VDD
IQ
Supply Voltage
3.0
5.0
3.5
200
0.7
6.0
5
V
Quiescent Current
Mute Current
VIN= 0 Vrms
mA
Imute
VTM
A
µ
Mute Terminal Voltage
0.3
1.6
0.5
V
Differential Channel
Voltage Gain
GVCL
-0.5
0
dB
dB
∆
APA3541
APA3544
-2
4
0
6
2
8
Vin=1Vrms,f= 1kHz,RL=32
Ω
GVCL
Voltage Gain
Vin=0.5Vrms, f=1kHz,Rl=32
BW<80kHz
Ω
Total Harmonic Channel
Distortion Factor
THD
PU1
0.03 0.1
%
APA3541
50
75
55
80
RL=32 ,THD+N=0.1%,BW<8
Ω
Rated Output Power1
mW
0kHz
APA3544
APA3541
105 110
140 145
RL=16 ,THD+N=0.1%,BW<8
Ω
PU2
VNO
CS
Rated Output Power2
Output Noise Voltage
Channel Separation
mW
0kHz
APA3544
BW=20~20kHz , Vin=0Vrms
-93 -85 dBV
APA3541
APA3544
-90 -95
-65 -70
F=1kHz
dB
ATT
RR
Mute Attenuation
Ripple Rejection
VIN=1Vrms,f=1kHz,Mute=L
FRR=100Hz,VRR=-20dBV
65
50
70
60
dB
dB
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
3
www.anpec.com.tw
APA3541/4
Test and Application Circuit
1µ F
220µ F
VINB
1 0 µ F
VDD
VDD
Input B
Out B
BIAS
5
6
7
8
100µ F
BIAS
APA3541
0dB(6dB)
(APA3544)
B
0dB(6dB)
A
MUTE
4
3
2
1
VSS
Input A
Out A
Mute
220µ F
100kΩ
1µ F
VINA
VMUTE
H : Speaker Action
L : Mute on
1µ F
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
4
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APA3541/4
Typical Characteristics
8
5
4
3
2
1
0
RL=32Ω
RL=32Ω
7
6
5
MUTE : OFF
4
3
2
MUTE : ON
1
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 1 : Supply Voltage : VDD (V)
Figure 2 : Supply Voltage : VDD (V)
10
+8
+6
APA3541
VDD=5V
0
+4
+2
+0
-2
-10
-20
-30
-40
-50
-60
-70
-80
VDD=5V
VIN=0dBv
VIN=0dBv
f =1 kHz
RL=32Ω
-4
-6
-8
-10
-12
0
0.4
0.8
1.2
1.6
2
10
100
1k
10k
100k
Figure 3 : Mute Control Voltage : VTM (V)
Figure 4 : Frequency :f (Hz)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
5
www.anpec.com.tw
APA3541/4
Typical Characteristics Cont.
10
5
10
VDD= 3V
5
VDD= 5V
RL=32Ω
RL=32Ω
2
1
2
BW< 80kHz
BW< 80kHz
1
0.5
0.5
0.2
0.2
0.1
f =10KHz
f =10kHz
0.1
0.05
0.05
f =1KHz , 100Hz
0.02
0.01
f =1kHz, 100Hz
0.02
0.01
-40
-30
-20
-10
+0
+10
-40
-30
-20
-10
+0
+10
Output Voltage : VOUT (dBv)
Figure 6 :
Figure 5 : Output Voltage : VOUT (dBv)
10
10
5
VDD= 3V
5
VDD= 5V
RL=16Ω
RL=16Ω
2
2
1
BW< 80kHz
BW< 80kHz
1
0.5
0.5
f =10kHz
f =10kHz
0.2
0.2
0.1
0.1
0.05
0.05
f =1kHz, 100Hz
f =1kHz, 100Hz
0.02
0.01
0.02
0.01
-40
-40
-30
-20
-10
+0
+10
-30
-20
-10
+0 +10
Figure 7 : Output Voltage : VOUT (dBv)
Figure 8 : Output Voltage : VOUT (dBv)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
6
www.anpec.com.tw
APA3541/4
Typical Characteristics Cont.
+0
+0
-10
-20
VDD=5V
VDD=5V
-20
RL=32Ω
VIN=0dBv
RL=32Ω
-30
-40
-50
-60
-70
-80
-90
100
-40
-60
-80
-100
-120
10
100
1k
10k
100k
10
100
1k
10k
100k
Figure 9 : Frequency :f (Hz)
Figure 10 : Frequency :f (Hz)
0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
-7 0
-8 0
-9 0
-1 0 0
0
1
2
3
4
5
6
7
Figure 11 : Supply Voltage : VDD (V)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
7
www.anpec.com.tw
APA3541/4
Application Note
pacitors are recommended for the best THD and
noise performance .
Input Capacitor , Ci
In the typical application an input capacitor , Ci , is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation . In this
case , the external capacitor Ci and the internal re-
sistance Ri form a high-pass filter with the corner fre-
quency determined in the follow equation:
Output Coupling Capacitor, Cc
In the typical single-supply SE configuration , an out-
put coupling capacitor (Cc) is required to block the
DC bias at the output of the amplifier thus preventing
DC currents in the load . As with the input coupling
capacitor , the output coupling capacitor and imped-
ance of the load form a high-pass filter governed by
equation .
fc (highpass)= 1/ (2πRiCi)
(1)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the APA3541 where Ri is 180kΩ and
APA3544 is 90kΩ internal fixed . Equation is
reconfigured as follow:
fc(highpass)= 1/(2πRLCc)
(4)
For example , a 220µF capacitor with an 32Ω speaker
would attenuate low frequencies below 22Hz . The
main disadvantage , from a performance standpoint
, is the load impedance is typically small , which drives
the low-frequency corner higher degrading the bass
response . Large values of Cc are required to pass
low frequencies into the load .
Ci= 1/(2π*180kΩ*fc) for APA3541
Ci= 1/(2π*90kΩ*fc) for APA3544
(2)
And the ceramic capacitor is recommanded.
Bias Capacitor , Cb
Optimizing Depop Circuitry
As with any power amplifier , proper supply bypass-
ing is critical for low noise performance and high
power supply rejection . The capacitor location on
both the bypass and power supply pins should be as
close to the device as possible . The effect of a larger
half supply bias capacitor is improved PSRR due to
increased half-supply stability . Typical applications
employ a 5V regulator with 10µF and a 0 . 1µF bias
capacitors which aid in supply filtering .
When the amplifier is in mute mode , both of the out-
put stage and input bypass continues to be biased .
And no pop noise will be heard during the transition
out of mute mode .
Power Supply Decoupling, Cs
APA3541/4 is a high-performance CMOS audio am-
plifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD)
is as low as possible . Power supply decoupling also
prevents the oscillations causing by long lead length
between the amplifier and the speaker . The optimum
decoupling is achieved by using two different type
capacitors that target on different type of noise on
the power supply leads . For higher frequency tran-
sients , spikes , or digital hash on the line , a good
low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1µF placed as close as possible
to the device V lead works best . For filtering lower-
This does not eliminate the need for bypassing the
supply nodes of the APA3541/4 . The selection of
bias capacitors , especially Cb , is thus dependent
upon desired PSRR requirements , click and pop per-
formance . The capacitor is fed from a 95kΩ source
inside the amplifier . To keep the start-up pop as low
as possible , the relationship shown in equation should
be maintained .
1/(Cb*95kΩ)≤ 1/{Ci*Ri}
(3)
As an example , consider a circuit where Cb is
4.7µF, Ci is 1µF and APA3541 Ri is 180kΩ . Inserting
these values into the equation we get 2.24≤ 5.55
which satisfies the rule . Bias capacitor , Cb , values
of 2.2µF to 10µF ceramic or tantalum low-ESR ca-
DD
frequency noise signals , a large aluminum electro-
lytic capacitor of 10µF or greater placed near the audio
power amplifier is recommended .
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
8
www.anpec.com.tw
APA3541/4
Packaging Information
PDIP-8 pin ( Reference JEDEC Registration MS-001)
D
E1
E
1
1
A2
A
L
E3
A1
e2
e 1
e 3
Dim
Millimeters
Inches
Min.
Max.
Min.
Max.
5.33
0.210
A
A1
A2
D
0.38
2.92
9.02
0.015
0.115
0.355
3.68
10.16
0.145
0.400
2.54BSC
7.62 BSC
0.100BSC
0.300 BSC
e1
e2
e3
E
E1
E3
L
0.36
1.14
0.56
1.78
0.014
0.045
0.022
0.070
6.10
2.92
7.11
10.92
3.81
0.240
0.115
0.280
0.430
0.150
1
15
15
°
φ
°
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
9
www.anpec.com.tw
APA3541/4
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
L
0.004max.
Millimeters
Inches
Dim
Min.
Max.
Min.
Max.
0.069
0.010
0.197
0.157
0.244
0.050
0.020
A
A1
D
1.35
0.10
4.80
3.80
5.80
0.40
0.33
1.75
0.25
5.00
4.00
6.20
1.27
0.51
0.053
0.004
0.189
0.150
0.228
0.016
0.013
E
H
L
e1
e2
1.27BSC
0.50BSC
1
8
8
°
φ
°
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
10
www.anpec.com.tw
APA3541/4
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
°
183 C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
VPR
Average ramp-up rate(183 C to Peak)
3 C/second max.
°
10 C /second max.
°
°
120 seconds max
60 – 150 seconds
10 –20 seconds
Preheat temperature 125 ± 25 C)
Temperature maintained above 183 C
°
°
60 seconds
Time within 5 C of actual peak temperature
°
Peak temperature range
Ramp-down rate
220 +5/-0 C or 235 +5/-0 C 215-219 C or 235 +5/-0 C
°
°
°
°
6 C /second max.
10 C /second max.
°
°
6 minutes max.
Time 25 C to peak temperature
°
Package Reflow Conditions
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
pkg. thickness 2.5mm
and all bgas
≥
Convection 220 +5/-0 C
Convection 235 +5/-0 C
°
°
VPR 215-219 C
VPR 235 +5/-0 C
°
°
IR/Convection 220 +5/-0 C
IR/Convection 235 +5/-0 C
°
°
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
11
www.anpec.com.tw
APA3541/4
Reliability test Program
Test item
SOLDERABILITY
HOLT
Method
Description
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
°
245 C , 5 SEC
°
1000 Hrs Bias @ 125 C
PCT
°
168 Hrs, 100 % RH , 121 C
TST
MIL-STD-883D-1011.9
°
°
-65 C ~ 150 C, 200 Cycles
ESD
Latch-Up
MIL-STD-883D-3015.7
JESD 78
VHBM > 2KV, VMM > 200V
10ms , I > 100mA
tr
Carrier Tape & Reel Dimensions
t
D
P
Po
E
F
P1
Bo
W
Ao
D1
Ko
T2
J
C
A
B
T1
A
B
C
Application
SOP- 8
J
T1
T2
W
P
E
12.75+
0.15
330
1
62 +1.5
D
2
0.5
12.4 0.2
2
0.2
12 0. 3
±
8
0.1
1.75 0.1
±
±
±
±
±
±
F
D1
Po
P1
Ao
Bo
Ko
t
5.5
1
1.55 +0.1 1.55+ 0.25 4.0 0.1
2.0 0.1
6.4 0.1
5.2 0. 1
2.1 0.1 0.3 0.013
± ±
±
±
±
±
±
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
12
www.anpec.com.tw
APA3541/4
Cover Tape Dimensions
Application
SOP- 8
Carrier Width
Cover Tape Width
Devices Per Reel
12
9.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
13
www.anpec.com.tw
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