AWC6325P9 [ANADIGICS]
HELP3E Dual-band Cellular & PCS CDMA 3.4 V Linear Power Amplifier Module; HELP3E双频蜂窝和PCS CDMA 3.4 V线性功率放大器模块型号: | AWC6325P9 |
厂家: | ANADIGICS, INC |
描述: | HELP3E Dual-band Cellular & PCS CDMA 3.4 V Linear Power Amplifier Module |
文件: | 总11页 (文件大小:895K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AWC6325
HELP3ETM Dual-band Cellular & PCS CDMA
3.4 V Linear Power Amplifier Module
PRELIMINARY DATA SHEET - Rev 1.3
FEATURES
and linearity, which greatly reduces the total current
drawn from the battery. This feature, in conjunction
with selectable operating modes, enables significant
improvements in overall power added efficiency of
the AWC6325 across the entire dynamic range of
operating powers. APT requires use of an external
variable voltage supply (DC-DC converter), which is
used to provide the variable voltage to Vcc pad of the
amplifier. A low-leakage shutdown mode increases
standby time. This PAhas built-in directional couplers
for each band, with a common coupler output port
CPL_OUT. The 3 mm x 5 mm x 0.9 mm surface mount
package incorporates matching networks optimized
for output power, efficiency and linearity in a 50 Ω
system. The device is manufactured on an advanced
InGaP HBT MMIC technology offering state-of-the-art
reliability, temperature stability, and ruggedness.
•
InGaP HBT Technology
•
High Efficiency:
•
•
•
37 % @ POUT = +28 dBm
20 % @ POUT = +16 dBm
10 % @ POUT = +10 dBm
•
•
•
•
•
Low Quiescent Current: 4 mA
Internal Voltage Regulation
Built-in Directional Coupler
Common VMODE Control Line
Suitable for SMPS and average power tracking
systems with variable supply voltages
•
APT can reduce TS.09 average power
consumption more than 25%
•
•
•
Reduced External Component Count
Thin Package: 0.9 mm
RoHS Compliant Package, 260 oC MSL-3
APPLICATIONS
V
EN_CELL
1
2
14
13
12
11
10
9
GND
•
Dual-band Wireless Handsets and Data Devices
Bias Control
Voltage Regulation
for CDMA/EVDO networks:
•
•
Cellular BC 0 and 10
PCS BC 1 and 14
RFIN_CELL
CPL
RFOUT_CELL
V
MODE1
3
4
5
V
CC
CC
PRODUCT DESCRIPTION
AWC6325 addresses the demand for increased
integration in dual-band handsets for CDMAnetworks.
The small footprint 3 mm x 5 mm x 0.9 mm surface
mount RoHS compliant package contains independent
RF PA paths to ensure optimal performance in both
frequency bands in less board area than two single
band PAs. The package pinout was chosen to enable
handset manufacturers to independently provide
bias to both power amplifiers and simplify control
with common mode pins. The AWC6325 is part of
ANADIGICS’ 3rd generation of High-Efficiency-at-
Low-Power (HELP3E™) family of power amplifiers,
which deliver low quiescent currents and significantly
greater efficiency through selectable bias modes for
high, medium and low power operation. TheAWC6325
is designed for use both with and without average
power tracking (APT). APT can be used to optimize
the Vcc level for the desired output power level
VBATT
V
A
V
MODE2
CPLOUT
GND
RFIN_PCS
CPL
6
7
Bias Control
Voltage Regulation
V
EN_PCS
8
RFOUT_PCS
GND at Slug (pad)
Figure 1: Block Diagram
05/2012
AWC6325
VMODE1
CPLOUT
VMODE2
Figure 2: Pinout
Table 1: Pin Description
PIN
NAME
DESCRIPTION
1
2
VEN_CELL
RFIN_CELL
VMODE1
VBATT
Enable Voltage for Cell Band
RF Input for Cell Band
Mode Control Voltage 1
Battery Voltage
3
4
5
VMODE2
RFIN_PCS
VEN_PCS
Mode Control Voltage 2
RF Input for PCS Band
Enable Voltage for PCS Band
6
7
8
RFOUT_PCS RF Output for PCS Band
9
GND
CPLOUT
VCCA
VCC
Ground
10
11
12
13
14
Coupler Output Port
Supply Voltage A
Supply Voltage
RFOUT_CELL RF Output for Cell Band
GND Ground
PRELIMINARY DATA SHEET - Rev 1.3
2
05/2012
AWC6325
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER
MIN
0
MAX
+5
UNIT
V
Supply Voltage (VBATT, VCC, VCCA)
Mode Control Voltage (VMODE1,2,
RF Input Power (PIN
Storage Temperature (TSTG
V
EN)
0
+3.5
+10
+150
V
)
-
dBm
°C
)
-40
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure
to absolute ratings for extended periods of time may adversely affect
reliability.
Table 3: Operating Ranges
PARAMETER
MIN
TYP
MAX UNITS
COMMENTS
Cellular BC0 & 10
814
1850
-
-
849
MHz
1915
Operating Frequency (f)
PCS BC1 & 14
Supply Voltage (VCC, VCCA)
Battery Voltage (VBATT)
+0.8
+3.2
+3.4 +4.35
+3.4 +4.35
V
V
+1.35
0
+1.8
0
+3.1
+0.5
PA “on”
PA “shut down”
Enable Voltage (VEN_CELL, VEN_PCS)
Mode Control Voltage (VMODE1,2)
V
V
+1.35
0
+1.8
0
+3.1
+0.5
Logic High
Logic Low
Cellular RF Output Power CDMA
CDMA, HPM
CDMA, MPM
27.5 (1)
28.0
16.0
10.0
-
-
-
-
-
dBm
CDMA 2000, RC-1
CDMA 2000, RC-1
CDMA, LPM
PCS RF Output Power CDMA
CDMA, HPM
CDMA, MPM
27.5 (1)
28.0
16.0
10.0
-
-
-
-
-
dBm
CDMA, LPM
Case Temperature (TC)
-30
-
+90
°C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only
over the conditions defined in the electrical specifications.
Notes:
(1) For operation at VCC = +3.2 V, POUT is derated by 0.5 dB.
PRELIMINARY DATA SHEET - Rev 1.3
3
05/2012
AWC6325
Table 4: Electrical Specifications - Cellular Band (BC 0, 10)
(TC
= +25 °C, VBATT = VCC = +3.4 V, VEN_CELL = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)
COMMENTS
PARAMETER
MIN
TYP
MAX
UNIT
POUT
VMODE1
VMODE2
25
14
7
28
17
12
31
19
14
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
Gain
dB
Adjacent Channel Power
at ± 885 kHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-
-
-48.5
-52
-53.5
-46.5
-46.5
-46.5
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
dBc
Adjacent Channel Power
at ± 1.98 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-
-
-58
-59
-68
-56
-56
-56
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
dBc
-
-
-
37.5
19.5
10
-
-
-
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
Power-Added Efficiency (1)
%
Quiescent Current (Icq)
Mode Control Current
BATT Current
-
-
-
-
4
-
-
-
-
mA
mA
mA
mA
through VCC pins, VMODE1,2 = +1.8 V
through VMODE pin, VMODE1,2 = +1.8 V
through VBATT pin, VMODE1,2 = +1.8V
through VEN_CELL pin, VMODE1,2 = +1.8 V
0.5
1.5
0.3
Enable Current
Total Decoder Current on
VBATT (in Shutdown mode)
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
-
7
-
µA
HBT Leakage Current (VCC)
(Shutdown mode)
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
-
-
<1
-
-
mA
Noise In Receive Band
-133
dBm/Hz 869 MHz to 894 MHz
Harmonics
2fO
3fO, 4fO
-
-
-
-
-35
-35
dBc
POUT < +28 dBm
Input Impedence
Coupling Factor
-
-
2.5:1
-
-
VSWR
dB
22
POUT < +28 dBm
Spurious Output Level
(all spurious outputs)
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
-
-
-
-65
dBc
Load mismatch stress with no
permanent degradation or failure
8:1
-
VSWR Applies over full operating range
Notes:
(1) PAE and ACP measured at 836.5 MHz.
PRELIMINARY DATA SHEET - Rev 1.3
4
05/2012
AWC6325
Table 5: Electrical Specifications - PCS Band (BC 1, 14)
(TC
= +25 °C, VBATT = VCC = +3.4 V, VEN_PCS = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)
COMMENTS
PARAMETER
MIN
TYP
MAX
UNIT
POUT
VMODE1
VMODE2
24
10
7
26.5
13
9
30
16
12
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
Gain
dB
Adjacent Channel Power
at ± 1.25 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-
-
-48
-52.5
-53
-46.5
-46.5
-46.5
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
dBc
dBc
Adjacent Channel Power
at ± 1.98 MHz offset (1)
-
-
-
-55
-60
-63
-54
-54
-54
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
Adjacent Channel Power
at ± 2.25 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-
-
-59.5
-63.5
-67.5
-56.5
-57
-57
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
dBc
-
-
-
37
20
10
-
-
-
+28 dBm
+16 dBm
+10 dBm
0 V
1.8 V
1.8 V
0 V
0 V
1.8 V
Power-Added Efficiency (1)
%
Quiescent Current (Icq)
Mode Control Current
BATT Current
-
-
-
-
4
-
-
-
-
mA
mA
mA
mA
through VCC pins, VMODE1,2 = +1.8 V
through VMODE pin, VMODE1,2 = +1.8 V
through VBATT pin, VMODE1,2 = +1.8V
through VEN_PCS pin, VMODE1,2 = +1.8 V
0.5
1.5
0.3
Enable Current
Total Decoder Current on VBATT
(in Shutdown mode)
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
-
7
-
µA
µA
HBT Leakage Current on VCC
(in Shutdown mode)
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
-
-
<1
-
-
Noise In Receive Band
-133
dBm/Hz 1930 MHz to 1990 MHz
Harmonics
2fO
3fO, 4fO
-
-
-
-
-30
-30
dBc
POUT < +28 dBm
Input Impedence
Coupling Factor
-
-
-
2:1
VSWR
dB
22
-
POUT < +28 dBm
Spurious Output Level
(all spurious outputs)
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
-
-
-
-65
dBc
Load mismatch stress with no
permanent degradation or failure
8:1
-
VSWR Applies over full operating range
Notes:
(1) ACPRs and Efficiency measured at 1880 MHz.
PRELIMINARY DATA SHEET - Rev 1.3
5
05/2012
AWC6325
APPLICATION INFORMATION
Bias Modes
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
The power amplifier may be placed in Low, Medium,
or High Bias modes by applying the appropriate logic
level (see Operating Ranges table) to the VMODE pin.
The Bias Control table lists the recommended modes
of operation for various applications.
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE pads.
Vcontrols
Venable/Vmode(s)
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
On Sequence Start
T_0N=0µ
Off Sequence Start
T_0FF=0µ
ON Sequence
OFF Sequence
RFIN_CELL,PCS
notes 1,2
VEN_CELL,PCS
V
CC,
VCCA
note 1
T_0N+1µS
T_0N+3µS
T_0FF+2µS T_0FF+3µS
Referenced After 90%of Rise
Time
Referenced Before10%of Fall
Time
Figure 3: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
Table 6: Bias Control
POUT
LEVELS
BIAS
MODE
VEN_CELL
VEN_PCS
APPLICATION
Low Bias Mode
Medium Bias Mode
VMODE1
+1.8 V
+1.8 V
VMODE2
+1.8 V
0 V
VCC
VBATT
> 3.2 V
> 3.2 V
< +10 dBm
Low
+1.8 V
+1.8 V
0.8 - 4.35 V
0.8 - 4.35 V
> +10 dBm
< +16 dBm
Medium
High Bias Mode
Shutdown
> +16 dBm
High
+1.8 V
0 V
0 V
0 V
0 V
0 V
1.3 - 4.35 V
3.2 - 4.35 V
> 3.2 V
>3.2 V
-
Shutdown
PRELIMINARY DATA SHEET - Rev 1.3
6
05/2012
AWC6325
V
EN_CELL
1
2
14
13
12
11
10
9
Bias Control
Voltage Regulation
RFIN_CELL
CPL
RFOUT_CELL
VMODE1
3
4
5
V
CC
1000 pF
68 pF
V
BATT
V
CCA
68pF
2.2 µF
2.2 µF
V
MODE2
CPLOUT
RFIN_PCS
CPL
6
7
Bias Control
Voltage Regulation
VEN_PCS
8
RFOUT_PCS
GND at Slug (pad)
Figure 4: Application Circuit
PRELIMINARY DATA SHEET - Rev 1.3
7
05/2012
AWC6325
PACKAGE OUTLINE
Figure 5: Package Outline - 14 Pin 3 mm x 5 mm x 0.9 mm Surface Mount Module
Pin 1 Identifier
Part Number
Lot Number
6325
LLLLLNN
Date Code
Country Code(CC)
YY= Year WW= Work Week
YYWWCC
Figure 6: Branding Specification
PRELIMINARY DATA SHEET - Rev 1.3
8
05/2012
AWC6325
PCB BOARD DESIGN GUIDELINES
and the PCB-to-device interconnect pattern. The
PCB metal design recommendations primarily deal
with the PCB-to-device interconnection. Specific
board-level electrical and thermal performance re-
quirements will be dictated by the physical geometry
of the specific application and are the responsibility
of the end product manufacturer.
Refer to Figure 7 for the recommended PCB metal
design, soldermask design, and stencil print patterns
when assembling with ANADIGICS modules.
It is important to note that the PCB metal design is
dependent upon several factors: the electrical and
thermal performance requirements of the product,
Figure 7: PCB Board Design Guidelines
PRELIMINARY DATA SHEET - Rev 1.3
9
05/2012
AWC6325
Figure 8: Carrier Tape Drawing
Ø50.8
0.2
Ø177.8
MIN.
Ø54.2
0.1
MADE IN USA
(2X)SLOT 3.0 .1
12.4
.
(3X)1.78 .25
Ø13.0 0.2
DIMENSIONS ARE IN MILLIMETERS
Ø20.6 0.13
CENTER HOLE DETAIL
ENLARGED FOR CLARITY
NOTES:
MATERIAL:
BLACK CARBON POLYSTYRENE
1X104TO 1X105 ohms/square
1.
SURFACE RESISTIVITY:
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
Figure 9: Reel Drawing
PRELIMINARY DATA SHEET - Rev 1.3
10
05/2012
AWC6325
ORDERING INFORMATION
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDER NUMBER
COMPONENT PACKAGING
RoHS Compliant 14 Pin
AWC6325Q7
-30 C to +90 C 3 mm x 5 mm x 0.9 mm Tape and Reel, 2500 pieces per Reel
Surface Mount Module
RoHS Compliant 14 Pin
AWC6325P9
-30 C to +90 C 3 mm x 5 mm x 0.9 mm
Partial Tape and Reel
Surface Mount Module
anaDigiCS, iꢀc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
iMPOrTanT nOTiCE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of anANADIGICS product
in any such application without written consent is prohibited.
PRELIMINARY DATA SHEET - Rev 1.3
11
05/2012
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