AWC6340P9 [ANADIGICS]

HELP CDMA Band Class 0,10 CDMA Power Amplifier Module; HELP CDMA频段0,10级CDMA功率放大器模块
AWC6340P9
型号: AWC6340P9
厂家: ANADIGICS, INC    ANADIGICS, INC
描述:

HELP CDMA Band Class 0,10 CDMA Power Amplifier Module
HELP CDMA频段0,10级CDMA功率放大器模块

放大器 功率放大器 CD
文件: 总10页 (文件大小:910K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
AWC6340  
HELPTM CDMA Band Class 0,10  
CDMA Power Amplifier Module  
PRELIMINARY DATA SHEET- Rev 1.8  
FEATURES  
CDMA/EVDO Compliant  
HELPTM technology  
High Efficiency (RC-1 waveform):  
• 36 % @ POUT = +28.0 dBm  
• 16 % @ POUT = +15 dBm  
A
WC6340  
Low Quiescent Current: 12 mA  
Low Leakage Current in Shutdown Mode: <5 µA  
Internal Voltage Regulator  
•ꢀ Integrated “daisy chainable” directional coupler  
with CPLIN and CPLOUT port.  
Internal DC Blocks on all RF ports  
Optimized for a 50 System  
1.8V Control Logic  
M45 Package  
10 Pin 3 mm x 3 mm x 1 mm  
Surface Mount Module  
RoHS Compliant Package, 260 oC MSL-3  
APPLICATIONS  
Band Class 0, 10 CDMA/EVDO Wireless  
Devices  
GND at Slug (pad)  
PRODUCT DESCRIPTION  
The AWC6340 is a HELPTM product for CDMA  
devices operating in Band Class 0 and 10. This PA  
incorporates ANADIGICS’ HELP™ technology to  
deliver exceptional efficiency at low power levels and  
low quiescent current without the need for external  
voltage regulators or converters. The device is  
manufactured using advanced InGaP HBT technology  
offering state-of-the-art reliability, temperature stability,  
and ruggedness. Two selectable bias modes that  
optimize efficiency for different output power levels and  
a shutdown mode with low leakage current increase  
handset talk and standby time. A “daisy chainable”  
directional coupler is integrated in the module thus  
eliminating the need of an external coupler. The  
self-contained 3 mm x 3 mm x 1 mm surface mount  
package incorporates matching networks optimized for  
output power, efficiency, and linearity in a 50 Ω system.  
1
2
3
4
5
10  
V
BATT  
V
CC  
9
8
7
6
CPL  
RFIN  
RFOUT  
CPLIN  
GND  
Bias Control  
GND  
Voltage Regulation  
VMODE  
V
EN  
CPLOUT  
Figure 1: Block Diagram  
02/2012  
AWC6340  
1
2
10  
9
V
BATT  
V
CC  
RFIN  
RFOUT  
3
8
GND  
CPLIN  
4
5
7
6
V
MODE  
GND  
VEN  
CPLOUT  
Figure 2: Pinout (X-ray Top View)  
Table 1: Pin Description  
PIN  
1
NAME  
DESCRIPTION  
Battery Voltage  
RF Input  
V
BATT  
2
RFIN  
3
GND  
Ground  
4
V
MODE  
Mode Control Voltage  
PA Enable Voltage  
Coupler Output  
Ground  
5
V
EN  
6
CPLOUT  
GND  
7
8
CPLIN  
RFOUT  
Coupler Input  
RF Output  
9
10  
V
CC  
Supply Voltage  
PRELIMINARY DATA SHEET - Rev 1.8  
2
02/2012  
AWC6340  
ELECTRICAL CHARACTERISTICS  
Table 2: Absolute Minimum and Maximum Ratings  
PARAMETER  
MIN  
0
MAX  
+5  
UNIT  
V
Supply Voltage (VCC  
)
Battery Voltage (VBATT  
Control Voltages (VMODE,  
RF Input Power (PIN  
Storage Temperature (TSTG  
)
0
+6  
V
V
EN  
)
0
+3.5  
+10  
+150  
V
)
-
dBm  
°C  
)
-40  
Stresses in excess of the absolute ratings may cause permanent damage.  
Functional operation is not implied under these conditions. Exposure  
to absolute ratings for extended periods of time may adversely affect  
reliability.  
Table 3: Operating Ranges  
PARAMETER  
MIN  
816  
+3.1  
TYP  
MAX  
UNIT COMMENTS  
Operating Frequency (f)  
-
849  
MHz  
Supply Voltage (VCC  
)
+3.4 +4.35  
V
V
POUT +28 dBm  
+1.35  
0
+1.8  
-
+3.1  
+0.5  
PA "on"  
PA "shut down"  
Enable Voltage (VEN  
)
+1.35  
0
+1.8  
-
+3.1  
+0.5  
Low Bias Mode  
High Bias Mode  
Mode Control Voltage (VMODE  
)
V
CDMA Output Power  
HPM  
LPM  
27.5(1)  
-
28  
15  
-
-
dBm  
CDMA 2000, RC1  
C  
Case Te mperature (T  
C
)
-30  
-
+90  
The device may be operated safely over these conditions; however, parametric performance is guaranteed only  
overꢀtheꢀconditionsꢀdefinedꢀinꢀtheꢀelectricalꢀspecifications.  
Note:  
(1) For operation at 3.1 V, POUT is derated by 0.8 dB.  
PRELIMINARY DATA SHEET - Rev 1.8  
3
02/2012  
AWC6340  
Tableꢀ4:ꢀElectricalꢀSpecificationsꢀ-ꢀCDMA2000ꢀOperationꢀ(RC-1ꢀwaveform)  
(TC  
= +25 °C, VBATT = VCC = +3.4 V, VENABLE = +1.8 V, 50 system)  
COMMENTS  
PARAMETER  
MIN  
TYP MAX  
UNIT  
P
OUT  
V
MODE  
-
-
28  
15.5  
-
-
+28 dBm  
+15 dBm  
0 V  
1.8 V  
Gain  
dB  
Adjacent Channel Power  
at 885 kHz offset (1)  
-
-
-50  
-49  
-
-
+28 dBm  
+15 dBm  
0 V  
dBc  
dBc  
Primary Channel BW = 1.23 MHZ  
Adjacent Channel BW = 30 kHz  
1.8 V  
Adjacent Channel Power  
at 1.98 MHz offset (1)  
-
-
-62  
-58  
-
-
+28 dBm  
+15 dBm  
0 V  
1.8 V  
Primary Channel BW = 1.23 MHZ  
Adjacent Channel BW = 30 kHz  
-
-
36  
16  
-
-
+28 dBm  
+15 dBm  
0 V  
1.8 V  
Power-Added Efficiency (1)  
%
Quiescent Current (Icq)  
Low Bias Mode  
-
12  
-
mA  
through VCC pin  
1.8 V  
Mode Control Current  
Enable Current  
-
-
-
0.06  
0.4  
0.15  
0.6  
mA  
mA  
mA  
through VMODE pin, VMODE = 1.8 V  
through VEN pin  
BATT Current  
3.0  
0.5  
through VBATT pin, VMODE = +1.8 V  
V
V
BATT = +4.35 V, VCC = +4.35 V,  
EN = 0 V, VMODE = 0 V  
µA  
Leakage Current  
-
-
<5  
-
-
Noise in Receive Band  
-135  
dBm/Hz  
Harmonic  
2fo  
-
-
-40  
-60  
-
-
dBc  
P
OUT +28 dBm  
3fo, 4fo  
Coupling Factor  
Directivity  
-
-
20  
20  
-
-
dB  
dB  
Coupler IN_OUT  
698 MHz to 2620 MHz  
Pin 8-6, Shutdown Mode  
-
<0.25  
-
-70  
-
dB  
Daisy Chain Insertion Loss  
P
OUT +28 dBm  
Spurious Output Level  
(all spurious outputs)  
In-band Load VSWR < 5:1  
-
-
-
dBc  
Out-of-band Load VSWR < 10:1  
Applies over all operating conditions  
Load mismatch stress with no  
permanent degradation or failure  
8:1  
VSWR Applies over all operating conditions  
Notes:  
(1) ACLR and Efficiency measured at 836.5 MHz.  
PRELIMINARY DATA SHEET - Rev 1.8  
4
02/2012  
AWC6340  
APPLICATION INFORMATION  
To ensure proper performance, refer to all related The Bias Control table below lists the recommended  
Application Notes on the ANADIGICS web site: modes of operation for various applications.  
http://www.anadigics.com  
Two operating modes are recommended to optimize  
Shutdown Mode  
current consumption. High Bias/High Power operating  
The power amplifier may be placed in a shutdown mode is for POUT levels > 15 dBm. At about 15 dBm,  
mode by applying logic low levels (see Operating the PAshould be “Mode Switched” to Low Power Mode.  
Ranges table) to the VEN and VMODE voltages.  
Bias Modes  
The power amplifier may be placed in either Low or  
High Bias modes by applying the appropriate logic  
level (see Operating Ranges table) to the VMODE pin.  
Vcontrols  
Venable/Vmode(s)  
Rise/Fall Max 1µS  
Defined at 10% to 90%  
of Min/Max Voltage  
On Sequence Start  
T_0N=0µ  
Off Sequence Start  
T_0FF=0µ  
ON Sequence  
OFF Sequence  
RFIN  
notes 1,2  
VEN  
VCC  
note 1  
T_0N+1µS  
T_0N+3µS  
T_0FF+2µS T_0FF+3µS  
Referenced After 90%of Rise  
Time  
Referenced Before10%of Fall  
Time  
Figure 3: Recommended ON/OFF Timing Sequence  
Notes:  
(1) Level might be changed after RF is ON.  
(2) RF OFF defined as PIN ≤ -30 dBm.  
(3) Switching simultaneously between VMODE and VEN is not recommended.  
Table 5: Bias Control  
P
OUT  
BIAS  
APPLICATION  
V
EN  
V
MODE  
V
CC  
V
BATT  
LEVELS  
+15 dBm  
> +15 dBm  
-
MODE  
Low power  
High power  
Shutdown  
Low  
High  
+1.8 V +1.8 V  
3.1 - 4.35 V  
3.1 - 4.35 V  
3.1 - 4.35 V  
> 3.1 V  
> 3.1 V  
> 3.1 V  
+1.8 V  
0 V  
0 V  
0 V  
Shutdown  
PRELIMINARY DATA SHEET - Rev 1.8  
5
02/2012  
AWC6340  
VBATT  
VCC  
C2  
0.01 µF  
C1  
C9  
C3  
330 pF  
C4  
C5  
2.2 µF  
GND at slug  
2.2 µF ceramic  
0.01 µF 100 pF  
1
2
10  
9
VBATT  
VCC  
RFIN  
RFIN  
GND  
VMODE  
VEN  
RFOUT  
RFOUT  
8
3
4
CPLIN  
GND  
CPLIN  
7
6
VMODE  
VEN  
5
CPLOUT  
CPLOUT  
Figure 4: Evaluation Board Schematic  
PRELIMINARY DATA SHEET - Rev 1.8  
6
02/2012  
AWC6340  
PACKAGE OUTLINE  
Figure 5: Package Outline - 10 Pin 3 mm x 3 mm x 1 mm Surface Mount Module  
Figureꢀ6:ꢀBrandingꢀSpecificationꢀ-ꢀM45ꢀPackage  
PRELIMINARY DATA SHEET - Rev 1.8  
7
02/2012  
AWC6340  
PCB AND STENCIL DESIGN GUIDELINE  
Figure 7: Recommended PCB Layout Information  
PRELIMINARY DATA SHEET - Rev 1.8  
8
02/2012  
AWC6340  
COMPONENT PACKAGING  
Pin 1  
Figure 8: Carrier Tape  
Figure 9: Reel  
PRELIMINARY DATA SHEET - Rev 1.8  
9
02/2012  
AWC6340  
ORDERING INFORMATION  
TEMPERATURE  
PACKAGE  
DESCRIPTION  
ORDER NUMBER  
COMPONENT PACKAGING  
RANGE  
RoHS Compliant 10 Pin  
3 mm x 3 mm x 1 mm Tape and Reel, 2500 pieces per Reel  
Surface Mount Module  
AWC6340Q7  
-30 oC to +90 oC  
RoHS Compliant 10 Pin  
3 mm x 3 mm x 1 mm Partial Tape and Reel  
Surface Mount Module  
AWC6340P9  
-30 oC to +90 oC  
anaDigiCS  
141 Mount Bethel Road  
Warren, New Jersey 07059, U.S.A.  
Tel: +1 (908) 668-5000  
Fax: +1 (908) 668-5132  
URL: http://www.anadigics.com  
iMPOrTanT nOTiCE  
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.  
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to  
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed  
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers  
to verify that the information they are using is current before placing orders.  
warning  
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of anANADIGICS product  
in any such application without written consent is prohibited.  
PRELIMINARY DATA SHEET - Rev 1.8  
10  
02/2012  

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