TSL2571 [AMSCO]
LIGHT-TO-DIGITAL CONVERTER; 光 - 数字转换器
| 型号： | TSL2571 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | LIGHT-TO-DIGITAL CONVERTER |
| 文件： | 总25页 (文件大小：706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
TSL2571
LIGHT-TO-DIGITAL CONVERTER
r
r
TAOS117A − FEBRUARY 2011
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
Features
D Ambient Light Sensing (ALS)
− Approximates Human Eye Response
− Programmable Analog Gain
6 SDA
5 INT
4 NC
VDD
1
− Programmable Integration Time
− Programmable Interrupt Function with
Upper and Lower Threshold
SCL 2
GND 3
− Resolution Up to 16 Bits
− Very High Sensitivity — Operates Well
Behind Darkened Glass
− Up to 1,000,000:1 Dynamic Range
Applications
D Programmable Wait Timer
− Programmable from 2.72 ms
to > 8 Seconds
D Display Management
D Backlight Control
− Wait State — 65 mA Typical Current
D Portable Device Power Optimization
D Cell Phones, PDA, GPS
D Notebooks and Monitors
D LCD TVs
2
D I C Interface Compatible
2
− Up to 400 kHz (I C Fast Mode)
− Dedicated Interrupt Pin
D Small 2 mm ꢀ 2 mm ODFN Package
D Sleep Mode — 2.5 mA Typical Current
Description
The TSL2571 family of devices provides ambient light sensi(ALS) that approximates human eye response
to light intensity under a variety of liging onditions and ough a variety of attenuation materials. While useful
for general purpose light sensing, he device is particularly useful for display management with the purpose of
extending battery life and proving optimum viewing n diverse lighting conditions. Display panel and keyboard
backlighting can account for u30 to 40 percent of otal platform power. The ALS features are ideal for use
in notebook PCs, LCD monitors, flat-panel teles, and cell phones.
Functional Block Diagram
Interrupt
INT
GND
Wait Control
Upper Limit
Lower Limit
CH0
ADC
CH0
Data
V
DD
SCL
SDA
ALS Control
CH0
CH1
ADC
CH1
Data
CH1
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
Texas Advarnced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
www.taosinc.com
1
TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Detailed Description
The TSL2571 light-to-digital device includes on-chip photodiodes, integrating amplifiers, ADCs, accumulators,
2
clocks, buffers, comparators, a state machine, and an I C interface. The device combines one photodiode
(CH0), which is responsive to both visible and infrared light, and one photodiode (CH1), which is responsive
primarily to infrared light. Two integrating ADCs simultaneously convert the amplified photodiode currents into
a digital value providing up to 16 bits of resolution. Upon completion of the conversion cycle, the conversion
result is transferred to the data registers. This digital output can be read by a microprocessor through which the
illuminance (ambient light level) in lux is derived using an empirical formula to approximate the human eye
response.
2
Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I C serial bus for eas
connection to a microcontroller or embedded controller. The digital output of the device is inherently more
immune to noise when compared to an analog interface.
The device provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-st value
is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The
interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light
intensity value. An interrupt is generated when the value of an ALS conversion exceeds eithean upper or lower
threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many
consecutive exceeded thresholds are necessary to trigger an interrupt. Interrupt threholds and persistence
settings are configured independently.
Copyright E 2011, TAOS Inc.
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
Power supply ground. All voltages are referenced to GND.
NAME
GND
INT
NO.
3
5
O
Interrupt — open drain (active low).
NC
4
Do not connect.
2
2
SCL
SDA
2
I
I C serial clock input terminal — clock signal for I C serial data.
2
2
6
I/O
I C serial data I/O terminal — serial data I/O for I C .
Supply voltage.
V
1
DD
Available Options
DEVICE
TSL25711
TSL25713
ADDRESS
PACKAGE − LEADS
INTERFACE DESCRIPTION
ORDERING NUMBER
TSL25711FN
2
0x39
0x39
0x29
0x29
FN−6
FN−6
FN−6
FN−6
I C Vbus = V Interface
DD
2
I C Vbus = 1.8 V Interface
TSL25713FN
†
TSL25715
C Vbus = V Interface
TSL25715FN
DD
†
2
TSL25717
I C b= 1.8 V Interface
TSL25717FN
†
Contact TAOS for availability.
Absolute Maximum Ratings over operating free-air temperaure range (unless otherwise noted)†
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
DD
Digital output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
O
Digital output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
O
Storage temperature range, T
ESD tolerance, human body mel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolutmaximum ratings” use permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditioyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditionfor extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
Recommended Operating Condins
MIN NOM
MAX
3.6
UNIT
V
Supply voltage, V
2.6
3
DD
Operating free-air temperature, T
−30
70
°C
A
Copyright E 2011, TAOS Inc.
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Operating Characteristics, VDD = 3 V, TA = 25ꢁ C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
175
65
MAX
UNIT
Active
Wait mode
250
I
Supply current
μA
DD
2
Sleep mode — no I C activity
3 mA sink current
2.5
4
0.4
0.6
5
0
0
V
I
INT, SDA output low voltage
V
OL
6 mA sink current
Leakage current, SDA, SCL, INT pins
−5
μA
LEAK
TSL25711, TSL25715
TSL25713, TSL25717
TSL25711, TSL25715
TSL25713, TSL25717
0.7 V
DD
V
SCL, SDA input high voltage
SCL, SDA input low voltage
V
V
IH
IL
1.25
0.3 V
DD
V
0.54
ALS Characteristics, VDD = 3 V, TA = 25ꢁ C, Gain = 16, AEN = 1 (unless otherwise noted)
(Notes 1 ,2, 3)
PARAMETER
TEST CONDITIONS
CHANNEL
CH0
MIN
TYP
MAX
5
UNIT
0
E = 0, AGAIN = 120×,
e
Dark ADC count value
counts
ATIME = 0xDB (100 ms)
CH1
1
5
ADC integration time step size
ADC Number of integration steps
ADC counts per step
ATIME = 0xFF
258
1
2.72
2.9
256
ms
steps
ATIME = 0xFF
ATIME = 0xC0
0
1024 counts
65535 counts
6000
ADC count value
0
2
C0
CH1
CH0
CH1
4000
5000
790
λ = 625 nm, 11.6 μW/cm ,
p
ATIME = 0F6 (27 ms) See note 2.
ADC count value
counts
6000
2
4000
5000
2800
λ = 850 m, E = 219.7 μW/cm ,
p
e
ATIM= 0xF6 (27 ms) See o3.
λ 625 nm, ATIME = 0xF6 27 ms) See note 2.
10.8
41
15.8
56
20.8
%
p
ADC count value ratio: CH1/CH0
Irradiance responsivity
λ 850 nm, ATIME (27 ms) See note 3.
68
CH0
29.1
4.6
λ = 625 nm, ATIME = 6 (27 ms)
p
counts/
See note 2.
CH1
CH0
CH1
(μW/
R
e
22.8
12.7
2
λ = 80 nm, ATIME = 0xF6 (27 ms)
p
cm )
See note .
8×
16×
12×
−10
10
Gain scaling, relative to 1× gain
−10
−10
10
10
%
setting
NOTES: 1. Optical measurements are mde using small-angle incident radiation from light-emitting diode optical sources. Visible 625 nm LEDs
and infrared 850 nm LEDare sed for final product testing for compatibility with high-volume production.
2. The 625 nm irradiancE is upplied by an AlInGaP light-emitting diode with the following typical characteristics: peak wavelength
e
λp = 625 nm and spectrl halfwidth Δλ½ = 20 nm.
3. The 850 nm rdiane E is supplied by a GaAs light-emitting diode with the following typical characteristics: peak wavelength
e
λp = 850 nm anspectral halfwidth Δλ½ = 42 nm.
Copyright E 2011, TAOS Inc.
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r
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Wait Characteristics, VDD = 3 V, TA = 25ꢁ C, WEN = 1 (unless otherwise noted)
PARAMETER
Wait step size
Wait number of integration steps
TEST CONDITIONS
WTIME = 0xFF
CHANNEL
MIN
2.58
1
TYP
MAX
2.9
UNIT
ms
2.72
256
steps
AC Electrical Characteristics, VDD = 3 V, TA = 25ꢁ C (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
kHz
μ
2
f
t
Clock frequency (I C only)
400
(SCL)
(BUF)
Bus free time between start and stop condition
1.3
Hold time after (repeated) start condition. After
this period, the first clock is generated.
t
0.6
s
(HDSTA)
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
μs
μs
μs
ns
μs
μs
ns
ns
pF
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
F
Data setup time
10
1.3
0.6
SCL clock low period
SCL clock high period
Clock/data fall time
300
300
10
Clock/data rise time
Input pin capacitance
R
C
i
†
Specified by design and characterization; not production tested.
PARAMETER MEASUREMENT INFORMATION
t
t
(R)
(LOW)
V
IH
SCL
SDA
V
IL
t
t
t
(HDSTA)
(HIGH)
(SUSTA)
t
t
t
(SUSTO)
t
(BUF)
(HDDA
(SUDAT)
V
V
IH
IL
P
S
S
P
Stop
Condition
Stt
Condtion
Start
Stop
t
(LOWSEXT)
SCL
SCL
ACK
ACK
t
t
t
(LOWMEXT)
(LOWMEXT)
(LOWMEXT)
SCL
SDA
Figure 1. Timing Diagrams
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
TYPICAL CHARACTERISTICS
SPECTRAL RESPONSIVITY
NORMALIZED IDD
vs.
VDD and TEMPERATURE
110%
108%
106%
104%
102%
1
0.8
0.6
0.4
0.2
Ch 0
75ꢁC
50ꢁC
25ꢁC
100%
98%
96%
4%
92%
0ꢁC
Ch 1
0
2.7
2.8
2.9
3
3.1
3.2
3.3
300 400 500 600 700 800 900 1000 1100
V
— V
λ − Wavelength − nm
DD
Figure 2
Figure 3
NORMALIZED RESPONSIVITY
vs.
ANGULAR DICEMENT
1.0
0.8
0.6
0.4
0.2
0
-Q
−30
+Q
30
90
−90
−60
0
60
Q − Angular Displacement − °
Figure 4
Copyright E 2011, TAOS Inc.
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
PRINCIPLES OF OPERATION
System State Machine
The device provides control of ALS and power management functionality through an internal state machine
(Figure 5). After a power-on-reset, the device is in the sleep mode. As soon as the PON bit is set, the device
will move to the start state. It will then continue through the Wait and ALS states. If these states are enabled,
the device will execute each function. If the PON bit is set to 0, the state machine will continue until all
conversions are completed and then go into a low power sleep mode.
Sleep
PON = 1 (r0:b0)
PON = 0 (r0:b0)
Start
Wait
ALS
Figure 5. Simpd State Diagram
NOTE: In this document, the nomenclature uses thbit field name in talic followed by the register number and
bit number to allow the user to easily identify the register and bit hat controls the function. For example, the
power on (PON) is in register 0, bit 0. This rpresented as ON (0:b0).
Photodiodes
Conventional silicon detectors espond strongly to inrarelight, which the human eye does not see. This can
lead to significant error when thfrared content of the ambient light is high (such as with incandescent lighting)
due to the difference between the silicon detesponse and the brightness perceived by the human eye.
This problem is overcome through the usof two photodiodes. The channel 0 photodiode, referred to as the
CH0 channel, is sensitive to both visible and inrared light, while the channel 1 photodiode, referred to as CH1,
is sensitive primarily to infrared lighTwo integrating ADCs convert the photodiode currents to digital outputs.
The ADC digital outputs from the two hannels are used in a formula to obtain a value that approximates the
human eye response in units olu
Copyright E 2011, TAOS Inc.
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
ALS Operation
The ALS engine contains ALS gain control (AGAIN) and two integrating analog-to-digital converters (ADC) for
the Channel 0 and Channel 1 photodiodes. The ALS integration time (ATIME) impacts both the resolution and
the sensitivity of the ALS reading. Integration of both channels occurs simultaneously and upon completion of
the conversion cycle, the results are transferred to the data registers (C0DATA and C1DATA). This data is also
referred to as channel count. The transfers are double-buffered to ensure data integrity.
ATIME(r1)
2.72 ms to 696 ms
C0DATAH(r0x15), C0DATA(r0x14)
C1DATAH(r0x17), C1DATA(r0x16)
CH0
ALS
CH0
Data
ALS Control
CH0
CH1
ADC
CH1
Data
CH1
AGAIN(r0x0F, b1:0)
1ꢀ, 8ꢀ, 16ꢀ, 120ꢀ Gain
Figure 6. ALS Operation
The registers for programming the integration and wait mes are a 2’s compliment values. The actual time can
be calculated as follows:
ATIME = 256 − Integratn Time / 2.72 ms
Inversely, the time can be calculated from the register value fows:
Integration Time = 272 ms × (256 − ATIME)
In order to reject 50/60-Hz ripple trongly present in luorescent lighting, the integration time needs to
be programmed in multiples of 10 .3 ms or the hcyle time. Both frequencies can be rejected with a
programmed value of 50 ms (ATIME = 0xED) or ms of 50 ms (i.e. 100, 150, 200, 400, 600).
The registers for programming the AGAIN hold a two-bit value representing a gain of 1×, 8×, 16×, or 120×. The
gain, in terms of amount of gain, will be represented by the value AGAINx, i.e. AGAINx = 1, 8, 16, or 120.
Lux Equation
The lux calculation is a function of Cchannel count (C0DATA), CH1 channel count (C1DATA), ALS gain
(AGAINx), and ALS integration ime n milliseconds (ATIME_ms). If an aperture, glass/plastic, or a light pipe
attenuates the light equally aross the spectrum (300 nm to 1100 nm), then a scaling factor referred to as glass
attenuation (GA) can be used o compensate for attenuation. For a device in open air with no aperture or
glass/plastic above the evice, GA = 1. If it is not spectrally flat, then a custom lux equation with new coefficients
should be generated. (See TAOS application note).
Counts per Lux (CPL) needs to be calculated only when ATIME or AGAIN is changed, otherwise it remains a
constant. Thfirssegment of the equation (Lux1) covers fluorescent and incandescent light. The second
segment (Lux2) covers dimmed incandescent light. The final lux is the maximum of Lux1, Lux2, or 0.
PL = (ATIME_ms × AGAINx) / (GA × 53)
Lux1 = (C0DATA − 2 × C1DATA) / CPL
Lux2 = (0.6 × C0DATA − C1DATA) / CPL
Lux = MAX(Lux1, Lux2, 0)
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TSL2571
LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Interrupts
The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for
light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s
status is available in the status register (0x13), the output of the interrupt state can be enabled using the ALS
interrupt enable (AIEN) field in the enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range.
An interrupt can be generated when the ALS CH0 data (C0DATA) falls outside of the desired light level
range, as determined by the values in the ALS interrupt low threshold registers (AILTx) and ALS interrupt hig
threshold registers (AIHTx). It is important to note that the low threshold value must be less than the high
threshold value for proper operation.
To further control when an interrupt occurs, the device provides a persistence filter. The persistence flteallows
the user to specify the number of consecutive out-of-range ALS occurrences before an interrupt s gerated.
The persistence register (0x0C) allows the user to set the ALS persistence (APERS) value. See the persistence
register for details on the persistence filter values. Once the persistence filter generates an interrupt, it will
continue until a special function interrupt clear command is received (see command regiter).
AIHTH(r07), AIHT(r06)
APERS(r0x0C3:0)
Upper Limi
ALS Perstene
CH0
ADC
CH0
Data
LoweLimit
CH0
AILTH(r05), AILTL(r0
Figre 7. Programmable Interrupt
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LIGHT-TO-DIGITAL CONVERTER
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State Diagram
Figure 8 shows a more detailed flow for the state machine. The device starts in the sleep mode. The PON bit
is written to enable the device. A 2.72-ms delay will occur before entering the start state.
If the WEN bit is set, the state machine will then cycle through the wait state. If the WLONG bit is set, the wait
cycles are extended by 12× over normal operation. When the wait counter terminates, the state machine will
step to the ALS state.
The AEN should always be set. In this case, a minimum of 1 integration time step should be programmed. The
ALS state machine will continue until it reaches the terminal count at which point the data will be latched in
the ALS register and the interrupt set, if enabled.
1 to 256 steps
Sleep
Step: 2.72 ms
Time: 2.72 ms − 696 ms
120 Hz Minimum − 8 ms
100 Hz Minimum − 10 ms
PON = 1
PON = 0
Start
ALS
LS
Check
ALS
Delay
AEN = 1
Wait
Check
2.72 ms
WEN = 1
Wait
WLONG = 0
1 to 256 steps
Step: 2.72 ms
WLNG = 1
o 256 steps
p: 32.64 ms
Time: 2.72 ms − 696 ms
Minimum − 2.72 ms
Time: 32.64 ms − 8.35 s
Minimum − 32.64 ms
Figure . Expanded State Diagram
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LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
I2C Protocol
2
Interface and control are accomplished through an I C serial compatible interface (standard or fast mode) to
a set of registers that provide access to device control functions and output data. The devices support the 7-bit
2
I C addressing protocol.
2
The I C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure 17).
During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the
first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the
register address from the previous command will be used for data access. Likewise, if the MSB of the comman
is not set, the device will write a series of bytes at the address stored in the last valid command with a register
address. The command byte contains either control information or a 5-bit register address. The control
commands can also be used to clear interrupts.
2
2
The I C bus protocol was developed by Philips (now NXP). For a complete description of the I C protoclease
2
review the NXP I C design specification at http://www.i2c−bus.org/references/.
A
N
P
R
S
S
W
Acknowledge (0)
Not Acknowledged (1)
Stop Condition
Read (1)
Start Condition
Repeated Start Condition
Write (0)
... Continuation of protocol
Master-to-Slave
Slave-to-Master
1
7
1
1
8
1
8
1
1
...
...
S
Slave Address
W
A
Command Code
Data Byte
A
P
2
I C Write Protocol
1
7
1
1
1
8
1
1
S
Slave Address
R
A
Data
A
Data
A
P
2
I C Read Protocol
1
7
1
1
8
1
1
7
1
1
S
Slave Addres
W
A
Command Code
A
S
Slave Address
R
A
8
1
8
1
1
...
Data
A
Data
A
P
2
I C Read Protocol — Combined Format
2
Figure 9. I C Protocols
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LIGHT-TO-DIGITAL CONVERTER
TAOS117A − FEBRUARY 2011
Register Set
The device is controlled and monitored by data registers and a command register accessed through the serial
interface. These registers provide for a variety of control functions and can be read to determine results of the
ADC conversions. The register set is summarized in Table 1.
Table 1. Register Address
ADDRESS
−−
RESISTER NAME
COMMAND
ENABLE
ATIME
R/W
W
REGISTER FUNCTION
Specifies register address
RESET VALUE
0x00
0x00
0xFF
0xFF
0x0
x0
0x00
0x00
0x00
0x00
0x00
ID
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x0C
0x0D
0x0F
0x12
0x13
0x14
0x15
0x16
0x17
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Enables states and interrupts
ALS ADC time
WTIME
Wait time
AILTL
ALS interrupt low threshold low byte
ALS interrupt low threshold high byte
ALS interrupt high threshold low byte
ALS interrupt high threshold high byte
Interrupt persistence filters
Configuration
AILTH
AIHTL
AIHTH
PERS
CONFIG
CONTROL
ID
Control register
Device ID
STATUS
C0DATA
C0DATAH
C1DATA
C1DATAH
R
Device status
0x00
0x00
0x00
0x00
0x00
R
CH0 ADC low data rester
CH0 ADC high data register
CH1 ADC odaa register
CH1 ADhigh data register
R
R
R
2
The mechanics of accessing a specc register depends n the specific protocol used. See the section on I C
protocols on the previous pages. general, the CMAND register is written first to specify the specific
control/status register for following read/write opera
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LIGHT-TO-DIGITAL CONVERTER
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Command Register
The command registers specifies the address of the target register for future write and read operations.
Table 2. Command Register
7
6
5
4
3
2
ADD
1
0
COMMAND
− −
COMMAND
TYPE
FIELD
COMMAND
TYPE
BITS
7
DESCRIPTION
Select Command Register. Must write as 1 when addressing COMMAND register.
Selects type of transaction to follow in subsequent data transfers:
6:5
FIELD VALUE
DESCRIPTION
00
01
10
11
Repeated byte protocol transaction
Auto-increment protocol transaction
Reserved — Do not use
Special function — See description belw
Transaction type 00 will repeatedly read thsame register with each ta acess.
Transaction type 01 will provide an aut-increment function to read succssive register bytes.
ADD
4:0
Address register/special function field. Dependg on the transacion type, see above, this field either
specifies a special function command or elecs the specific contrtats-register for following write and
read transactions. The field valisted below apply only to special function commands:
FIELD VALUE
00000
DESRIPTION
Nrml — no action
S interrupt clear
00110
other
eserved — do not write
ALS interrupt cler — lears any pendinLS iterupt. This special function is self clearing.
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Enable Register (0x00)
The ENABLE register is used to power the device on/off, enable functions, and interrupts.
Table 3. Enable Register
7
6
5
4
3
2
1
0
Address
0x00
Reserved
AIEN
WEN
Reserved
AEN
PON
ENABLE
FIELD
Reserved
AIEN
BITS
7:5
4
DESCRIPTION
Reserved. Write as 0.
ALS interrupt mask. When asserted, permits ALS interrupts to be generated.
Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables
wait timer.
WEN
3
Reserved
AEN
2
1
Reserved. Write as 0.
ALS Enable. Writing a 1 activates the ALS. Writing a 0 disables the ALS.
Power ON. This bit activates the internal oscillator to permit the timers and ADC hannls to perate.
Writing a 1 activates the oscillator. Writing a 0 disables the oscillator.
1
PON
0
NOTE 1: A minimum interval of 2.72 ms must pass after PON is asserted befe ALn be initiated. This requed time is enforced by the
hardware in cases where the firmware does not provide it.
ALS Timing Register (0x01)
The ALS timing register controls the internal itegrtion time of the ALS ADCs in 2.72-ms increments.
Tabl4. ALS Timing Rister
FIELD
BITS
DSCRIPTION
INTEG_CYCLS
ATIME
7:0
VALUE
0xFF
0xF6
TIME
MAX COUNT
1024
2.72 ms
27.2 ms
101 ms
174 ms
696 ms
1
37
64
256
10240
0xDB
0xC0
0x00
37888
65535
65535
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TAOS117A − FEBRUARY 2011
Wait Time Register (0x03)
Wait time is set 2.72 ms increments unless the WLONG bit is asserted in which case the wait times are 12×
longer. WTIME is programmed as a 2’s complement number.
Table 5. Wait Time Register
FIELD
BITS
DESCRIPTION
TIME (WLONG = 0)
WTIME
7:0
REGISTER VALUE
WAIT TIME
TIME (WLONG = 1)
0.032 sec
0xFF
0xB6
0x00
1
2.72 ms
201 ms
696 ms
74
2.4 sec
256
8.3 sec
NOTE: The Wait Time Register should be configured before AEN is asserted.
ALS Interrupt Threshold Registers (0x04 − 0x07)
The ALS interrupt threshold registers provides the values to be used as the high and low trigger points for the
comparison function for interrupt generation. If C0DATA crosses below the low threshold specified, or above
the higher threshold, an interrupt is asserted on the interrupt pin.
Table 6. ALS Interrupt Threshold Registers
REGISTER
AILTL
ADDRESS
0x04
BITS
7:0
DSCRIPTION
ALS low theshold lower byte
ALS low threshold upper byt
ALS high threshold loyte
ALS high threshuppr byte
AILTH
0x05
7:0
AIHTL
0x06
7:0
AIHTH
0x07
7:
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Persistence Register (0x0C)
The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is
provided to allow interrupts to be generated after each ADC integration cycle or if the ADC integration has
produced a result that is outside of the values specified by threshold register for some specified amount of time.
ALS interrupts are generated using C0DATA.
Table 7. Persistence Register
7
6
5
4
3
2
1
0
Address
0x0C
PERS
FIELD
Reserved
APERS
BITS
7:4
DESCRIPTION
Reserved
APERS
Reserved
Interrupt persistence. Controls rate of interrupt to the host processor.
3:0
FIELD VALUE
0000
0001
0010
0011
MEANING
INTERRUPT PERSISTENCE FUNCTON
Every ALS cycle generates an interrupt
Every
1
1 value outside of threshold range
2 consecute valus out of range
3 consecue valueout of range
5 cecutive values out of range
10 cutie values out of ge
15 conecutive values out rang
20 consecutive values oof rage
2consecutive valout orange
30 consecute vals ot of range
35 consecutive alues out of range
40 conscutivvalues out of range
45 consective values out of range
5cutive values out of range
55 consecutive values out of range
6consecutive values out of range
2
3
0100
0101
0110
5
10
15
20
25
30
5
40
45
50
55
60
0111
1000
1001
1010
1011
1100
1101
1110
1111
Configuration Register (0x0D)
The configuration register sets he wait long time.
Table 8. Configuration Register
7
5
4
3
2
1
0
Address
0x0D
CONFIG
FIELD
WLONG
Reserved
Reserved
BTS
DESCRIPTION
Reserved
WOG
Reserved
7:2
Reserved. Write as 0.
Wait Long. When asserted, the wait cycles are increased by a factor 12× from that programmed in the
1
0
WTIME register.
Reserved. Write as 0.
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Control Register (0x0F)
The Control register provides eight bits of miscellaneous control to the analog block. These bits typically control
functions such as gain settings and/or diode selection.
Table 9. Control Register
7
6
5
4
3
2
1
0
Address
0x0F
CONTROL
Reserved
AGAIN
FIELD
Reserved
AGAIN
BITS
7:2
DESCRIPTION
Reserved. Write bits as 0
ALS Gain Control.
FIELD VALUE
1:0
ALS GAIN VALUE
00
01
10
11
1× gain
8× gain
16× gain
120× gain
ID Register (0x12)
The ID Register provides the value for the part nuber. The ID registeis a read-only register.
Table 10. ID Register
7
6
5
4
3
2
1
0
Address
0x12
ID
ID
FIELD
BITS
DESCRIPTION
0x04 = TSL25711 & TSL25715
0x0D = TSL25713 & TSL25717
ID
7:0
Part number identification
Status Register (0x13)
The Status Register provides the rnal status of the device. This register is read only.
Table 11. Status Register
7
6
5
4
3
2
1
0
Address
0x13
STATUS
FIELD
Rserved
AINT
Reserved
AVALID
BIT
75
4
DESCRIPTION
Reserved
AINT
Reserved. Write as 0.
ALS Interrupt. Indicates that the device is asserting an ALS interrupt.
Reserved.
eserve
ALID
3:1
0
ALS Valid. Indicates that the ALS CH0 / CH1 channels have completed an integration cycle.
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ADC Channel Data Registers (0x14 − 0x17)
ALS data is stored as two 16−bit values. To ensure the data is read correctly, a two−byte read I2C transaction
should be used with auto increment protocol bits set in the command register. With this operation, when the
lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent
read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles
end between the reading of the lower and upper registers.
Table 12. ADC Channel Data Registers
REGISTER
C0DATA
ADDRESS
0x14
BITS
7:0
DESCRIPTION
ALS CH0 data low byte
C0DATAH
C1DATA
0x15
7:0
ALS CH0 data high byte
ALS CH1 data low byte
ALS CH1 data high byte
0x16
7:0
C1DATAH
0x17
7:0
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TAOS117A − FEBRUARY 2011
APPLICATION INFORMATION: HARDWARE
Typical Hardware Application
A typical hardware application circuit is shown in Figure 10. A 1-μF low-ESR decoupling capacitor should be
placed as close as possible to the V pin.
DD
V
V
BUS
DD
V
DD
R
P
R
P
R
PI
1 mF
TSL2571
INT
SCL
SDA
GND
Figure 10. Typical Application Hardware Circuit
2
2
V
BUS
in Figure 10 refers to the I C bus voltage, which is either V or 1.8 V. Be re to apply the specified I C
DD
bus voltage shown in the Available Options table for te specic device being used
2
The I C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R )
P
2
2
value is a function of the I C bus speed, the I C bltage, and the pacitive load. The TAOS EVM running
at 400 kbps, uses 1.5-kΩ resistors. A 10-kΩ pull-uresistor (R ) can bused for the interrupt line.
PI
PCB Pad Layout
Suggested PCB pad layout guidelins fr the Dual FlaNo-ad (FN) surface mount package are shown in
Figure 11.
2500
Note: Pads can be
extended further if hand
soldering is needed.
1000
1000
400
650
650
1700
400
NOTES: A. All linear imensions are in micrometers.
B. Thidrawinis subject to change without notice.
Figure 11. Suggested FN Package PCB Layout
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MECHANICAL DATA
PACKAGE FN
Dual Flat No-Lead
TOP VIEW
466 ꢂ 10
PIN OUT
TOP VIEW
PIN 1
VDD
1
SCL 2
GND 3
6 SDA
5 INT
4 NC
466
ꢂ 10
2000 ꢂ 100
2000
ꢂ 100
Photodiode Array Area
END VIEW
SIDE VIEW
295
Nomina
650 ꢂ 50
203 ꢂ 8
650
300
ꢂ 50
BOTTOM VIEW
C of Photodiode Array Area
C
L of Solder Cntats
L(Note B)
20 Nomina
140 Nominal
C
L of Solder Contacts
of Photodiode Array Area (Note B)
C
L
PIN 1
Pb
750 ꢂ 150
Lead Free
NOTES: A. All linear imesions are in micrometers. Dimension tolerance is 20 μm unless otherwise noted.
B. This centered within the package within a tolerance of 3 mils.
. Paage top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
. Contct finish is copper alloy A194 with pre-plated NiPdAu lead finish.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 12. Package FN — Dual Flat No-Lead Packaging Configuration
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MECHANICAL DATA
TOP VIEW
2.00 ꢂ 0.05
1.75
ꢃ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢂ 0.05
ꢃ 1.00
ꢂ 0.25
B
A
A
DETAIL A
DETAIL B
5ꢁ Max
5ꢁ Max
0.254
2.18 ꢂ 0.05
2.18 ꢂ 0.05
ꢂ 0.02
0.83 ꢂ 0.05
B
o
A
o
K
o
NOTES: A. Alineadimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The imensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbs on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
DEah reel is 178 millimeters in diameter and contains 3500 parts.
E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
G. This drawing is subject to change without notice.
Figure 13. Package FN Carrier Tape
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MANUFACTURING INFORMATION
The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.
The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Table 13. Solder Reflow Profile
PARAMETER
Average temperature gradient in preheating
Soak time
REFERENCE
DEVICE
2.5°C/sec
t
2 to 3 minutes
Max 60 sec
Max 50 sec
Max 10 sec
260°C
soak
Time above 217°C (T1)
t
1
Time above 230°C (T2)
t
2
Time above T
−10°C (T3)
t
peak
3
Peak temperature in reflow
T
peak
Temperature gradient in cooling
Max −5°C/se
Not to scale — for reference only
T
peak
T
3
T
T
2
1
Time (sec)
t
t
t
3
2
1
t
soak
Figure 14. Solder Reflow Profile Graph
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MANUFACTURING INFORMATION
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package. To ensure the package contains
the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping.
Devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them
from ambient moisture during shipping, handling, and storage before use.
The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under
the following conditions:
Temperature Range
Relative Humidity
Total Time
5°C to 50°C
60% maximum
12 months from the date code on the aluminized envelope — if unened
168 hours or fewer
Opened Time
Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized
envelope has been open for more than 168 hours. If rebaking is required, it should e doe at 50°C for 12 hours.
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PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowlege and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to proide epresentative
and accurate information but may not have conducted destructive testing or chemical analysis on comng materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thCAS numbers and other
limited information may not be available for release.
NOCE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reservs the right to make chages to the products contained in this
document to improve performance or for any other purpose, or to discontinue tem without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders r designing TAOS products into systems.
TAOS assumes no responsibility for the use f ay products or cicuits scibed in this document or customer product
design, conveys no license, either expressed oimplied, under any paent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no aim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liility arising out of the se of any product or circuit, and specifically disclaims any
and all liability, including without limitatconsequential oncidntal damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, IC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH TE FILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Ts Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorpoated
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