TSL25725 [ETC]
LIGHT-TO-DIGITAL CONVERTER;
ETC 
TSL2572
LIGHT-TO-DIGITAL CONVERTER
r
r
TAOS132 − MARCH 2012
PACKAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
Features
D
Ambient Light Sensing (ALS)
− Approximates Human Eye Response
− Programmable Analog Gain and
Integration Time
− 45,000,000:1 Dynamic Range
− Operation to 60,000 lux in Sunlight
− Very High Sensitivity — Ideally Suited for
Operation Behind Dark Glass
6 SDA
5 INT
4 NC
VDD
1
SCL 2
GND 3
Not Actual Size
− Package UV Rejection Filter
D
D
Maskable Interrupt
− Programmable Upper and Lower
Thresholds with Persistence Filter
Applications
D
D
D
D
Display Backlight Control
Keyboard Illumination Control
Wait Timer and Power Management
− Low Power 2.2 mA Sleep State with User-
Selectable Sleep-After-Interrupt Mode
− 90 mA Wait State with Programmable Wait
Time from 2.7 ms to > 8 seconds
Solid State Lighting Control for Daylight
Harvesting
Printer Paper Detection
2
D
I C Fast Mode Compatible Interface
− Data Rates up to 400 kbit/s
− Input Voltage Levels Compatible with V
or 1.8-V Bus
End Products and Market Segments
DD
D
Mobile Handsets, Tablets, Laptops,
Monitors and TVs, Portable Media Players
D
D
Register Set- and Pin-Compatible with the
TSL2x71 Series
D
D
D
D
D
D
Medical and Industrial Instrumentation
White Goods
Small 2 mm ꢀ 2 mm Dual Flat No-Lead (FN)
Package
Toys
Industrial/Commercial Lighting
Digital Signage
Printers
Description
The TSL2572 device family provides ambient light sensing (ALS) that approximates human eye response to
light intensity under a variety of lighting conditions and through a variety of attenuation materials. Accurate ALS
measurements are the result of TAOS’ patented dual-diode technology and the UV rejection filter incorporated
in the package. In addition, the operating range is extended to 60,000 lux in sunlight when the low-gain mode
is used.
While useful for general purpose light sensing, the TSL2572 device is particularly useful for display
management to provide optimum viewing in diverse lighting conditions while extending battery life. The
TSL2572 device family is ideally suited for use in mobile handsets, TVs, tablets, monitors, and portable media
players where the display backlight may account for 50% to 70% of the system power consumption.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
Texas Advarnced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
www.taosinc.com
1
TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Functional Block Diagram
Interrupt
INT
Wait Control
Upper Limit
Lower Limit
CH0
ADC
CH0
Data
V
DD
SCL
SDA
ALS Control
CH0
CH1
ADC
CH1
Data
GND
CH1
Detailed Description
The TSL2572 light-to-digital device provides on-chip photodiodes, integrating amplifiers, ADCs, accumulators,
2
clocks, buffers, comparators, a state machine, and an I C interface. Each device combines a Channel 0
photodiode (CH0), which is responsive to both visible and infrared light, and a channel 1 photodiode (CH1),
which is responsive primarily to infrared light. Two integrating ADCs simultaneously convert the amplified
photodiode currents into a digital value providing up to 16 bits of resolution. Upon completion of the conversion
cycle, the conversion result is transferred to the data registers. This digital output can be read by a
microprocessor through which the illuminance (ambient light level) in lux is derived using an empirical formula
to approximate the human eye response.
2
Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I C serial bus for easy
connection to a microcontroller or embedded controller. The digital output of the device is inherently more
immune to noise when compared to an analog interface.
The device provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-set value
is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The
interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light
intensity value. An interrupt is generated when the value of an ALS conversion exceeds either an upper or lower
threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many
consecutive exceeded thresholds are necessary to trigger an interrupt.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
2
www.taosinc.com
TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
Power supply ground. All voltages are referenced to GND.
NAME
GND
INT
NO.
3
5
O
Interrupt — open drain (active low).
NC
4
Do not connect.
2
2
SCL
SDA
2
I
I C serial clock input terminal — clock signal for I C serial data.
2
2
6
I/O
I C serial data I/O terminal — serial data I/O for I C .
Supply voltage.
V
DD
1
Available Options
DEVICE
TSL25721
TSL25723
ADDRESS
PACKAGE − LEADS
INTERFACE DESCRIPTION
ORDERING NUMBER
TSL25721FN
2
0x39
0x39
0x29
0x29
FN−6
FN−6
FN−6
FN−6
I C Vbus = V Interface
DD
2
I C Vbus = 1.8 V Interface
TSL25723FN
†
2
TSL25725
I C Vbus = V Interface
TSL25725FN
DD
†
2
TSL25727
I C Vbus = 1.8 V Interface
TSL25727FN
†
Contact TAOS for availability.
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, V (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
DD
Input terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
Output terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
Output terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
Storage temperature range, T
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
Recommended Operating Conditions
MIN NOM
MAX
3.6
3.6
70
UNIT
V
2
Supply voltage, V
Supply voltage, V
(TSL25721 & TSL25725) (I C V
= V )
DD
2.4
2.7
3
3
DD
bus
2
(TSL25723 & TSL25727) (I C V
= 1.8 V)
V
DD
bus
Operating free-air temperature, T
−30
°C
A
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
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3
TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Operating Characteristics, VDD = 3 V, TA = 25ꢁ C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
200
90
MAX
UNIT
Active
250
Wait state
I
Supply current
μA
DD
2
Sleep state — no I C activity
3 mA sink current
2.2
4
0.4
0.6
5
0
0
V
I
INT, SDA output low voltage
V
OL
6 mA sink current
Leakage current, SDA, SCL, INT pins
−5
μA
LEAK
TSL25721, TSL25725
TSL25723, TSL25727
TSL25721, TSL25725
TSL25723, TSL25727
0.7 V
DD
V
SCL, SDA input high voltage
SCL, SDA input low voltage
V
V
IH
1.25
0.3 V
DD
V
IL
0.54
ALS Characteristics, VDD = 3 V, TA = 25ꢁ C, AGAIN = 16ꢀ, AEN = 1 (unless otherwise noted)
(Notes 1 ,2, 3)
PARAMETER
TEST CONDITIONS
CHANNEL
CH0
MIN
0
TYP
1
MAX
5
UNIT
E = 0, AGAIN = 120×,
e
Dark ADC count value
counts
ms
ATIME = 0xDB (100 ms)
CH1
0
1
5
ADC integration time step size
ATIME = 0xFF
2.58
2.73
2.9
ADC number of integration steps
(Note 4)
1
256
steps
ADC counts per step (Note 4)
ADC count value (Note 4)
ATIME = 0xFF
ATIME = 0xC0
0
0
1024 counts
65535 counts
6000
2
CH0
CH1
CH0
CH1
4000
5000
680
White light, E = 263.9 μW/cm ,
e
ATIME = 0xF6 (27 ms) (Note 2)
ADC count value
counts
6000
2
4000
5000
2850
λ = 850 nm, E = 263.4 μW/cm ,
p
e
ATIME = 0xF6 (27 ms) (Note 3)
White light, ATIME = 0xF6 (27 ms) (Note 2)
0.086 0.136
0.456 0.570
18.9
0.186
0.684
ADC count value ratio: CH1/CH0
Irradiance responsivity
λ = 850 nm, ATIME = 0xF6 (27 ms) (Note 3)
p
CH0
White light, ATIME = 0xF6 (27 ms)
(Note 2)
counts/
CH1
CH0
CH1
2.58
(μW/
R
e
19.0
2
λ = 850 nm, ATIME = 0xF6 (27 ms)
p
cm )
(Note 3)
10.8
AGAIN = 1× and AGL = 1
AGAIN = 8× and AGL = 0
AGAIN = 16× and AGL = 0
AGAIN = 120× and AGL = 0
0.128
7.2
0.16
8.0
0.192
8.8
×
Gain scaling, relative to 1× gain
setting
14.4
108
16.0
120
17.6
132
NOTES: 1. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible white LEDs
and infrared 850 nm LEDs are used for final product testing for compatibility with high-volume production.
2. The white LED irradiance is supplied by a white light-emitting diode with a nominal color temperature of 4000 K.
3. The 850 nm irradiance E is supplied by a GaAs light-emitting diode with the following typical characteristics: peak wavelength
e
λp = 850 nm and spectral halfwidth Δλ½ = 42 nm.
4. Parameter ensured by design and is not tested.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
4
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Wait Characteristics, VDD = 3 V, TA = 25ꢁ C, WEN = 1 (unless otherwise noted)
PARAMETER
Wait step size
Wait number of integration steps (Note 1)
NOTE 1: Parameter ensured by design and is not tested.
TEST CONDITIONS
CHANNEL
MIN
2.58
1
TYP
MAX
2.9
UNIT
ms
WTIME = 0xFF
2.73
256
steps
AC Electrical Characteristics, VDD = 3 V, TA = 25ꢁ C (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
kHz
μs
2
f
t
Clock frequency (I C only)
400
(SCL)
Bus free time between start and stop condition
1.3
(BUF)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
t
0.6
μs
(HDSTA)
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
μs
ns
μs
μs
ns
ns
pF
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
F
Data setup time
100
1.3
0.6
SCL clock low period
SCL clock high period
Clock/data fall time
300
300
10
Clock/data rise time
Input pin capacitance
R
C
i
†
Specified by design and characterization; not production tested.
PARAMETER MEASUREMENT INFORMATION
t
t
(R)
t
(F)
(LOW)
V
IH
SCL
SDA
V
IL
t
t
t
(HDSTA)
(HIGH)
(SUSTA)
t
t
t
(SUSTO)
t
(BUF)
(HDDAT)
(SUDAT)
V
V
IH
IL
P
S
S
P
Stop
Condition
Start
Condition
Figure 1. Timing Diagrams
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
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5
TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
TYPICAL CHARACTERISTICS
NORMALIZED RESPONSIVITY
vs.
SPECTRAL RESPONSIVITY
ANGULAR DISPLACEMENT
1
0.8
0.6
1.0
0.8
Both Axes
Ch 0
0.6
0.4
0.4
0.2
0
Ch 1
0.2
0
-Q
−30
+Q
30
90
−90
−60
0
60
300 400 500 600 700 800 900 1000 1100
Q − Angular Displacement − °
λ − Wavelength − nm
Figure 2
Figure 3
RESPONSE to WHITE LED
vs.
NORMALIZED IDD
vs.
VDD and TEMPERATURE
TEMPERATURE
110%
115%
110%
108%
106%
104%
102%
105%
100%
95%
0ꢁC
Ch 0
100%
98%
96%
94%
92%
50ꢁC
25ꢁC
75ꢁC
Ch 1
90%
2.7
2.8
2.9
3
3.1
3.2
3.3
0
10
20
30
40
50
60
70
Temperature − °C
V
DD
— V
Figure 4
Figure 5
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
PRINCIPLES OF OPERATION
System State Machine
An internal state machine provides system control of the ALS and wait timer features of the device. At power
up, an internal power-on-reset initializes the device and puts it in a low-power Sleep state.
2
When a start condition is detected on the I C bus, the device transitions to the Idle state where it checks the
Enable register (0x00) PON bit. If PON is disabled, the device will return to the Sleep state to save power.
Otherwise, the device will remain in the Idle state until the ALS function is enabled. Once enabled, the device
will execute the Wait and ALS states in sequence as indicated in Figure 6. Upon completion and return to Idle,
the device will automatically begin a new Wait-ALS cycle as long as PON and AEN remain enabled.
If the ALS function generates an interrupt and the Sleep-After-Interrupt (SAI) feature is enabled, the device will
2
transition to the Sleep state and remain in a low-power mode until an I C command is received. See the
Interrupts section for additional information.
Sleep
I2C
Start
!PON
Idle
WEN &
AEN
!WEN
& AEN
INT & SAI
ALS
Wait
Figure 6. Simplified State Diagram
Photodiodes
Conventional ALS detectors respond strongly to infrared light, which the human eye does not see. This can lead
to significant error when the infrared content of the ambient light is high (such as with incandescent lighting).
This problem is overcome through the use of two photodiodes. The Channel 0 photodiode, referred to as the
CH0 channel, is sensitive to both visible and infrared light, while the Channel 1 photodiode, referred to as CH1,
is sensitive primarily to infrared light. Two integrating ADCs convert the photodiode currents to digital outputs.
The ADC digital outputs from the two channels are used in a formula to obtain a value that approximates the
human eye response in units of lux.
Copyright E 2012, TAOS Inc.
The LUMENOLOGY r Company
r
r
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
ALS Operation
The ALS engine contains ALS gain control (AGAIN) and two integrating analog-to-digital converters (ADC), one
for the CH0 and one for the CH1 photodiodes. The ALS integration time (ATIME) impacts both the resolution
and the sensitivity of the ALS reading. Integration of both channels occurs simultaneously and upon completion
of the conversion cycle, the results are transferred to the data registers (C0DATA and C1DATA). This data is
also referred to as channel count. The transfers are double-buffered to ensure data integrity.
ATIME(r1)
2.73 ms to 699 ms
C0DATAH(r0x15), C0DATA(r0x14)
AGL(r0x0D, b2)
CH0
ALS
CH0
Data
ALS Control
CH0
CH1
ADC
CH1
Data
C1DATAH(r0x17), C1DATA(r0x16)
CH1
AGAIN(r0x0F, b1:0)
1ꢀ, 8ꢀ, 16ꢀ, 120ꢀ Gain
Figure 7. ALS Operation
The registers for programming the integration and wait times are 2’s compliment values. The actual time can
be calculated as follows:
ATIME = 256 − Integration Time / 2.73 ms
Inversely, the time can be calculated from the register value as follows:
Integration Time = 2.73 ms × (256 − ATIME)
In order to reject the 50/60-Hz ripple present in fluorescent lighting, the integration time needs to
be programmed in multiples of 10 / 8.3 ms or the half cycle time. Both frequencies can be rejected with a
programmed value of 50 ms (ATIME = 0xED) or multiples of 50 ms (i.e. 100, 150, 200, 400, 600).
AGAIN can be programmed to 1×, 8×, 16×, or 120× with the 2-bit AGAIN field in the Control register (0x0F).
The gain, in terms of amount of gain, will be represented by the value AGAINx, i.e. AGAINx = 1, 8, 16, or 120.
With the AGL bit set, the 1× and 8× gains are lowered to 1/6× and 8/6×, respectively, to allow for operation up
to 60k lux. Do not enable AGL when AGAIN is 16× or 120×.
Lux Equation
The lux calculation is a function of CH0 channel count (C0DATA), CH1 channel count (C1DATA), ALS gain
(AGAINx), and ALS integration time in milliseconds (ATIME_ms). If an aperture, glass/plastic, or a light pipe
attenuates the light equally across the spectrum (300 nm to 1100 nm), then a scaling factor referred to as glass
attenuation (GA) can be used to compensate for attenuation. For a device in open air with no aperture or
glass/plastic above the device, GA = 1. If it is not spectrally flat, then a custom lux equation with new coefficients
should be generated. (See TAOS application note).
Counts per Lux (CPL) needs to be calculated only when ATIME or AGAIN is changed, otherwise it remains a
constant. The first segment of the equation (Lux1) covers fluorescent and incandescent light. The second
segment (Lux2) covers dimmed incandescent light. The final lux is the maximum of Lux1, Lux2, or 0.
CPL = (ATIME_ms × AGAINx) / (GA × 60)
Lux1 = (1 × C0DATA − 1.87 × C1DATA) / CPL
Lux2 = (0.63 × C0DATA − 1 × C1DATA) / CPL
Lux = MAX(Lux1, Lux2, 0)
Copyright E 2012, TAOS Inc.
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r
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Interrupts
The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for
light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s
status is available in the status register (0x13), the output of the interrupt state can be enabled using the ALS
interrupt enable (AIEN) fields in the enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level. An
interrupt can be generated when the ALS CH0 data (C0DATA) falls outside of the desired light level range, as
determined by the values in the ALS interrupt low threshold registers (AILTx) and ALS interrupt high threshold
registers (AIHTx).
It is important to note that the thresholds are evaluated in sequence, first the low threshold, then the high
threshold. As a result, if the low threshold is set above the high threshold, the high threshold is ignored and only
the low threshold is evaluated.
To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows
the user to specify the number of consecutive out-of-range ALS occurrences before an interrupt is generated.
The persistence filter register (0x0C) allows the user to set the ALS persistence filter (APERS) value. See the
persistence filter register for details on the persistence filter values. Once the persistence filter generates an
interrupt, it will continue until a special function interrupt clear command is received (see command register).
AIHTH(r07), AIHTL(r06)
APERS(r0x0C, b3:0)
Upper Limit
ALS Persistence
CH0
ADC
CH0
Data
Lower Limit
CH0
AILTH(r05), AILTL(r04)
Figure 8. Programmable Interrupt
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r
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
System State Machine Timing
The system state machine shown in Figure 6 provides an overview of the states and state transitions that
provide system control of the device. This section highlights the programmable features, which affect the state
machine cycle time, and provides details to determine system level timing.
When the power management feature is enabled (WEN), the state machine will transition in turn to the Wait
state. The wait time is determined by WLONG, which extends normal operation by 12× when asserted, and
WTIME. The formula to determine the wait time is given in the box associated with the Wait state in Figure 9.
When the ALS feature is enabled (AEN), the state machine will transition through the ALS Init and ALS ADC
states. The ALS Init state takes 2.73 ms, while the ALS ADC time is dependent on the integration time (ATIME).
The formula to determine ALS ADC time is given in the associated box in Figure 9. If an interrupt is generated
as a result of the ALS cycle, it will be asserted at the end of the ALS ADC state and transition to the Sleep state
if SAI is enabled.
Sleep
2
I C Start
!PON
WEN
& AEN
Idle
INT & SAI
!WEN
& AEN
ATIME: 1 ~ 256 steps
Time: 2.73 ms/step
Range: 2.73 ms ~ 699 ms
ALS
ADC
Wait
ALS
Init
WTIME: 1 ~ 256 steps
WLONG = 0
2.73 ms/step
WLONG = 1
Time: 2.73 ms
Time:
32.8 ms/step
32.8 ms ~ 8.39s
Range: 2.73 ms ~ 699 ms
Note: PON, WEN, AEN, and SAI are fields in the Enable register (0x00).
Figure 9. Detailed State Diagram
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
I2C Protocol
2
Interface and control are accomplished through an I C serial compatible interface (standard or fast mode) to
a set of registers that provide access to device control functions and output data. The devices support the 7-bit
2
I C addressing protocol.
2
The I C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure 10).
During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the
first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the
register address from the previous command will be used for data access. Likewise, if the MSB of the command
is not set, the device will write a series of bytes at the address stored in the last valid command with a register
address. The command byte contains either control information or a 5-bit register address. The control
commands can also be used to clear interrupts.
2
2
The I C bus protocol was developed by Philips (now NXP). For a complete description of the I C protocol, please
2
review the NXP I C design specification at http://www.i2c−bus.org/references/.
A
N
P
R
S
Acknowledge (0)
Not Acknowledged (1)
Stop Condition
Read (1)
Start Condition
Sr
W
Repeated Start Condition
Write (0)
... Continuation of protocol
Master-to-Slave
Slave-to-Master
1
7
1
1
8
1
8
1
1
...
...
S
Slave Address
W
A
Command Code
A
Data Byte
A
P
2
I C Write Protocol
1
7
1
1
8
1
8
1
1
S
Slave Address
R
A
Data
A
Data
A
P
2
I C Read Protocol
1
7
1
1
8
1
1
7
1
1
S
Slave Address
W
A
Command Code
A
Sr
Slave Address
R
A
8
1
8
1
1
...
Data
A
Data
A
P
2
I C Read Protocol — Combined Format
2
Figure 10. I C Protocols
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TSL2572
LIGHT-TO-DIGITAL CONVERTER
TAOS132 − MARCH 2012
Register Set
The device is controlled and monitored by data registers and a command register accessed through the serial
interface. These registers provide for a variety of control functions and can be read to determine results of the
ADC conversions. The register set is summarized in Table 1.
Table 1. Register Address
ADDRESS
−−
RESISTER NAME
COMMAND
ENABLE
ATIME
R/W
W
REGISTER FUNCTION
Specifies register address
RESET VALUE
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ID
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x0C
0x0D
0x0F
0x12
0x13
0x14
0x15
0x16
0x17
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Enables states and interrupts
ALS time
WTIME
Wait time
AILTL
ALS interrupt low threshold low byte
ALS interrupt low threshold high byte
ALS interrupt high threshold low byte
ALS interrupt high threshold high byte
Interrupt persistence filters
Configuration
AILTH
AIHTL
AIHTH
PERS
CONFIG
CONTROL
ID
Control register
Device ID
STATUS
C0DATA
C0DATAH
C1DATA
C1DATAH
R
Device status
0x00
0x00
0x00
0x00
0x00
R
CH0 ADC low data register
CH0 ADC high data register
CH1 ADC low data register
CH1 ADC high data register
R
R
R
2
The mechanics of accessing a specific register depends on the specific protocol used. See the section on I C
protocols on the previous pages. In general, the COMMAND register is written first to specify the specific
control/status register for following read/write operations.
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Command Register
The command registers specifies the address of the target register for future write and read operations.
Table 2. Command Register
7
6
5
4
3
2
ADD
1
0
Reset
0x00
COMMAND
COMMAND
TYPE
FIELD
COMMAND
TYPE
BITS
7
DESCRIPTION
Select Command Register. Must write as 1 when addressing COMMAND register.
Selects type of transaction to follow in subsequent data transfers:
6:5
FIELD VALUE
DESCRIPTION
00
01
10
11
Repeated byte protocol transaction
Auto-increment protocol transaction
Reserved — Do not use
Special function — See description below
Transaction type 00 will repeatedly read the same register with each data access.
Transaction type 01 will provide an auto-increment function to read successive register bytes.
ADD
4:0
Address field/special function field. Depending on the transaction type, see above, this field either
specifies a special function command or selects the specific control-status-register for following write and
read transactions. The field values listed below apply only to special function commands:
FIELD VALUE
00000
DESCRIPTION
Normal — no action
ALS interrupt clear
00110
other
Reserved — Do not write
The ALS interrupt clear special function clears any pending ALS interrupt and is self clearing.
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Enable Register (0x00)
The ENABLE register is used to power the device on/off, enable functions, and interrupts.
Table 3. Enable Register
7
6
5
4
3
2
1
0
Reset
0x00
Reserved
SAI
Reserved
AIEN
WEN
Reserved
AEN
PON
ENABLE
FIELD
BITS
DESCRIPTION
Reserved
7
Reserved. Write as 0.
Sleep after interrupt. When asserted, the device will power down at the end of an ALS cycle if an interrupt has
been generated.
SAI
6
Reserved
AIEN
5
4
Reserved. Write as 0.
ALS interrupt mask. When asserted, permits ALS interrupts to be generated.
Wait Enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the
wait timer.
WEN
3
Reserved
AEN
2
1
Reserved. Write as 0.
ALS Enable. This bit actives the two channel ADC. Writing a 1 activates the ALS. Writing a 0 disables the ALS.
Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a
1 activates the oscillator. Writing a 0 disables the oscillator.
PON
0
ALS Time Register (0x01)
The ALS time register controls the internal integration time of the ALS channel ADCs in 2.73 ms increments.
Upon power up, the ALS time register is set to 0xFF.
Table 4. ALS Time Register
FIELD
BITS
DESCRIPTION
INTEG_CYCLES
ATIME
7:0
VALUE
0xFF
0xF6
TIME
MAX COUNT
1024
1
2.73 ms
27.3 ms
101 ms
175 ms
699 ms
10
37
64
256
10240
0xDB
0xC0
0x00
37888
65535
65535
Wait Time Register (0x03)
Wait time is set 2.73 ms increments unless the WLONG bit is asserted in which case the wait times are 12×
longer. WTIME is programmed as a 2’s complement number. Upon power up, the wait time register is set to
0xFF.
Table 5. Wait Time Register
FIELD
BITS
DESCRIPTION
TIME (WLONG = 0)
WTIME
7:0
REGISTER VALUE
WAIT TIME
TIME (WLONG = 1)
0.033 sec
0xFF
0xB6
0x00
1
2.73 ms
202 ms
699 ms
74
2.4 sec
256
8.4 sec
NOTE: The Wait Time Register should be configured before AEN is asserted.
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ALS Interrupt Threshold Registers (0x04 − 0x07)
The ALS interrupt threshold registers provides the values to be used as the high and low trigger points for the
comparison function for interrupt generation. If C0DATA crosses below the low threshold specified, or above
the higher threshold, an interrupt is asserted on the interrupt pin.
Table 6. ALS Interrupt Threshold Registers
REGISTER
AILTL
ADDRESS
0x04
BITS
7:0
DESCRIPTION
ALS low threshold lower byte
ALS low threshold upper byte
ALS high threshold lower byte
ALS high threshold upper byte
AILTH
0x05
7:0
AIHTL
0x06
7:0
AIHTH
0x07
7:0
Persistence Filter Register (0x0C)
The persistence filter register controls the interrupt capabilities of the device. Configurable filtering is provided
to allow interrupts to be generated after every ADC cycle or if the ADC cycle has produced a result that is outside
of the values specified by threshold register for some specified amount of time. ALS interrupts are generated
using C0DATA.
Table 7. Persistence Filter Register
7
6
5
4
3
2
1
0
Reset
0x00
PERS
FIELD
Reserved
APERS
DESCRIPTION
BITS
7:4
Reserved
APERS
Reserved. Write as 0.
ALS Interrupt persistence filter. Controls rate of ALS interrupt to the host processor.
3:0
FIELD VALUE
0000
0001
0010
0011
MEANING
INTERRUPT PERSISTENCE FUNCTION
Every ALS cycle generates an interrupt
Every
1
1 value outside of threshold range
2 consecutive values out of range
3 consecutive values out of range
5 consecutive values out of range
10 consecutive values out of range
15 consecutive values out of range
20 consecutive values out of range
25 consecutive values out of range
30 consecutive values out of range
35 consecutive values out of range
40 consecutive values out of range
45 consecutive values out of range
50 consecutive values out of range
55 consecutive values out of range
60 consecutive values out of range
2
3
0100
0101
0110
5
10
15
20
25
30
35
40
45
50
55
60
0111
1000
1001
1010
1011
1100
1101
1110
1111
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Configuration Register (0x0D)
The configuration register sets the wait long time and ALS gain level.
Table 8. Configuration Register
7
6
5
4
3
2
1
0
Reset
0x00
CONFIG
FIELD
AGL
WLONG
Reserved
Reserved
BITS
DESCRIPTION
Reserved
7:3
Reserved. Write as 0.
ALS gain level. When asserted, the 1× and 8× ALS gain (AGAIN) modes are scaled by 0.16. Otherwise,
AGL
2
AGAIN is scaled by 1. Do not use with AGAIN greater than 8×.
Wait Long. When asserted, the wait cycles are increased by a factor 12× from that programmed in the
WLONG
1
0
WTIME register.
Reserved
Reserved. Write as 0.
Control Register (0x0F)
The Control register provides ALS gain control to the analog block.
Table 9. Control Register
7
6
5
4
3
2
1
0
Reset
0x00
CONTROL
AGAIN
Reserved
FIELD
Reserved
AGAIN
BITS
7:2
DESCRIPTION
Reserved. Write as 0.
ALS Gain.
1:0
FIELD VALUE
ALS GAIN VALUE
00
01
10
11
1× gain
8× gain
16× gain
120× gain
ID Register (0x12)
The ID Register provides the value for the part number. The ID register is a read-only register.
Table 10. ID Register
7
6
5
4
3
2
1
0
Reset
ID
ID
ID
FIELD
BITS
DESCRIPTION
0x34= TSL25721 & TSL25725
0x3D = TSL25723 & TSL25727
ID
7:0
Part number identification
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Status Register (0x13)
The Status Register provides the internal status of the device. This register is read only.
Table 11. Status Register
7
6
5
4
3
2
1
0
Reset
0x00
STATUS
FIELD
Reserved
AINT
Reserved
AVALID
BIT
7:5
4
DESCRIPTION
Reserved
AINT
Reserved. Bits read as 0.
ALS Interrupt. Indicates that the device is asserting an ALS interrupt.
Reserved. Bits read as 0.
Reserved
3:1
ALS Valid. Indicates that the ALS channels have completed an integration cycle after AEN has been
asserted.
AVALID
0
ADC Channel Data Registers (0x14 − 0x17)
2
ALS data is stored as two 16-bit values. To ensure the data is read correctly, a two-byte read I C transaction
should be used with auto increment protocol bits set in the command register. With this operation, when the
lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent
read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles
end between the reading of the lower and upper registers.
Table 12. ADC Channel Data Registers
REGISTER
C0DATA
ADDRESS
0x14
BITS
7:0
DESCRIPTION
ALS CH0 data low byte
C0DATAH
C1DATA
0x15
7:0
ALS CH0 data high byte
ALS CH1 data low byte
ALS CH1 data high byte
0x16
7:0
C1DATAH
0x17
7:0
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APPLICATION INFORMATION: HARDWARE
Typical Hardware Application
A typical hardware application circuit is shown in Figure 11. A 1-μF low-ESR decoupling capacitor should be
placed as close as possible to the V pin.
DD
V
DD
V
BUS
V
DD
R
R
R
PI
P
P
1 mF
TSL2572
INT
SCL
GND
SDA
Figure 11. Typical Application Hardware Circuit
2
2
V
BUS
in Figure 11 refers to the I C bus voltage, which is either V or 1.8 V. Be sure to apply the specified I C
DD
bus voltage shown in the Available Options table for the specific device being used.
2
The I C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R )
P
2
2
value is a function of the I C bus speed, the I C bus voltage, and the capacitive load. The TAOS EVM running
at 400 kbps, uses 1.5-kΩ resistors. A 10-kΩ pull-up resistor (R ) can be used for the interrupt line.
PI
PCB Pad Layout
Suggested land pattern based on the IPC−7351B Generic Requirements for Surface Mount Design and Land
Pattern Standard (2010) for the small outline no-lead (SON) package is shown in Figure 12.
2.70
1.20
1.20
0.35 ꢀ 6
0.65
0.65
TOP VIEW
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 12. Suggested FN Package PCB Layout
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PACKAGE INFORMATION
PACKAGE FN
TOP VIEW
Dual Flat No-Lead
398 ꢂ 10
PIN OUT
TOP VIEW
PIN 1
VDD
1
6 SDA
5 INT
4 NC
355
ꢂ 10
2000 ꢂ 100
SCL 2
GND 3
2000
ꢂ 100
Photodiode Array Area
END VIEW
SIDE VIEW
295
Nominal
650 ꢂ 50
203 ꢂ 8
650
BSC
300
ꢂ 50
BOTTOM VIEW
C
of Photodiode Array Area
(Note B)
C
L of Solder Contacts
L
1 Nominal
144 Nominal
C
L of Solder Contacts
of Photodiode Array Area (Note B)
C
L
PIN 1
Pb
750 ꢂ 150
Lead Free
NOTES: A. All linear dimensions are in micrometers.
B. The die is centered within the package within a tolerance of 75 μm.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 13. Package FN — Dual Flat No-Lead Packaging Configuration
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CARRIER TAPE AND REEL INFORMATION
TOP VIEW
2.00 ꢂ 0.05
1.75
ꢃ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢂ 0.05
ꢃ 1.00
ꢂ 0.25
A
A
B
DETAIL A
DETAIL B
5ꢁ Max
5ꢁ Max
0.254
2.18 ꢂ 0.05
2.18 ꢂ 0.05
ꢂ
0
.
0
2
0.83 ꢂ 0.05
B
o
A
o
K
o
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
D. Each reel is 178 millimeters in diameter and contains 3500 parts.
E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
G. This drawing is subject to change without notice.
Figure 14. Package FN Carrier Tape
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SOLDERING INFORMATION
The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.
The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Table 13. Solder Reflow Profile
PARAMETER
Average temperature gradient in preheating
Soak time
REFERENCE
DEVICE
2.5°C/sec
t
2 to 3 minutes
Max 60 sec
Max 50 sec
Max 10 sec
260°C
soak
Time above 217°C (T1)
t
1
Time above 230°C (T2)
t
2
Time above T
−10°C (T3)
t
3
peak
Peak temperature in reflow
T
peak
Temperature gradient in cooling
Max −5°C/sec
Not to scale — for reference only
T
peak
T
3
T
T
2
1
Time (sec)
t
t
t
3
2
1
t
soak
Figure 15. Solder Reflow Profile Graph
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STORAGE INFORMATION
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package. To ensure the package contains
the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping.
Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect
them from ambient moisture during shipping, handling, and storage before use.
Shelf Life
The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on
the bag when stored under the following conditions:
Shelf Life: 12 months
Ambient Temperature: < 40°C
Relative Humidity: < 90%
Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator
Card shows that the devices were exposed to conditions beyond the allowable moisture region.
Floor Life
The FN package has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices
removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices
are stored under the following conditions:
Floor Life: 168 hours
Ambient Temperature: < 30°C
Relative Humidity: < 60%
If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior
to solder reflow or dry packing.
Rebaking Instructions
When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
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PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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