TSL2561 [AMSCO]
LIGHT-TO-DIGITAL CONVERTER; 光 - 数字转换器
| 型号： | TSL2561 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | LIGHT-TO-DIGITAL CONVERTER |
| 文件： | 总43页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
r
r
TAOS059Q − NOVEMBER 2009
PACKAGE CS
6-LEAD CHIPSCALE
(TOP VIEW)
D Approximates Human Eye Response
D Programmable Interrupt Function with
User-Defined Upper and Lower Threshold
Settings
6 SDA
5 INT
4 SCL
VDD
1
D 16-Bit Digital Output with SMBus (TSL2560)
2
at 100 kHz or I C (TSL2561) Fast-Mode at
ADDR SEL 2
GND 3
400 kHz
D Programmable Analog Gain and Integration
Time Supporting 1,000,000-to-1 Dynamic
Range
PACKAGE T
6-LEAD TMB
(TOP VIEW)
D Automatically Rejects 50/60-Hz Lighting
Ripple
D Low Active Power (0.75 mW Typical) with
Power Down Mode
6 SDA
VDD
1
D RoHS Compliant
5 INT
ADDR SEL 2
GND 3
4 SCL
PACAGE FN
DUAL FLAT NO-LEAD
(TOP VIEW)
Description
The TSL2560 and TSL2561 are light-to-digital
converters that transform light intensity to a digital
signal output capable of direct I C (TSL2561) or
2
VDD
1
6 SDA
5 INT
4 SCL
SMBus (TSL2560) interface. Each device com-
bines one broadband photodiode visble plus
infrared) and one infrared-respondng photodiode
on a single CMOS integrated circuit capable of
providing a near-photopic reonse over an
effective 20-bit dynamic range 6-bit resolutio
Two integrating ADCs convert the photodio
currents to a digital output that represents the
irradiance measured on each channel. This digital
output can be input to a microprocessor where
illuminance (ambient light level) in lux s derived
using an empirical formula to aoximate the
human eye response. The TSL2560 device
permits an SMB-Alert ste iterrupt, and the
TSL2561 device supporta traditional level style
interrupt that remains asserted until the firmware
clears it.
DR SEL 2
GND 3
PACKAGE CL
6-LEAD ChipLED
(TOP VIEW)
SDA 5
INT 6
4 SCL
3 ADDR SEL
2 GND
VDD
1
Package Drawings are Not to Scale
While useful r general purpose light sensing applications, the TSL2560/61 devices are designed particularly
for display panes (LCD, OLED, etc.) with the purpose of extending battery life and providing optimum viewing
in diversliging conditions. Display panel backlighting, which can account for up to 30 to 40 percent of total
platfm power, can be automatically managed. Both devices are also ideal for controlling keyboard illumination
basupon ambient lighting conditions. Illuminance information can further be used to manage exposure
control in digital cameras. The TSL2560/61 devices are ideal in notebook/tablet PCs, LCD monitors, flat-panel
teevisions, cell phones, and digital cameras. In addition, other applications include street light control, security
lighting, sunlight harvesting, machine vision, and automotive instrumentation clusters.
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
Texas Advarnced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
www.taosinc.com
1
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
Functional Block Diagram
Channel 0
Visible and IR
Integrating
A/D Converter
Channel 1
IR Only
V
= 2.7 V to 3.5 V
DD
Command
Register
ADC
Register
Address Select
Interrupt
ADDR SEL
INT
SCL
SA
Two-Wire Serial Interface
Detailed Description
The TSL2560 and TSL2561 are second-generation ambienight snsor devices. Each cntains two integrating
analog-to-digital converters (ADC) that integrate currents frm twphotodiodes. Interation of both channels
occurs simultaneously. Upon completion of the convion cycle, the conversion result is transferred to the
Channel 0 and Channel 1 data registers, respectivelhe transfers are uble-buffered to ensure that the
integrity of the data is maintained. After the transfer, the evice automatically begins the next integration cycle.
2
Communication to the device is accomplished through a standard, two-wire SMBus or I C serial bus.
Consequently, the TSL256x device can be easily connected to a crocontroller or embedded controller. No
external circuitry is required for signal coditining, thereby vinPCB real estate as well. Since the output
of the TSL256x device is digital, the ouput s effectively immune to noise when compared to an analog signal.
The TSL256x devices also supporan interrupt featurthat simplifies and improves system efficiency by
eliminating the need to poll a sensor a light intensvale. The primary purpose of the interrupt function is
to detect a meaningful change in light intensity. The pt of a meaningful change can be defined by the user
both in terms of light intensity and time, or persistence, of that change in intensity. The TSL256x devices have
the ability to define a threshold above and belothe current light level. An interrupt is generated when the value
of a conversion exceeds either of these limits.
Available Options
DEVICE
INTERFAE
SMBu
PACKAGE − LEADS
Chipscale
PACKAGE DESIGNATOR ORDERING NUMBER
TSL2560
TSL2560
TSL2560
TSL2560
TSL2561
TS1
TS56
TSL2561
CS
T
TSL2560CS
TSL2560T
SMBus
TMB-6
MBus
Dual Flat No-Lead − 6
ChipLED-6
FN
CL
CS
T
TSL2560FN
TSL2560CL
TSL2561CS
TSL2561T
SMBus
2
I C
Chipscale
2
I C
TMB-6
2
I C
Dual Flat No-Lead − 6
ChipLED-6
FN
CL
TSL2561FN
TSL2561CL
2
I C
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
2
www.taosinc.com
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
Terminal Functions
TERMINAL
CS, T, FN
CL
PKG
NO.
TYPE
DESCRIPTION
NAME
PKG
NO.
ADDR SEL
GND
2
3
5
4
6
1
3
2
6
4
5
1
I
SMBus device select — three-state
Power supply ground. All voltages are referenced to GND.
Level or SMB Alert interrupt — open drain.
INT
O
I
SCL
SMBus serial clock input terminal — clock signal for SMBus serial data.
SMBus serial data I/O terminal — serial data I/O for SMBus.
Supply voltage.
SDA
I/O
V
DD
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 V
DD
Digital output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.8 V
O
Digital output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 mA to 20 mA
O
Storage temperature range, T
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” mae ermanent damato the device. These are stress ratings only, and
functional operation of the device at these or any other conditions yond those indicated unr “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extendd periods may afect evice reliability.
NOTE 1: All voltages are with respect to GND.
Recommended Operating Conditons
MIN NOM
MAX
3.6
UNIT
V
Supply voltage, V
2.7
3
DD
Operating free-air temperature, T
−30
70
°C
A
SCL, SDA input low voltage, V
−0.5
2.1
0.8
3.6
V
V
IL
SCL, SDA input high voltage, V
IH
Electrical Characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETR
TEST CONDITIONS
MIN
TYP
0.24
3.2
MAX
0.6
15
UNIT
mA
μA
V
Active
I
Supply current
DD
Power down
3 mA sink current
6 mA sink current
0
0
0.4
0.6
5
V
I
INT, SDA output ow voltage
Leage current
OL
V
−5
μA
LEAK
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
3
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
Operating Characteristics, High Gain (16ꢀ), VDD = 3 V, TA = 25ꢀ C, (unless otherwise noted) (see
Notes 2, 3, 4, 5)
TSL2560T, FN, & CL
TSL2560CS, TSL2561CS
TSL2561T, FN & CL
PARAMETER
TEST CONDITIONS
CHANNEL
UNIT
MIN
690
0
TYP
MAX
780
MIN
690
0
TYP
MAX
780
f
Oscillator frequency
735
735
kHz
osc
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
Ch0
Ch1
4
4
Dark ADC count value
E = 0, T = 402 ms
counts
e
int
0
4
0
4
65535
65535
37177
37177
5047
5047
1250
65535
65535
37177
37177
5047
5047
T
int
T
int
T
int
> 178 ms
Full scale ADC count
value (Note 6)
= 101 ms
= 13.7 ms
cun
750
700
1000
200
λ = 640 nm, T = 101 ms
p
int
2
E = 36.3 μW/cm
e
counts
counts
1000
820
1300
λ = 940 nm, T = 101 ms
p
int
2
E = 119 μW/cm
e
ADC count value
75
700
1000
190
1250
1300
λ = 640 nm, T = 101 ms
p
int
2
E = 41 μW/cm
e
1000
850
λ = 940 nm, T = 101 ms
p
int
2
E = 135 μW/cm
e
λ = 640 nm, T = 101 ms
0.15
0.69
0.20
2
7.5
5.5
8.4
6.9
36
0.25
0.95
0.14
0.70
0.19
0.85
24.4
4.6
7.4
6.3
35
0.24
1
ADC count value ratio:
Ch1/Ch0
p
int
λ = 940 nm, T = 101 ms
p
int
Ch0
Ch1
Ch0
Ch1
C
Ch1
C0
Ch1
λ = 640 nm, T = 01 ms
p
int
counts/
(μW/
R
R
Irradiance responsivity
Illuminance responsivity
e
2
cm )
λ = 940 nmT 101 ms
p
i
Fluorescent light source:
= 402 ms
T
int
4
3.8
129
67
counts/
lux
v
144
72
Incandescent light source:
= 402 ms
T
int
Fluorescent light sorce:
= 402 ms
0.11
0.5
0.11
0.52
T
int
ADC count value ratio:
Ch1/Ch0
Incandescnt light source:
= 402 s
T
int
Ch0
Ch1
Ch0
Ch1
2.3
0.25
9
2.2
0.24
8.1
Fluorescet light source:
= 02 ms
T
nt
Illuminance responsivity,
low gain mode (Note 7)
counts/
lux
R
v
Incndescent light source:
= 402 ms
nt
4.5
4.2
Fluorescent light source:
= 402 ms
0.65
0.60
1
1
1.35
1.40
0.65
0.60
1
1
1.35
1.40
(Sensor Lux) /
(actual Lux), higgan
mode (N)
T
int
Incandescent light source:
= 402 ms
T
int
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
4
www.taosinc.com
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance E is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
e
λp = 640 nm and spectral halfwidth Δλ½ = 17 nm.
4. The 940 nm irradiance E is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
e
λp = 940 nm and spectral halfwidth Δλ½ = 40 nm.
5. Integration time T , is dependent on internal oscillator frequency (f ) and on the integration field value in the timing register as
int
osc
described in the Register Set section. For nominal f
= 735 kHz, nominal T = (number of clock cycles)/f
.
osc
int
osc
Field value 00: T = (11 × 918)/f
= 13.7 ms
= 101 ms
= 402 ms
osc
int
osc
Field value 01: T = (81 × 918)/f
int
osc
Field value 10: T = (322 × 918)/f
int
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods analso
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11 × 918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81 × 918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for T = 178 ms for nominal f
= 735 kHz.
int
osc
7. Low gain mode has 16ꢁ lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based n msured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtaineith a commercial luxmeter. e rae of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 9nm optical parameters. evices are not 100% tested with
fluorescent or incandescent light sources.
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
5
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
AC Electrical Characteristics, VDD = 3 V, TA = 25ꢀ C (unless otherwise noted)
†
PARAMETER
Conversion time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
12
100
400
ms
(CONV)
2
Clock frequency (I C only)
0
10
400
100
kHz
kHz
μs
f
t
t
(SCL)
Clock frequency (SMBus only)
Bus free time between start and stop condition
1.3
(BUF)
Hold time after (repeated) start condition. After
this period, the first clock is generated.
0.6
μs
(HDSTA)
t
t
t
t
t
t
t
t
t
Repeated start condition setup time
Stop condition setup time
Data hold time
0.6
0.6
0
μs
μs
s
ns
μs
μs
ms
ns
ns
pF
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
(TIMEOUT)
F
0.9
Data setup time
100
1.3
0.6
25
SCL clock low period
SCL clock high period
Detect clock/data low timeout (SMBus only)
Clock/data fall time
35
300
300
10
Clock/data rise time
R
C
Input pin capacitance
i
†
Specified by design and characterization; not production tested.
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
6
www.taosinc.com
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
t
t
(R)
t
(F)
(LOW)
V
IH
SCL
SDA
V
IL
t
t
t
(HDSTA)
(HIGH)
(SUSTA)
t
t
t
(SUSTO)
t
(BUF)
(HDDAT)
(SUDAT)
V
V
IH
IL
P
S
S
P
Stop
Condition
Start
Condition
Start
Stop
t
(LOWSEXT)
SCL
SCL
ACK
ACK
t
t
t
(LOWMEXT)
(LOWMEXT)
(LOWMEXT)
SCL
SDA
Figure 1. ing Diagrams
1
9
1
9
SCL
SDA
A6 A5
A4
A3
A1 A0 R/W
D7 D6
D5 D4 D3 D2
D1 D0
Start by
Master
K by
L256x
ACK by Stop by
TSL256x Master
Frame 1 SMBus Slave Address yte
Frame 2 Command Byte
Figure 2. Example Timing Diagram for SMBus Send Byte Format
1
9
1
9
SCL
SDA
A6 A5
A4
A3
A2 A1 A0 R/W
D7 D6
D5 D4 D3 D2
D1 D0
Start by
Master
ACK by
TSL256x
NACK by Stop by
Master Master
Frame 1 SMBus Slave Address Byte
Frame 2 Data Byte From TSL256x
Figure 3. Example Timing Diagram for SMBus Receive Byte Format
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
7
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
TYPICAL CHARACTERISTICS
SPECTRAL RESPONSIVITY
1
0.8
0.6
Channel 0
Photodiode
0.4
0.2
0
Channel
Photodde
300 400 500 600 700 900 1000 110
λ − Wavelengt− nm
Figure 4
NORMALIZED RESPONSIVITY
NORMALIZED RESPONSIVITY
vs.
vs.
ANGULAR DISPLACEMENT — CS ACKGE
ANGULAR DISPLACEMENT — T PACKAGE
1.0
0.8
1.0
0.8
0.6
0.4
0.6
0.4
0.2
0
0.2
0
90
90
−90
−60
−30
0
30
60
−90
−60
−30
0
30
60
ꢀ
−
A
n
g
u
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
ꢀ
−
A
n
g
u
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
Figure 5
Figure 6
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
8
www.taosinc.com
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
NORMALIZED RESPONSIVITY
vs.
ANGULAR DISPLACEMENT — CL PACKAGE
NORMALIZED RESPONSIVITY
vs.
ANGULAR DISPLACEMENT — FN PACKAGE
1.0
1.0
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0
0.2
0
90
−
−60
−30
30
60
90
−90
−60
−30
0
30
60
ꢀ
−
A
g
l
a
D
i
s
p
l
a
c
e
m
e
n
t
−
°
ꢀ
−
A
n
g
u
l
a
r
D
i
s
p
l
a
c
e
m
e
n
t
−
°
Figure 7
Figure 8
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
www.taosinc.com
9
TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
The TSL256x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion
of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,
respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
Digital Interface
Interface and control of the TSL256x is accomplished through a two-wire serial interface to a set of regsts
that provide access to device control functions and output data. The serial interface is compatible with Sysm
2
Management Bus (SMBus) versions 1.1 and 2.0, and I C bus Fast-Mode. The TSL256x offers threslave
addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1.
Table 1. Slave Address Selection
ADDR SEL TERMINAL LEVEL
SLAVE ADDESS
010101
SMB ALERT ADRES
0001100
GND
Float
VDD
0111001
00100
1
0001100
2
NOTE: The Slave and SMB Alert Addresses are 7 bits. Please note the SMBs and I C protocols opages 9 through 12. A read/write bit should
be appended to the slave address by the master device to properly communicate witthe TSL256X device.
SMBus and I2C Protocols
Each Send and Write protocol is, esentially, a series bytes. A byte sent to the TSL256x with the most
significant bit (MSB) equal to 1 will nterpreted as OMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), is used to select the destination for the subsequent
byte(s) received. The TSL256x responds to any Receive Byte requests with the contents of the register
specified by the stored register select address
The TSL256X implements the following protocols of the SMB 2.0 specification:
D
D
D
D
D
D
D
Send Byte Protocol
Receive Byte Protocol
Write Byte Protocol
Write Word Protoco
Read Word Protocol
Block Write Prtocol
Block Red Potocol
2
TTSL56X implements the following protocols of the Philips Semiconductor I C specification:
D
D
I Write Protocol
2
I C Read (Combined Format) Protocol
Copyright E 2009, TAOS Inc.
The LUMENOLOGY r Company
r
r
10
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte
following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains
the byte count (i.e. the number of bytes to be transferred). The TSL2560 (SMBus) device ignores this field and
extracts this information by counting the actual number of bytes transferred before the Stop condition is
detected.
2
2
When an I C Write or I C Read (Combined Format) is initiated, the byte count is also ignored but follows the
2
SMBus protocol specification. Data bytes continue to be transferred from the TSL2561 (I C) device to Master
until a NACK is sent by the Master.
The data formats supported by the TSL2560 and TSL2561 devices are:
2
D
D
Master transmitter transmits to slave receiver (SMBus and I C):
−
The transfer direction in this case is not changed.
Master reads slave immediately after the first byte (SMBus only):
−
At the moment of the first acknowledgment (provided by the slave receiver) he master transmitter
becomes a master receiver and the slave receiver becomes a slave transmiter.
2
D
Combined format (SMBus and I C):
−
During a change of direction within a transfer, te maer repeats both a STRT condition and the slave
address but with the R/W bit reversed. In thicase, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and a STOP condition.
For a complete description of SMBus proocols, please reviw the SMBus Specification at
2
2
http://www.smbus.org/specs. For a complete description of I C protocls, please review the I C Specification
at http://www.semiconductors.philips.com.
1
7
1
1
A
8
1
1
S
Sve Address
Wr
Data Byte
A
X
P
A
Acknowledge (this it position may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
Rd
S
Read (bit valuof 1)
Start Cond
Sr
Wr
X
Rpeated Start Condition
Write (bit value of 0)
Shown under a field indicates that that field is required to have a value of X
... Continuation of protocol
Master-to-Slave
Slave-to-Master
2
Figure 9. SMBus and I C Packet Protocol Element Key
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1
7
1
1
8
1
1
S
Slave Address
Wr
A
Data Byte
A
P
Figure 10. SMBus Send Byte Protocol
1
7
1
1
8
1
A
1
1
S
Slave Address
Rd
A
Data Byte
P
Figure 11. SMBus Receive Byte Protocol
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Code
A
Data Byte
A
P
Figure 12. SMBus Write Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
A
1
1
S
Slave Address
Wr
A
Command Code
A
S
ve Address
Rd
Data Byte Low
P
Figure 13. SMBus Read Byte Prcol
1
7
1
1
8
1
1
8
1
1
S
Slave Address
Wr
A
Comnd Code
A
DatByte Low
A
Data Byte High
A
P
Figure 14. SMBus Write Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
...
S
Slave Address
Wr
A
Command C
A
S
Slave Address
Rd
A
Data Byte Low
A
8
1
A
1
1
Data Byte High
P
Figure 15. SMBus Read Word Protocol
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1
7
1
1
8
1
8
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
1
...
Data Byte 2
A
Data Byte N
A
P
2
Figure 16. SMBus Block Write or I C Write Protocols
2
NOTE: The I C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
1
7
1
1
8
1
1
7
1
1
8
1
...
S
Slave Address
Wr
A
Command Code
A
Sr Slave Address Rd
A
Byte Count = N
A
8
1
8
1
8
1
...
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
2
Figure 17. SMBus Block Read or I C Read (Combined Format) Protocols
2
NOTE: The I C read protocol does not use the Byte Count packet, and thMaster will continue receiving ata Bes until the Master initiates
a Stop Condition. See the Command Register on page 13 for aditional iormation regarding the Blk Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixten registers (three arreserved) and a command register
accessed through the serial interface. These registers provide for varety of control functions and can be read
to determine results of the ADC conversins. he register set is summarized in Table 2.
Table 2. Register ddress
ADDRESS
−−
RESISTER AME
COMND
REGISTER FUNCTION
Specifies regster address
0h
COROL
Conasic functions
1h
TIMING
Integran time/gain control
Low yte of low interrupt threshold
2h
THRESHLOWLOW
3h
THRESHLOHIGH High byte of low interrupt threshold
THRESHHIGHLW Low byte of high interrupt threshold
THRESHHIGIGH High byte of high interrupt threshold
4h
5h
6h
NTERRPT
−
Interrupt control
7h
Reserved
8h
CRC
Factory test — not a user register
Reserved
9h
−−
A
ID
Part number/ Rev ID
Reserved
Bh
−−
Ch
Dh
Eh
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
Fh
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
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Command Register
The command register specifies the address of the target register for subsequent read and write operations.
The Send Byte protocol is used to configure the COMMAND register. The command register contains eight bits
as described in Table 3. The command register defaults to 00h at power on.
Table 3. Command Register
7
CMD
0
6
CLEAR
0
5
WORD
0
4
BLOCK
0
3
2
1
0
0
0
COMMAND
ADDRESS
Reset Value:
0
0
FIELD
CMD
BIT
7
DESCRIPTION
Select command register. Must write as 1.
CLEAR
6
Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is selclearing.
SMB Write/Read Word Protocol. 1 indicates that this SMB transaction is using either he SB Write Word or
Read Word protocol.
WORD
BLOCK
5
4
Block Write/Read Protocol. 1 indicates that this transaction is using either the lock rite or the Block Read
protocol. See Note below.
Register Address. This field selects the specificontrol status register fofollowing write and read
commands according to Table 2.
ADDRESS
3:0
2
NOTE: An I C block transaction will continue until the Master sends a stop ition. See Figure 1nd Figure 17. Unlike the I2C protocol, the
SMBus read/write protocol requires a Byte Count. All four ADC Chnel Data Registers (Ch though Fh) can be read simultaneously in
a single SMBus transaction. This is the only 32-bit data block suppoted by the TSL250 SBus protocol. The BLOCK bit must be set
to 1, and a read condition should be initiated with a COMMAND CODE of 9Bh. By usina COMMAND CODE of 9Bh during an SMBus
Block Read Protocol, the TSL2560 device will automaticinsrt the appropriate Cont (Byte Count = 4) as illustrated in Figure 17.
A write condition should not be used in conjunction th the Bh register.
Control Register (0h)
The CONTROL register contains two bits and is primarily used to power the TSL256x device up and down as
shown in Table 4.
Tabe 4. Control Register
7
Resv
0
6
Resv
0
5
Rev
0
4
Resv
0
3
Resv
0
2
Resv
0
1
0
0
0
CONTROL
0h
POWER
Reset Value:
FIELD
BIT
DESCRIPTION
Resv
7:2
Resrved. Write as 0.
Power up/power down. By writing a 03h to this register, the device is powered up. By writing a 00h to this
register, the device is powered down.
POWER
1:0
NOTE: If a value of 03h is written, the value returned during a read cycle will be 03h. This feature can be
used to verify that the device is communicating properly.
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Timing Register (1h)
The TIMING register controls both the integration time and the gain of the ADC channels. A common set of
control bits is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.
Table 5. Timing Register
7
Resv
0
6
Resv
0
5
Resv
0
4
GAIN
0
3
Manual
0
2
Resv
0
1
1
0
0
TIMING
1h
INTEG
Reset Value:
FIELD
BIT
DESCRIPTION
Resv
7−5
Reserved. Write as 0.
Switches gain between low gain and high gain modes. Writing a 0 selects low gain (1×); ritina 1 selects
GAIN
4
3
high gain (16×).
Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an tegration cycle.
NOTE: This field only has meaning when INTEG = 11. It is ignored at all other ties.
Manual
Resv
2
Reserved. Write as 0.
INTEG
1:0
Integrate time. This field selects the integation te for each conversion.
Integration time is dependent on the INTEG FIELALUE and the internal clock frequency. Nominal integration
times and respective scaling between integration es scale proportnally as shown in Table 6. See Note 5
and Note 6 on page 5 for detailed information regading how the scale vaues were obtained; see page 22 for
further information on how to calculate lux.
Table 6. Integration me
INTEG FIELD ALU
SCALE
0.034
0.2
OMINAL INTEGRATION TIME
0
0
10
11
13.7 ms
101 ms
402 ms
N/A
−−
The manual timing control feature is used to manually start and stop the integration time period. If a particular
integration time period is required that s not listed in Table 6, then this feature can be used. For example, the
manual timing control can be used synchronize the TSL256x device with an external light source (e.g. LED).
A start command to begin integration can be initiated by writing a 1 to this bit field. Correspondingly, the
integration can be stopped by smply writing a 0 to the same bit field.
Interrupt Threshold Register (2h − 5h)
The interrupt theshold registers store the values to be used as the high and low trigger points for the comparison
function or interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
abothe high threshold specified, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW
and THRESHLOWHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold.
Registers THRESHHIGHLOW and THRESHHIGHHIGH provide the low and high bytes, respectively, of the
upper interrupt threshold. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 00h on power up.
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Table 7. Interrupt Threshold Register
REGISTER
ADDRESS
BITS
7:0
DESCRIPTION
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
2h
3h
4h
5h
ADC channel 0 lower byte of the low threshold
ADC channel 0 upper byte of the low threshold
ADC channel 0 lower byte of the high threshold
ADC channel 0 upper byte of the high threshold
7:0
7:0
7:0
NOTE: Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol should
not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted as the
COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information as desied.
The Write Word protocol should be used to write byte-paired registers. For example, the THRESHLOWLOW and THRESHLOWHIG
registers (as well as the THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16-bit ADC vale in
a single transaction.
Interrupt Control Register (6h)
The INTERRUPT register controls the extensive interrupt capabilities of the TSL256x. The SL256x permits
both SMB-Alert style interrupts as well as traditional level-style interrupts. The errupt persist bit field
(PERSIST) provides control over when interrupts occur. A alue 0 causes an interrut to occur after every
integration cycle regardless of the threshold settings. A vale of 1 results in an iterrupt after one integration
time period outside the threshold window. A value of (where N is 2 through15) results in an interrupt only if
the value remains outside the threshold window for N cecutive integraticycles. For example, if N is equal
to 10 and the integration time is 402 ms, then the total me is approximately seconds.
When a level Interrupt is selected, an interrupt is generated whenevethe last conversion results in a value
outside of the programmed threshold window. The iterrupt is actiow and remains asserted until cleared by
writing the COMMAND register with the CLER bit set.
In SMBAlert mode, the interrupt is simar to the traditional level style and the interrupt line is asserted low. To
clear the interrupt, the host responds to the SMBAlert by prforming a modified Receive Byte operation, in which
the Alert Response Address (ARA) placed in the slave ddress field, and the TSL256x that generated the
interrupt responds by returning its own address in thn most significant bits of the receive data byte. If more
than one device connected on the bus has pulled the SMBAlert line low, the highest priority (lowest address)
device will win communication rights via stanard rbitration during the slave address transfer. If the device
loses this arbitration, the interrupt will not be cleared. The Alert Response Address is 0Ch.
When INTR = 11, the interrupt is generated immediately following the SMBus write operation. Operation then
behaves in an SMBAlert mode, and thoftware set interrupt may be cleared by an SMBAlert cycle.
NOTE: Interrupts are based on the vale of hannl 0 only.
Table 8. Interrupt Control Register
7
Rsv
0
6
Resv
0
5
4
3
2
1
0
0
0
INTERRUPT
6h
INTR
PERSIST
Reset Value:
0
0
0
0
FEL
Resv
BITS
7:6
DESCRIPTION
Reserved. Write as 0.
INTR Control Select. This field determines mode of interrupt logic according to Table 9, below.
Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10, below.
INTR
5:4
PERSIST
3:0
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Table 9. Interrupt Control Select
INTR FIELD VALUE
READ VALUE
Interrupt output disabled
00
01
10
11
Level Interrupt
SMBAlert compliant
Test Mode: Sets interrupt and functions as mode 10
NOTE: Field value of 11 may be used to test interrupt connectivity in a system or to assist in debugging interrupt service routine soware
Table 10. Interrupt Persistence Select
PERSIST FIELD VALUE
INTERRUPT PERSIST FUNCTION
Every ADC cycle generates interrupt
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Any value outside of threshold range
2 integration time periods out of range
3 integration time periods out of range
4 integration time eriods out of range
5 integration time eriods ut of range
6 integratitime periods out of range
7 integratioe priods out of ran
8 integration me periods out of rge
9 integration time periods out orange
1nteation time periodt of range
1 integration time eriodout of range
12 integration time perds out of range
13 integration tme priods out of range
14 integration timperiods out of range
15 integme periods out of range
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ID Register (Ah)
The ID register provides the value for both the part number and silicon revision number for that part number.
It is a read-only register, whose value never changes.
Table 11. ID Register
7
6
−
5
−
4
−
3
−
2
1
−
0
−
ID
Ah
PARTNO
REVNO
Reset Value:
−
−
FIELD
BITS
DESCRIPTION
PARTNO
7:4
Part Number Identification:
FIELD VALUE
0000
DEVICE NUMBER
TSL2560CS
0001
TSL2561CS
0100
TSL2560T/FN/CL
TSL2561T/FN/CL
0101
REVNO
3:0
Revision number identification
ADC Channel Data Registers (Ch − Fh)
The ADC channel data are expressed as 16-bt values spread across two registers. The ADC channel 0 data
registers, DATA0LOW and DATA0HIGH provide the lower and ur bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DAA1IGH provide thlowr and upper bytes, respectively, of the ADC
value of channel 1. All channel data registrs are read-only and default to 00h on power up.
Tabl2. ADC Channel Data Registers
REGISTER
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
ADDRESS
BITS
70
DESCRIPTION
ADC channel 0 lower byte
Ch
Dh
Eh
Fh
7:
ADC channel 0 upper byte
ADC channel 1 lower byte
ADC channel 1 upper byte
7:0
7:0
The upper byte data registers cn ony be read following a read to the corresponding lower byte register. When
the lower byte register is red, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
integration cycles end between the reading of the lower and upper registers.
NOTE: The Read Word prool cbe used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
the DATA1LOW and ATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
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APPLICATION INFORMATION: SOFTWARE
Basic Operation
After applying V , the device will initially be in the power-down state. To operate the device, issue a command
DD
to access the CONTROL register followed by the data value 03h to power up the device. At this point, both ADC
channels will begin a conversion at the default integration time of 400 ms. After 400 ms, the conversion results
will be available in the DATA0 and DATA1 registers. Use the following pseudo code to read the data registers:
// Read ADC Channels Using Read Word Protocol − RECOMMENDED
Address = 0x39
//Slave addr – also 0x29 or 0x49
//Address the Ch0 lower data register and configure for Read Word
Command = 0xAC
//Set Command bit and Word bit
//Reads two bytes from sequential registers 0x0C and 0x0D
//Results are returned in DataLow and DataHigh variables
ReadWord (Address, Command, DataLow, DataHigh)
Channel0 = 256 * DataHigh + DataLow
//Address the Ch1 lower data register and cofigure for Read Wd
Command = 0xAE
//St bit fields 7 ad 5
//Reads two bytes from sequential registers 0x0E and 0x0F
//Results are returned in DataLow and taHigh variables
ReadWord (Address, Command, DataLow, DHigh)
Channel1 = 256 * DataHigh + DataLow
//Shift DataHgh to upper byte
// Read ADC Channels Using Read Byte Potocol
Address = 0x39
//Sve addr − also 0x29 or 0x49
/Address the Ch0 lower data register
//sult returned in DataLow
/Address the Ch0 upper data register
//Result returned in DataHigh
Command = 0x8C
ReadByte (Address, Comman, DtaLow)
Command = 0x8D
ReadByte (Address, Commd, DataHigh)
Channel0 = 256 * DataH+ DataLow
//Shift DataHigh to upper byte
Command = 0x8E
ReadByte (Address, Command, DatLow
Command = 0x8F
ReadByte (Address, Command, DataHigh)
Channel1 = 256 * DataHigh + DtaLow
//Address the Ch1 lower data register
//Result returned in DataLow
//Address the Ch1 upper data register
//Result returned in DataHigh
//Shift DataHigh to upper byte
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APPLICATION INFORMATION: SOFTWARE
Configuring the Timing Register
The command, timing, and control registers are initialized to default values on power up. Setting these registers
to the desired values would be part of a normal initialization or setup procedure. In addition, to maximize the
performance of the device under various conditions, the integration time and gain may be changed often during
operation. The following pseudo code illustrates a procedure for setting up the timing register for various
options:
// Set up Timing Register
//Low Gain (1x), integration time of 402ms (default value)
Address = 0x39
Command = 0x81
Data = 0x02
WriteByte(Address, Command, Data)
//Low Gain (1x), integration time of 101ms
Data = 0x01
WriteByte(Address, Command, Data)
//Low Gain (1x), integration time of 13.7ms
Data = 0x00
WriteByte(Address, Command, Data)
//High Gain (16x), integration time of 101
Data = 0x11
WriteByte(Address, Command, Data)
//Read data registers (see Basic Operation example)
//Perform Manual Integration
//Set up for manual integriowith Gain o1x
Data = 0x03
//Set manual integration me – device converting
WriteByte(Address, Command, Data)
//Begin integration period
Data = 0x0B
WriteByte(Address, Command, Dat)
//Integrate for 50ms
Sleep (50)
//Wait for 50ms
//Stop integrating
Data = 0x03
WriteByte(Address, Cmmand, Data)
//Read data regisers see Basic Operation example)
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APPLICATION INFORMATION: SOFTWARE
Interrupts
The interrupt feature of the TSL256x device simplifies and improves system efficiency by eliminating the need
to poll the sensor for a light intensity value. Interrupt styles are determined by the INTR field in the Interrupt
Register. The interrupt feature may be disabled by writing a field value of 00h to the Interrupt Control Register
so that polling can be performed.
The versatility of the interrupt feature provides many options for interrupt configuration and usage. The primar
purpose of the interrupt function is to provide a meaningful change in light intensity. However, it also e used
as an end-of-conversion signal. The concept of a meaningful change can be defined by the user both in trms
of light intensity and time, or persistence, of that change in intensity. The TSL256x device implemets two
16-bit-wide interrupt threshold registers that allow the user to define a threshold above and below thurrent
light level. An interrupt will then be generated when the value of a conversion exceeds either of thee limits. For
simplicity of programming, the threshold comparison is accomplished only with Channel 0. Ths simplifies
calculation of thresholds that are based, for example, on a percent of the current light level. It is adequate to
use only one channel when calculating light intensity differences since, for a given lighsouce, the channel 0
and channel 1 values are linearly proportional to each other and thus both valuescae linearly with light
intensity.
To further control when an interrupt occurs, the TSL256devie provides an nterrupt persistence feature. This
feature allows the user to specify a number of cnversion cycles for which a light intensity exceeding either
interrupt threshold must persist before actually gating an interruThis can be used to prevent transient
changes in light intensity from generating an unanted interrupt. Wita value of 1, an interrupt occurs
immediately whenever either threshold is exceeded. With valueof , where N can range from 2 to 15, N
consecutive conversions must result in vaues outside the interrupt window for an interrupt to be generated. For
example, if N is equal to 10 and the integration time is 402 then an interrupt will not be generated unless
the light level persists for more than 4 seonds outside threshold.
Two different interrupt styles are aailable: Level and SMBus Alert. The difference between these two interrupt
styles is how they are cleardoth result in the inerrupt line going active low and remaining low until the
interrupt is cleared. A level stynterrupt is cleaby setting the CLEAR bit (bit 6) in the COMMAND register.
The SMBus Alert style interrupt is cleared by at Response as described in the Interrupt Control Register
section and SMBus specification.
To configure the interrupt as an end-of-conversion signal, the interrupt PERSIST field is set to 0. Either Level
or SMBus Alert style can be used. An interrupt will be generated upon completion of each conversion. The
interrupt threshold registers are gred. The following example illustrates the configuration of a level interrupt:
// Set up end−of−conversiointerrupt, Level style
Address = 0x39
Command = 0x86
Data = 0x10
//Slave addr also 0x29 or 0x49
//Address Interrupt Register
//Level style, every ADC cycle
WriteByte(AddessCommand, Data)
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APPLICATION INFORMATION: SOFTWARE
The following example pseudo code illustrates the configuration of an SMB Alert style interrupt when the light
intensity changes 20% from the current value, and persists for 3 conversion cycles:
// Read current light level
Address = 0x39
Command = 0xAC
//Slave addr also 0x29 or 0x49
//Set Command bit and Word bit
ReadWord (Address, Command, DataLow, DataHigh)
Channel0 = (256 * DataHigh) + DataLow
//Calculate upper and lower thresholds
T_Upper = Channel0 + (0.2 * Channel0)
T_Lower = Channel0 – (0.2 * Channel0)
//Write the lower threshold register
Command = 0xA2
//Addr lower threshold reg, set Word Bit
WriteWord (Address, Command, T_Lower.LoByte, T_Lower.HiByte)
//Write the upper threshold register
Command = 0xA4
//Addr upper threshold reg, set Word bit
WriteWord (Address, Command, T_Upper.LoByte, T_Upper.HiByte)
//Enable interrupt
Command = 0x86
Data = 0x23
//Address interrupt register
//SMBAlert style, PERSIST = 3
WriteByte(Address, Command, Data)
In order to generate an interrupt on demand during system test or debug, a test mode (INTR = 11) can be used.
The following example illustrates how to generate an interrupt on demand:
// Generate an interrupt
Address = 0x39
Command = 0x86
Data = 0x30
//Slave addr also 0x29 or 0x49
//Address Interrupt register
//Test interrupt
WriteByte(Address, Command, Data)
//Interrupt line should now be low
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APPLICATION INFORMATION: SOFTWARE
Calculating Lux
The TSL256x is intended for use in ambient light detection applications such as display backlight control, where
adjustments are made to display brightness or contrast based on the brightness of the ambient light, as
perceived by the human eye. Conventional silicon detectors respond strongly to infrared light, which the human
eye does not see. This can lead to significant error when the infrared content of the ambient light is high, such
as with incandescent lighting, due to the difference between the silicon detector response and the brightness
perceived by the human eye.
This problem is overcome in the TSL256x through the use of two photodiodes. One of the photodiodes
(channel 0) is sensitive to both visible and infrared light, while the second photodiode (channel 1) is sensitive
primarily to infrared light. An integrating ADC converts the photodiode currents to digital outputs. Channel 1
digital output is used to compensate for the effect of the infrared component of light on the channel 0 digital
output. The ADC digital outputs from the two channels are used in a formula to obtain a value that approximates
the human eye response in the commonly used Illuminance unit of Lux:
CS Package
1.4
For 0 < CH1/CH0 ꢀ 0.52
For 0.52 < CH1/CH0 ꢀ 0.65
For 0.65 < CH1/CH0 ꢀ 0.80
For 0.80 < CH1/CH0 ꢀ 1.30
For CH1/CH0 > 1.30
Lux = 0.0315 ꢁ CH0 − 0.0593 ꢁ CH0 ꢁ ((CH1/CH0)
Lux = 0.0229 ꢁ CH0 − 0.0291 ꢁ CH1
Lux = 0.0157 ꢁ CH0 − 0.0180 ꢁ CH1
Lux = 0.00338 ꢁ CH0 − 0.00260 ꢁ CH1
Lux = 0
)
T, FN, and CL Package
For 0 < CH1/CH0 ꢀ 0.50
For 0.50 < CH1/CH0 ꢀ 0.61
For 0.61 < CH1/CH0 ꢀ 0.80
For 0.80 < CH1/CH0 ꢀ 1.30
For CH1/CH0 > 1.30
1.4
Lux = 0.0304 ꢁ CH0 − 0.062 ꢁ CH0 ꢁ ((CH1/CH0)
Lux = 0.0224 ꢁ CH0 − 0.031 ꢁ CH1
Lux = 0.0128 ꢁ CH0 − 0.0153 ꢁ CH1
Lux = 0.00146 ꢁ CH0 − 0.00112 ꢁ CH1
Lux = 0
)
The formulas shown above were obtained by optical testing with fluorescent and incandescent light sources,
and apply only to open-air applications. Optical apertures (e.g. light pipes) will affect the incident light on the
device.
Simplified Lux Calculation
Below is the argument and return value including source code (shown on following page) for calculating lux.
The source code is intended for embedded and/or microcontroller applications. Two individual code sets are
provided, one for the T, FN, and CL packages, and one for the CS package. All floating point arithmetic
operations have been eliminated since embedded controllers and microcontrollers generally do not support
these types of operations. Since floating point has been removed, scaling must be performed prior to calculating
illuminance if the integration time is not 402 ms and/or if the gain is not 16ꢁ as denoted in the source code on
the following pages. This sequence scales first to mitigate rounding errors induced by decimal math.
extern unsigned int CalculateLux(unsigned int iGain, unsigned int tInt, unsigned int
ch0, unsigned int ch1, int iType)
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//****************************************************************************
//
// Copyright E 2004−2005 TAOS, Inc.
//
// THIS CODE AND INFORMATION IS PROVIDED ”AS IS” WITHOUT WARRANTY OF ANY
// KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR
// PURPOSE.
//
//
//
//
Module Name:
lux.cpp
//****************************************************************************
#define LUX_SCALE
14
// scale by 2^14
#define RATIO_SCALE 9
// scale ratio by 2^9
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// Integration time scaling factors
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#define CH_SCALE
10
// scale channel values by 2^10
#define CHSCALE_TINT0
#define CHSCALE_TINT1
0x7517 // 322/11 * 2^CH_SCALE
0x0fe7 // 322/81 * 2^CH_SCALE
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// T, FN, and CL Package coefficients
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// For Ch1/Ch0=0.00 to 0.50
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Lux/Ch0=0.0304−0.062*((Ch1/Ch0)^1.4)
piecewise approximation
For Ch1/Ch0=0.00 to 0.125:
Lux/Ch0=0.0304−0.0272*(Ch1/Ch0)
For Ch1/Ch0=0.125 to 0.250:
Lux/Ch0=0.0325−0.0440*(Ch1/Ch0)
For Ch1/Ch0=0.250 to 0.375:
Lux/Ch0=0.0351−0.0544*(Ch1/Ch0)
For Ch1/Ch0=0.375 to 0.50:
Lux/Ch0=0.0381−0.0624*(Ch1/Ch0)
// For Ch1/Ch0=0.50 to 0.61:
//
Lux/Ch0=0.0224−0.031*(Ch1/Ch0)
//
// For Ch1/Ch0=0.61 to 0.80:
//
Lux/Ch0=0.0128−0.0153*(Ch1/Ch0)
//
// For Ch1/Ch0=0.80 to 1.30:
//
Lux/Ch0=0.00146−0.00112*(Ch1/Ch0)
//
// For Ch1/Ch0>1.3:
//
Lux/Ch0=0
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#define K1T 0x0040
#define B1T 0x01f2
#define M1T 0x01be
// 0.125 * 2^RATIO_SCALE
// 0.0304 * 2^LUX_SCALE
// 0.0272 * 2^LUX_SCALE
#define K2T 0x0080
// 0.250 * 2^RATIO_SCALE
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#define B2T 0x0214
#define M2T 0x02d1
// 0.0325 * 2^LUX_SCALE
// 0.0440 * 2^LUX_SCALE
#define K3T 0x00c0
#define B3T 0x023f
#define M3T 0x037b
// 0.375 * 2^RATIO_SCALE
// 0.0351 * 2^LUX_SCALE
// 0.0544 * 2^LUX_SCALE
#define K4T 0x0100
#define B4T 0x0270
#define M4T 0x03fe
#define K5T 0x0138
#define B5T 0x016f
#define M5T 0x01fc
// 0.50 * 2^RATIO_SCALE
// 0.0381 * 2^LUX_SCALE
// 0.0624 * 2^LUX_SCALE
// 0.61 * 2^RATIO_SCALE
// 0.0224 * 2^LUX_SCALE
// 0.0310 * 2^LUX_SCALE
#define K6T 0x019a
#define B6T 0x00d2
#define M6T 0x00fb
// 0.80 * 2^RATIO_SCALE
// 0.0128 * 2^LUX_SCALE
// 0.0153 * 2^LUX_SCALE
#define K7T 0x029a
#define B7T 0x0018
#define M7T 0x0012
// 1.3 * 2^RATIO_SCALE
// 0.00146 * 2^LUX_SCALE
// 0.00112 * 2^LUX_SCALE
#define K8T 0x029a
#define B8T 0x0000
#define M8T 0x0000
// 1.3 * 2^RATIO_SCALE
// 0.000 * 2^LUX_SCALE
// 0.000 * 2^LUX_SCALE
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// CS package coefficients
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// For 0 <= Ch1/Ch0 <= 0.52
//
//
//
//
//
//
//
//
//
//
Lux/Ch0 = 0.0315−0.0593*((Ch1/Ch0)^1.4)
piecewise approximation
For 0 <= Ch1/Ch0 <= 0.13
Lux/Ch0 = 0.0315−0.0262*(Ch1/Ch0)
For 0.13 <= Ch1/Ch0 <= 0.26
Lux/Ch0 = 0.0337−0.0430*(Ch1/Ch0)
For 0.26 <= Ch1/Ch0 <= 0.39
Lux/Ch0 = 0.0363−0.0529*(Ch1/Ch0)
For 0.39 <= Ch1/Ch0 <= 0.52
Lux/Ch0 = 0.0392−0.0605*(Ch1/Ch0)
// For 0.52 < Ch1/Ch0 <= 0.65
// Lux/Ch0 = 0.0229−0.0291*(Ch1/Ch0)
// For 0.65 < Ch1/Ch0 <= 0.80
// Lux/Ch0 = 0.00157−0.00180*(Ch1/Ch0)
// For 0.80 < Ch1/Ch0 <= 1.30
// Lux/Ch0 = 0.00338−0.00260*(Ch1/Ch0)
// For Ch1/Ch0 > 1.30
// Lux = 0
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
#define K1C 0x0043 // 0.130 * 2^RATIO_SCALE
#define B1C 0x0204 // 0.0315 * 2^LUX_SCALE
#define M1C 0x01ad // 0.0262 * 2^LUX_SCALE
#define K2C 0x0085 // 0.260 * 2^RATIO_SCALE
#define B2C 0x0228 // 0.0337 * 2^LUX_SCALE
#define M2C 0x02c1 // 0.0430 * 2^LUX_SCALE
#define K3C 0x00c8 // 0.390 * 2^RATIO_SCALE
#define B3C 0x0253 // 0.0363 * 2^LUX_SCALE
#define M3C 0x0363 // 0.0529 * 2^LUX_SCALE
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#define K4C 0x010a // 0.520 * 2^RATIO_SCALE
#define B4C 0x0282 // 0.0392 * 2^LUX_SCALE
#define M4C 0x03df // 0.0605 * 2^LUX_SCALE
#define K5C 0x014d // 0.65 * 2^RATIO_SCALE
#define B5C 0x0177 // 0.0229 * 2^LUX_SCALE
#define M5C 0x01dd // 0.0291 * 2^LUX_SCALE
#define K6C 0x019a // 0.80 * 2^RATIO_SCALE
#define B6C 0x0101 // 0.0157 * 2^LUX_SCALE
#define M6C 0x0127 // 0.0180 * 2^LUX_SCALE
#define K7C 0x029a // 1.3 * 2^RATIO_SCALE
#define B7C 0x0037 // 0.00338 * 2^LUX_SCALE
#define M7C 0x002b // 0.00260 * 2^LUX_SCALE
#define K8C 0x029a // 1.3 * 2^RATIO_SCALE
#define B8C 0x0000 // 0.000 * 2^LUX_SCALE
#define M8C 0x0000 // 0.000 * 2^LUX_SCALE
// lux equation approximation without floating point calculations
//////////////////////////////////////////////////////////////////////////////
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Routine:
unsigned int CalculateLux(unsigned int ch0, unsigned int ch0, int iType)
Description: Calculate the approximate illuminance (lux) given the raw
channel values of the TSL2560. The equation if implemented
as a piece−wise linear approximation.
Arguments:
unsigned int iGain − gain, where 0:1X, 1:16X
unsigned int tInt − integration time, where 0:13.7mS, 1:100mS, 2:402mS,
3:Manual
unsigned int ch0 − raw channel value from channel 0 of TSL2560
unsigned int ch1 − raw channel value from channel 1 of TSL2560
unsigned int iType − package type (T or CS)
Return:
unsigned int − the approximate illuminance (lux)
//////////////////////////////////////////////////////////////////////////////
unsigned int CalculateLux(unsigned int iGain, unsigned int tInt, unsigned int ch0,
unsigned int ch1, int iType)
{
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// first, scale the channel values depending on the gain and integration time
// 16X, 402mS is nominal.
// scale if integration time is NOT 402 msec
unsigned long chScale;
unsigned long channel1;
unsigned long channel0;
switch (tInt)
{
case 0:
// 13.7 msec
chScale = CHSCALE_TINT0;
break;
case 1:
// 101 msec
chScale = CHSCALE_TINT1;
break;
default:
// assume no scaling
chScale = (1 << CH_SCALE);
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break;
}
// scale if gain is NOT 16X
if (!iGain) chScale = chScale << 4;
// scale 1X to 16X
// scale the channel values
channel0 = (ch0 * chScale) >> CH_SCALE;
channel1 = (ch1 * chScale) >> CH_SCALE;
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// find the ratio of the channel values (Channel1/Channel0)
// protect against divide by zero
unsigned long ratio1 = 0;
if (channel0 != 0) ratio1 = (channel1 << (RATIO_SCALE+1)) / channel0;
// round the ratio value
unsigned long ratio = (ratio1 + 1) >> 1;
// is ratio <= eachBreak ?
unsigned int b, m;
switch (iType)
{
case 0: // T, FN and CL package
if ((ratio >= 0) && (ratio <= K1T))
{b=B1T; m=M1T;}
else if (ratio <= K2T)
{b=B2T; m=M2T;}
else if (ratio <= K3T)
{b=B3T; m=M3T;}
else if (ratio <= K4T)
{b=B4T; m=M4T;}
else if (ratio <= K5T)
{b=B5T; m=M5T;}
else if (ratio <= K6T)
{b=B6T; m=M6T;}
else if (ratio <= K7T)
{b=B7T; m=M7T;}
else if (ratio > K8T)
{b=B8T; m=M8T;}
break;
case 1:// CS package
if ((ratio >= 0) && (ratio <= K1C))
{b=B1C; m=M1C;}
else if (ratio <= K2C)
{b=B2C; m=M2C;}
else if (ratio <= K3C)
{b=B3C; m=M3C;}
else if (ratio <= K4C)
{b=B4C; m=M4C;}
else if (ratio <= K5C)
{b=B5C; m=M5C;}
else if (ratio <= K6C)
{b=B6C; m=M6C;}
else if (ratio <= K7C)
{b=B7C; m=M7C;}
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else if (ratio > K8C)
{b=B8C; m=M8C;}
break;
}
unsigned long temp;
temp = ((channel0 * b) − (channel1 * m));
// do not allow negative lux value
if (temp < 0) temp = 0;
// round lsb (2^(LUX_SCALE−1))
temp += (1 << (LUX_SCALE−1));
// strip off fractional portion
unsigned long lux = temp >> LUX_SCALE;
return(lux);
}
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APPLICATION INFORMATION: HARDWARE
Power Supply Decoupling and Application Hardware Circuit
The power supply lines must be decoupled with a 0.1 μF capacitor placed as close to the device package as
possible (Figure 18). The bypass capacitor should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents caused by internal logic switching.
V
V
BUS
DD
0.1 ꢁ F
TSL2560/
TSL2561
R
P
R
P
R
PI
INT
SCL
SDA
Figure 18. Bus Pull-Up Resistors
Pull-up resistors (Rp) maintain the SDAH and SCLH lines at a high level when the bus is free and ensure the
signals are pulled up from a low to a high level within the required rise time. For a complete description of the
SMBus maximum and minimum Rp values, please review the SMBus Specification at
2
http://www.smbus.org/specs. For a complete description of I C maximum and minimum Rp values, please
2
review the I C Specification at http://www.semiconductors.philips.com.
A pull-up resistor (R ) is also required for the interrupt (INT), which functions as a wired-AND signal in a similar
PI
fashion to the SCL and SDA lines. A typical impedance value between 10 kΩ and 100 kΩ can be used. Please
note that while Figure 18 shows INT being pulled up to V , the interrupt can optionally be pulled up to V
.
DD
BUS
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APPLICATION INFORMATION: HARDWARE
PCB Pad Layout
Suggested PCB pad layout guidelines for the TMB-6 (T) surface mount package, chipscale (CS) package, Dual
Flat No-Lead (FN) surface mount package, and ChipLED−6 (CL) surface mount package are shown in
Figure 19, Figure 20, Figure 21, and Figure 22.
3.80
0.90
0.90
0.25
0.70
0.70
0.70
2.60
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 19. Suggested T Package PCB Layout
0.50
0.50
6 ꢁ ꢂ 0.21
0.50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 20. Suggested CS Package PCB Layout
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2.90
1.30
1.30
0.40
1.70
0.40
0.65
0.65
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 21. Suggested FN Package PCB Layout
1.30
0.43
0.40
0.65
0.40
0.70
0.70
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 22. Suggested CL Package PCB Layout
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MECHANICAL DATA
PACKAGE CS
TOP VIEW
Six-Lead Chipscale Device
PIN OUT
BOTTOM VIEW
1398
171
6
5
4
1
2
3
203
465
1250
END VIEW
400 ꢃ 50
700 ꢃ 55
6 ꢁ 100
TYP 30ꢀ
BOTTOM VIEW
SIDE VIEW
375 ꢃ 30
6 ꢁ ꢂ 210 ꢃ 30
500
1750
500
Pb
Lead Free
500
375 ꢃ 30
NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is 25 μm unless otherwise noted.
B. Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%).
C. The top of the photodiode active area is 410 μm below the top surface of the package.
D. The layer above the photodiode is glass and epoxy with an index of refraction of 1.53.
E. This drawing is subject to change without notice.
Figure 23. Package CS — Six-Lead Chipscale Packaging Configuration
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MECHANICAL DATA
PACKAGE TMB-6
TOP VIEW
Six-Lead Surface Mount Device
TOP VIEW
1.90
0.31
PIN 1
R 0.20
6 Pls
2.60
PIN 4
3.80
Photo-Active Area
0.88
END VIEW
1.35
0.50
BOTTOM VIEW
0.90
TYP
0.90 TYP
0.60
TYP
0.30
TYP
Pb
Lead Free
0.30
TYP
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.20 mm unless otherwise noted.
B. The photo-active area is 1398 μm by 203 μm.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is 0.5 μm minimum of soft gold plated over a 18 μm thick copper foil pattern with a 5 μm to 9 μm nickel barrier.
E. The underside of the package includes copper traces used to connect the pads during package substrate fabrication. Accordingly,
exposed traces and vias should not be placed under the footprint of the TMB package in a PCB layout.
F. This package contains no lead (Pb).
G. This drawing is subject to change without notice.
Figure 24. Package T — Six-Lead TMB Plastic Surface Mount Packaging Configuration
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MECHANICAL DATA
PACKAGE FN
TOP VIEW
Dual Flat No-Lead
PIN OUT
TOP VIEW
PIN 1
VDD 1
6 DATA
5 INT
2000 ꢃ 75
ADR 2
GND 3
4 CLK
2000
ꢃ 75
Photo-Active Area
END VIEW
SIDE VIEW
650 ꢃ 50
203 ꢃ 8
Seating Plane
650
300
ꢃ 50
BOTTOM VIEW
PIN 1
Pb
Lead Free
750 ꢃ 150
NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is 20 μm unless otherwise noted.
B. The photo-active area is 1398 μm by 203 μm.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 25. Package FN — Dual Flat No-Lead Packaging Configuration
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MECHANICAL DATA
PACKAGE CL-6
TOP VIEW
Six-Lead Surface Mount Device
PIN OUT
TOP VIEW
2.60
4
3
5
2.20
6
2
Pin 1
Photo-Active Area
Pin 1 Marker
SIDE VIEW
2.2
0.65
0.18
BOTTOM VIEW
Pin 1 Marker
0.65
0.40
Pin 1
0.70
0.35
6
5
Pb
Lead Free
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The photo-active area is 1398 μm by 203 μm.
C. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
D. Contact finish is 0.1 μm (minimum) to 1.0 μm (maximum) of soft gold plated over a 15 μm (minimum) to 30 μm (maximum) thick
copper foil pattern with a 3 μm (minimum) to 15 μm (maximum) nickel barrier.
E. This package contains no lead (Pb).
F. This drawing is subject to change without notice.
Figure 26. Package CL — Six-Lead ChipLED Plastic Surface Mount Packaging Configuration
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MECHANICAL DATA
TOP VIEW
2.00 ꢃ 0.05
1.75
ꢂ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢃ 0.05
ꢂ 0.60
ꢃ 0.05
B
A
A
DETAIL B
DETAIL A
5ꢀ Max
5ꢀ Max
0.250
1.35 ꢃ 0.05
ꢃ 0.02
1.85 ꢃ 0.05
0.97 ꢃ 0.05
A
o
B
o
K
o
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
D. Each reel is 178 millimeters in diameter and contains 3500 parts.
E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
G. This drawing is subject to change without notice.
Figure 27. TSL2560/TSL2561 Chipscale Carrier Tape
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MECHANICAL DATA
2.10
0.30 ꢃ 0.050
SIDE VIEW
TOP VIEW
1.75 ꢃ 0.100
8 Typ
ꢂ 1.50
4 ꢃ 0.100
B
END VIEW
2 ꢃ 0.100
12 ꢃ 0.100
5.50
ꢃ 0.100
ꢂ 1.50
R 0.20 TYP
B
A
A
DETAIL B
DETAIL A
2.90 ꢃ 0.100 A
o
3.09 MAX
R 0.20 TYP
R 0.20 TYP
4.29 MAX
4.10 ꢃ 0.100
B
o
1.80 K
o
NOTES: A. All linear dimensions are in millimeters.
B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
D. Each reel is 178 millimeters in diameter and contains 1000 parts.
E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
G. This drawing is subject to change without notice.
Figure 28. TSL2560/TSL2561 TMB Carrier Tape
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
MECHANICAL DATA
TOP VIEW
2.00 ꢃ 0.05
1.75
ꢂ 1.50
4.00
4.00
B
+ 0.30
8.00
− 0.10
3.50 ꢃ 0.05
ꢂ 1.00
ꢃ 0.25
B
A
A
DETAIL A
DETAIL B
5ꢀ Max
5ꢀ Max
0.254
2.18 ꢃ 0.05
2.18 ꢃ 0.05
ꢃ 0.02
0.83 ꢃ 0.05
B
o
A
o
K
o
NOTES: H. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
I. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
J. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
K. Each reel is 178 millimeters in diameter and contains 3500 parts.
L. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
M. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
N. This drawing is subject to change without notice.
Figure 29. TSL2560/TSL2561 FN Carrier Tape
Copyright E 2009, TAOS Inc.
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
MECHANICAL DATA
TOP VIEW
2.00 ꢃ 0.05
1.75
ꢂ 1.50
+ 0.10
4.00
4.00
B
8.0 ꢃ 0.2
3.50 ꢃ 0.05
ꢂ 1.00
B
A
A
DETAIL B
DETAIL A
5ꢀ Max
5ꢀ Max
0.20
2.4
ꢃ
0
.
0
5
2.9
0.7
K
o
A
o
B
o
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted.
B. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
C. Symbols on drawing A , B , and K are defined in ANSI EIA Standard 481−B 2001.
o
o
o
D. Each reel is 178 millimeters in diameter and contains 2500 parts.
E. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
F. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
G. This drawing is subject to change without notice.
Figure 30. TSL2560/TSL2561 CL Carrier Tape
Copyright E 2009, TAOS Inc.
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www.taosinc.com
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
MANUFACTURING INFORMATION
The CS, T, FN, and CL packages have been tested and have demonstrated an ability to be reflow soldered to
a PCB substrate. The process, equipment, and materials used in these test are detailed below.
The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
Table 13. TSL2560/61 Solder Reflow Profile
PARAMETER
Average temperature gradient in preheating
Soak time
REFERENCE
TSL2560/61
2.5°C/sec
t
2 to 3 minutes
Max 60 sec
soak
Time above 217°C
t
1
Time above 230°C
t
Max 50 sec
2
Time above T
−10°C
t
Max 10 sec
peak
3
Peak temperature in reflow
T
260° C (−0°C/+5°C)
Max −5°C/sec
peak
Temperature gradient in cooling
Not to scale — for reference only
T
peak
T
3
T
T
2
1
Time (sec)
t
t
t
3
2
1
t
soak
Figure 31. TSL2560/TSL2561 Solder Reflow Profile Graph
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
MANUFACTURING INFORMATION
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the
package molding compound contains the smallest amount of absorbed moisture possible, each device is
dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica
gel to protect them from ambient moisture during shipping, handling, and storage before use.
The CS package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under
the following conditions:
Temperature Range
Relative Humidity
Floor Life
5°C to 50°C
60% maximum
1 year out of bag at ambient < 30°C / 60% RH
Rebaking will be required if the aluminized envelope has been open for more than 1 year. If rebaking is required,
it should be done at 90°C for 3 hours.
The T, FN, and CL packages have been assigned a moisture sensitivity level of MSL 3 and the devices should
be stored under the following conditions:
Temperature Range
Relative Humidity
Total Time
5°C to 50°C
60% maximum
6 months from the date code on the aluminized envelope — if unopened
168 hours or fewer
Opened Time
Rebaking will be required if the devices have been stored unopened for more than 6 months or if the aluminized
envelope has been open for more than 168 hours. If rebaking is required, it should be done at 90°C for 4 hours.
Copyright E 2009, TAOS Inc.
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TSL2560, TSL2561
LIGHT-TO-DIGITAL CONVERTER
TAOS059Q − NOVEMBER 2009
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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