MU82 [AMSCO]

8-input to 1-output digital multiplexer with 2x drive strength; 8输入1输出的数字多路复用器与2倍的驱动力
MU82
型号: MU82
厂家: AMS(艾迈斯)    AMS(艾迈斯)
描述:

8-input to 1-output digital multiplexer with 2x drive strength
8输入1输出的数字多路复用器与2倍的驱动力

复用器 驱动
文件: 总2页 (文件大小:17K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
0.35 µm CMOS  
MU82  
MU82 is an 8-input to 1-output digital multiplexer with 2x drive strength.  
Truth Table  
Capacitance  
Pin  
Cap [pF]  
I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2  
Q
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
X
0
X
X
0
X
X
X
0
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
I0  
I1  
0.008  
0.008  
0.008  
0.008  
0.008  
0.008  
0.009  
0.008  
0.053  
0.027  
0.018  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
I2  
X
X
X
X
X
X
X
X
X
X
1
I3  
X
X
X
X
X
X
X
X
1
I4  
X
X
X
X
X
X
1
I5  
X
X
X
X
1
I6  
X
X
1
I7  
1
S0  
S1  
S2  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Area  
Power  
0.959 mils2  
1.733 µW/MHz  
619 µm2  
Delay [ns] = tpd.. = f(SL, L)  
Output Slope [ns] = op_sl.. = f(SL, L)  
with SL = Input Slope [ns] ; L = Output Load [pF]  
with L = Output Load [pF]  
AC Characteristics: Tj = 25°C VDD = 3.3V Typical Process  
April 2000  
Page 1 of 2  
Rev. N/C  
0.35 µm CMOS  
MU82  
AC Characteristics  
Rise  
Fall  
Slope [ns]  
Load [pF]  
0.1  
2
0.1  
2
0.03  
0.3  
0.03  
0.3  
0.03  
0.3  
0.03  
0.3  
Delay I0 => Q  
0.85  
0.86  
0.88  
0.87  
0.87  
0.87  
0.89  
0.88  
0.82  
1.18  
0.8  
1.35  
1.35  
1.37  
1.37  
1.36  
1.36  
1.38  
1.37  
1.31  
1.68  
1.3  
1.02  
1.01  
1.04  
1.04  
1.03  
1.04  
1.06  
1.05  
1.03  
1.43  
1.06  
0.77  
0.59  
0.65  
1.51  
1.52  
1.53  
1.53  
1.53  
1.53  
1.55  
1.55  
1.52  
1.93  
1.56  
1.27  
1.09  
1.14  
0.93  
0.93  
0.95  
0.95  
0.95  
0.96  
0.97  
0.97  
1.23  
0.88  
0.64  
0.85  
0.55  
0.38  
1.48  
1.48  
1.5  
1.06  
1.06  
1.08  
1.09  
1.08  
1.08  
1.1  
1.61  
1.61  
1.64  
1.63  
1.63  
1.64  
1.65  
1.65  
2.09  
1.63  
1.4  
Delay I1 => Q  
Delay I2 => Q  
Delay I3 => Q  
1.5  
Delay I4 => Q  
1.5  
Delay I5 => Q  
1.51  
1.52  
1.52  
1.78  
1.43  
1.19  
1.41  
1.1  
Delay I6 => Q  
Delay I7 => Q  
1.1  
Delay S001 => Q  
Delay S010 => Q  
Delay S101 => Q  
Delay S110 => Q  
Delay S201 => Q  
Delay S210 => Q  
1.54  
1.08  
0.85  
1.08  
0.75  
0.6  
0.57  
0.33  
0.46  
1.07  
0.83  
0.95  
1.63  
1.3  
0.94  
1.16  
Slew I0 => Q  
0.35  
0.34  
0.35  
0.34  
0.35  
0.35  
0.36  
0.35  
0.35  
0.35  
0.35  
0.35  
0.34  
0.34  
1.86  
1.85  
1.86  
1.86  
1.86  
1.85  
1.86  
1.86  
1.86  
1.86  
1.86  
1.86  
1.85  
1.86  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
0.36  
0.35  
0.35  
0.35  
0.35  
0.39  
0.34  
1.86  
1.86  
1.86  
1.85  
1.86  
1.86  
1.85  
1.85  
1.86  
1.86  
1.86  
1.85  
1.87  
1.85  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.31  
0.31  
0.3  
1.34  
1.34  
1.35  
1.33  
1.35  
1.33  
1.33  
1.35  
1.35  
1.34  
1.34  
1.35  
1.34  
1.34  
0.32  
0.31  
0.32  
0.32  
0.33  
0.32  
0.32  
0.32  
0.32  
0.32  
0.32  
0.33  
0.31  
0.36  
1.35  
1.35  
1.33  
1.34  
1.35  
1.35  
1.34  
1.35  
1.34  
1.34  
1.34  
1.34  
1.34  
1.37  
Slew I1 => Q  
Slew I2 => Q  
Slew I3 => Q  
Slew I4 => Q  
Slew I5 => Q  
Slew I6 => Q  
Slew I7 => Q  
Slew S001 => Q  
Slew S010 => Q  
Slew S101 => Q  
Slew S110 => Q  
Slew S201 => Q  
Slew S210 => Q  
April 2000  
Page 2 of 2  
Rev. N/C  

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