LP62S2048X-10LT [AMICC]
256K X 8 BIT LOW VOLTAGE CMOS SRAM; 256K ×8位的低电压CMOS SRAM
| 型号： | LP62S2048X-10LT |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总17页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S2048-T Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
nPower supply range: 2.7V to 3.3V
nAccess times: 70/100 ns (max.)
nCurrent:
nAll inputs and outputs are directly TTL-compatible
nCommon I/O using three-state output
nOutput enable and two chip enable inputs for easy
application
Low power version:
Operating: 30mA (max.)
nData retention voltage: 2V (min.)
Standby: 50mA (max.)
nAvailable in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
and 36-pin CSP packages
Very low power version: Operating: 30mA (max.)
Standby: 10mA (max.)
nFull static operation, no clock or refreshing required
General Description
The LP62S2048-T is a low operating current 2,097,152-
bit static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
range: 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n SOP
n TSOP/(TSSOP)
n CSP (Chip Size Package)
36-pin Top View
1
VCC
A15
CE2
WE
A13
A8
32
31
30
A17
A16
A14
16
1
2
3
4
A12
A7
A6
A5
A4
A3
A2
29
28
27
26
1
2
3
4
5
6
5
6
A8
A0
A1
CE2
A3
A6
A
B
I/O
I/O
5
A2
WE
NC
A4
A5
A7
I/O1
A9
7
8
A11
25
24
23
22
C
D
E
F
6
I/O2
OE
9
GND
VCC
VCC
GND
A10
10
11
12
13
14
15
16
CE1
I/O8
A1
A0
21
20
19
18
17
I/O
I/O
7
NC
CE1
A11
A17
A16
A12
I/O
3
4
I/O1
I/O2
I/O7
I/O6
I/O5
I/O4
I/O
G
H
8
OE
A15
A13
A9
A10
A14
32
17
I/O3
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
CE2 A15 VCC A17 A16
22 23 24 25 26
I/O
11
A14
27
12
A12
28
13
A7
29
14
A6
30
15
A5
31
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13 WE
Pin No.
20
A0
21
I/O
Pin
Name
3
I/O8
A3
1
I/O GND I/O I/O
2
4
5
I/O6
I/O7
CE1 A10
OE
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
LP62S2048-T Series
Block Diagram
A0
VCC
GND
ROW
1024 X 2048
A15
A16
A17
DECODER
MEMORY ARRAY
I/O1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O8
CE2
CE1
OE
CONTROL
CIRCUIT
WE
Pin Description - SOP
Pin Descriptions - TSOP/TSSOP
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1 - 4, 7,
9 - 20, 31
1 - 12, 23,
25 - 28, 31
A0 - A17
Address Inputs
Write Enable
A0 - A17
Address Inputs
5
WE
CE2
VCC
NC
13 - 15,
17 - 21
I/O1 - I/O8
GND
Data Input/Outputs
6
8
9
Chip Enable
16
22
Ground
Power Supply
No Connection
Chip Enable
CE1
24
29
Output Enable
Write Enable
21 - 23,
25 - 29
OE
I/O1 - I/O8
Data Input/Outputs
WE
CE2
VCC
24
30
GND
CE1
OE
Ground
30
32
Chip Enable
Chip Enable
Power Supply
32
Output Enable
(August, 2001, Version 1.0)
2
AMIC Technology, Inc.
LP62S2048-T Series
Pin Description - CSP
Symbol
Description
Symbol
NC
Description
No Connection
A0 - A17
WE
Address Inputs
Write Enable
I/O1 - I/O8
Data Input/Output
Power Supply
Ground
Output Enable
Chip Enable
Chip Enable
VCC
GND
--
OE
CE1
CE2
--
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
Typ.
Max.
Unit
V
2.7
0
3.0
3.3
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Output Load
2.0
-0.3
-
VCC + 0.3
V
VIL
-
+0.6
30
1
V
CL
-
pF
-
TTL
Output Load
-
-
(August, 2001, Version 1.0)
3
AMIC Technology, Inc.
LP62S2048-T Series
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . -0.5V to + 4.6V
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -25°C to + 85°C
Storage Temperature, Tstg . . . . .. . . . . -55°C to + 125°C
Temperature Under Bias, Tbias . . . . . . -10°C to + 85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V)
LP62S2048-70LT/10LT
LP62S2048-70LLT/10LLT
Symbol
Parameter
Unit
Conditions
Min.
Max.
Min.
Max.
Input Leakage
Current
-
1
-
1
VIN = GND to VCC
çILIú
mA
mA
CE1 = VIH or CE2 = VIL
Output Leakage
Current
-
-
1
3
-
-
1
3
çILOú
ICC
or OE = VIH or WE = VIL
VI/O = GND to VCC
Active Power
Supply Current
CE1 = VIL, CE2 = VIH
II/O = 0mA
mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC1
ICC2
-
-
30
5
-
-
30
5
mA
mA
Dynamic
Operating
Current
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA
(August, 2001, Version 1.0)
4
AMIC Technology, Inc.
LP62S2048-T Series
DC Electrical Characteristics (continued)
LP62S2048-70LT/10LT
LP62S2048-70LLT/10LLT
Symbol
Parameter
Unit
Conditions
Min.
Max.
Min.
Max.
ISB
-
0.5
-
0.5
mA
CE1 = VIH or CE2 =VIL
CE1 ³ VCC - 0.2V
VIN ³ 0V
ISB1
ISB2
-
-
50
50
-
-
10
10
mA
Standby Power
Supply Current
CE2 £ 0.2V
VIN ³ 0V
mA
V
Output Low
Voltage
VOL
VOH
-
0.4
-
-
0.4
-
IOL = 2.1mA
IOH = -1.0mA
Output High
Voltage
2.2
2.2
V
Truth Table
Mode
CE2
I/O Operation
Supply Current
CE1
H
OE
X
WE
X
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
Standby
X
X
X
ISB, ISB2
Output Disable
Read
L
H
H
H
H
L
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
L
H
Write
L
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(August, 2001, Version 1.0)
5
AMIC Technology, Inc.
LP62S2048-T Series
AC Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V)
LP62S2048-70LT/LLT
LP62S2048-10LT/LLT
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
tAA
Read Cycle Time
70
-
-
100
-
ns
ns
ns
Address Access Time
70
70
-
-
100
100
tACE1
-
CE1
CE2
Chip Enable Access Time
tACE2
tOE
-
-
70
35
-
-
-
100
50
-
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
10
10
CE1
CE2
tCLZ2
tOLZ
10
5
-
-
10
5
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
0
25
0
35
CE1
CE2
tCHZ2
tOHZ
tOH
0
0
25
25
-
0
0
35
35
-
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
10
10
Write Cycle
tWC
Write Cycle Time
70
60
0
-
-
100
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
60
50
0
-
80
60
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
35
-
30
0
40
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2001, Version 1.0)
6
AMIC Technology, Inc.
LP62S2048-T Series
Timing Waveforms
Read Cycle 1 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2 (1, 3, 4, 6)
CE1
tACE1
5
tCLZ1
5
tCHZ1
DOUT
Read Cycle 3 (1, 4, 7, 8)
CE2
tACE2
5
tCHZ2
5
tCLZ2
DOUT
(August, 2001, Version 1.0)
7
AMIC Technology, Inc.
LP62S2048-T Series
Timing Waveforms (continued)
Read Cycle 4 (1)
tRC
Address
tAA
OE
tOE
tOH
5
tOLZ
CE1
tACE1
5
5
tCHZ1
tCLZ1
CE2
5
tACE2
tOHZ
5
tCHZ2
5
tCLZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
(August, 2001, Version 1.0)
8
AMIC Technology, Inc.
LP62S2048-T Series
Timing Waveforms (continued)
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
(4)
(4)
CE1
CE2
1
2
tAS
tWP
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
(August, 2001, Version 1.0)
9
AMIC Technology, Inc.
LP62S2048-T Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
tAS
5
tCW
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2001, Version 1.0)
10
AMIC Technology, Inc.
LP62S2048-T Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
VDR1
2.0
3.3
V
CE1 ³ VCC - 0.2V
CE2 £ 0.2V,
VDR2
VCC for Data Retention
2.0
3.3
V
VCC = 2.0V,
CE1 ³ VCC - 0.2V,
VIN ³ 0V
ICCDR1
L-Version
-
-
20*
5**
mA
LL-Version
Data Retention Current
L-Version
-
20*
VCC = 2.0V,
CE2 £ 0.2V,
VIN ³ 0V
ICCDR2
mA
LL-Version
-
0
5**
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
-
-
-
ns
ns
tRC
5
See Retention Waveform
tVR
VCC Rising Time from Data Retention Voltage
to Operating Voltage
ms
** LP62S2048-70LLT/10LLT
LP62S2048-70LT/10LT
ICCDR: max. 1mA at TA = 0°C to + 40°C
ICCDR: max. 5mA at TA = 0°C to + 40°C
*
(August, 2001, Version 1.0)
11
AMIC Technology, Inc.
LP62S2048-T Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
2.7V
2.7V
tCDR
tR
VDR
³ 2V
tVR
VIH
VIH
CE1
³ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
2.7V
tCDR
tR
VDR
³ 2V
tVR
VIL
VIL
CE2 £ 0.2V
(August, 2001, Version 1.0)
12
AMIC Technology, Inc.
LP62S2048-T Series
Ordering Information
Part No.
Access Time (ns)
Operating Current
Max. (mA)
Standby Current
Package
Max. (mA)
LP62S2048M-70LT
LP62S2048M-70LLT
LP62S2048V-70LT
LP62S2048V-70LLT
LP62S2048X-70LT
LP62S2048X-70LLT
LP62S2048U-70LT
LP62S2048U-70LLT
LP62S2048M-10LT
LP62S2048M-10LLT
LP62S2048V-10LT
LP62S2048V-10LLT
LP62S2048X-10LT
LP62S2048X-10LLT
LP62S2048U-10LT
LP62S2048U-10LLT
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
50
32L SOP
10
32L SOP
50
32L TSOP
32L TSOP
32L TSSOP
32L TSSOP
36L CSP
10
70
50
10
50
10
36L CSP
50
32L SOP
10
32L SOP
50
32L TSOP
32L TSOP
32L TSSOP
32L TSSOP
36L CSP
10
100
50
10
50
10
36L CSP
(August, 2001, Version 1.0)
13
AMIC Technology, Inc.
LP62S2048-T Series
Package Information
SOP (W.B.) 32L Outline Dimensions
unit: inches/mm
32
17
e1
L
16
1
b
Detail F
e1
D
LE
e
s
y
See Detail F
Seating Plane
Symbol
Dimensions in inches
Dimensions in mm
3.00 Max.
0.10 Min.
2.69±0.13
0.41 +0.10
-0.05
A
A1
A2
b
0.118 Max.
0.004 Min.
0.106±0.005
0.016 +0.004
-0.002
c
0.008 +0.004
-0.002
0.20 +0.10
-0.05
D
E
e
0.805 Typ. (0.820 Max.)
0.445±0.010
0.050 ±0.006
0.525 NOM.
0.556±0.010
0.031±0.008
0.055±0.008
0.044 Max.
20.45 Typ. (20.83 Max.)
11.30±0.25
1.27±0.15
e1
13.34 NOM.
14.12±0.25
0.79±0.20
HE
L
LE
S
1.40±0.20
1.12 Max.
y
0.004 Max.
0.10 Max.
q
0° ~ 10°
0° ~ 10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0)
14
AMIC Technology, Inc.
LP62S2048-T Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
q
L
LE
HD
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
q
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0)
15
AMIC Technology, Inc.
LP62S2048-T Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
q
L
LE
D1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
Dimensions in mm
1.25 Max.
A
A1
A2
b
0.049 Max.
0.002 Min.
0.05 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
0.528±0.008
0.465±0.004
0.02±0.008
0.0266 Min.
0.0109 TYP.
0.004 Max.
0° ~ 6°
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
c
E
e
D
D1
L
LE
S
y
q
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2001, Version 1.0)
16
AMIC Technology, Inc.
LP62S2048-T Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
0.10
C
S
0.25 C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS F 0.25mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS F 0.25mm (NSMD)
(August, 2001, Version 1.0)
17
AMIC Technology, Inc.
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