LP62S4096EU-55LLT [AMICC]
512K X 8 BIT LOW VOLTAGE CMOS SRAM; 512K ×8位的低电压CMOS SRAM
| 型号： | LP62S4096EU-55LLT |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总14页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
2.0
Change VCCmax from 3.3V to 3.6V
January 25, 2002
Add product family and 55ns specification
(January, 2002, Version 2.0)
AMIC Technology, Inc.
LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
n Power supply range: 2.7V to 3.6V
n Access times: 55ns / 70ns (max.)
n Current:
The LP62S4096E-T is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words
by 8 bits and operates on a low power supply range: 2.7V to
3.3V. It is built using AMIC's high performance CMOS
Very low power version: Operating: 30mA (max.)
process.
Standby:
10mA (max.)
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP/TSSOP 36-ball CSP package
Data retention is guaranteed at a power supply voltage as low
as 2V.
n CE2 pin for CSP package only
Product Family
Power Dissipation
Package
Operating
Temperature
VCC
Range
Data Retention
(ICCDR, Typ.)
Standby
Operating
(ICC2, Typ.)
Product Family
Speed
Type
(ISB1, Typ.)
32L TSOP
32L TSSOP
36B CSP
LP62S4096E-T
2.7V~3.6V 55ns / 70ns
5mA
-25°C ~ +85°C
0.08mA
0.3mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
n TSOP/(TSSOP)
n CSP (Chip Size Package)
36-pin Top View
16
1
1
2
3
4
5
6
A8
A0
A1
CE2
A3
A6
A
B
I/O5
A2
WE
NC
A4
A5
A7
I/O1
C
D
E
F
I/O6
I/O2
GND
VCC
VCC
GND
I/O7
A18
CE1
A11
A17
A16
A12
I/O
3
4
I/O
G
H
I/O8
OE
A15
A13
A9
A10
A14
17
32
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
A14
27
12
A12
28
13
A7
14
A6
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
A17
22
A15
VCC
24
A18
25
Pin No.
23
29
30
31
Pin
Name
I/O3
A3
A0
I/O
1
I/O2
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
(January, 2002, Version 2.0)
AMIC Technology, Inc.
LP62S4096E-T Series
Block Diagram
A0
VCC
GND
ROW
1024 X 4096
A16
A17
A18
DECODER
MEMORY ARRAY
I/O1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O8
CE1
CE2
OE
CONTROL
CIRCUIT
WE
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Pin Description
Symbol
Description
Symbol
VCC
Parameter
Supply Voltage
Ground
Min.
2.7
0
Typ.
3.0
0
Max.
3.6
0
Unit
V
A0 - A18
I/O1 - I/O8
GND
Address Inputs
GND
V
Data Input/Outputs
Ground
Input High
Voltage
VCC
+ 0.3
VIH
2.2
-
V
Chip Enable
CE1, CE2
OE
VIL
CL
Input Low Voltage
Output Load
-0.3
0
-
+0.6
30
1
V
pF
-
Output Enable
Write Enable
Power Supply
-
-
TTL
Output Load
-
WE
VCC
(January, 2002, Version 2.0)
3
AMIC Technology, Inc.
LP62S4096E-T Series
Absolute Maximum Ratings*
*Comments
VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -25°C to + 85°C
Storage Temperature, Tstg --------------- -55°C to + 125°C
Temperature Under Bias, Tbias ----------- -10°C to + 85°C
Power Dissipation, PT --------------------------------------- 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S4096E-55LLT / 70LLT
Symbol
Parameter
Unit
Conditions
Min.
Typ.
Max.
Input Leakage Current
Output Leakage Current
-
-
1
VIN = GND to VCC
çILIú
mA
mA
CE1= VIH , CE2= VIL or
-
-
1
çILOú
OE = VIH WE =VIL
VI/O = GND to VCC
ICC
Active Power Supply Current
Dynamic Operating Current
-
-
-
5
mA
mA
CE1= VIL, CE2= VIH II/O = 0mA
Min. Cycle, Duty = 100%,
ICC1
20
30
CE1= VIL CE2= VIH, II/O = 0mA
CE1= VIL, CE2= VIH, VIH = VCC
VIL = 0V, f = 1MHZ
II/O = 0mA
ICC2
ISB
Dynamic Operating Current
Standby Power
-
-
5
-
15
1
mA
mA
VCC £ 3.3V
CE1= VIH, CE2= VIL
VCC £ 3.3V
ISB1
Supply Current
-
0.3
10
mA
CE1³ VCC - 0.2V, or CE2 £ 0.2V
VIN £ 0.2V
VOL
VOH
Output Low Voltage
Output High Voltage
-
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.2
(January, 2002, Version 2.0)
4
AMIC Technology, Inc.
LP62S4096E-T Series
Truth Table
Mode
I/O Operation
Supply Current
CE1
CE2
OE
X
WE
X
Standby
Standby
H
X
L
L
L
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
X
X
ISB, ISB1
Output Disable
H
H
H
H
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Read
Write
L
H
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
Conditions
VIN = 0V
Input Capacitance
6
8
pF
pF
CI/O*
Input/Output Capacitance
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V)
LP62S4096E-55LLT
LP62S4096E-70LLT
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
55
55
30
-
70
70
35
-
tACE1, tACE2
tOE
Chip Enable Access Time
-
-
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
tCLZ1, tCLZ2
tOLZ
10
5
0
0
5
10
5
-
-
tCHZ1, tCHZ2
tOHZ
20
20
-
0
25
25
-
0
tOH
5
(January, 2002, Version 2.0)
5
AMIC Technology, Inc.
LP62S4096E-T Series
AC Characteristics (continued)
LP62S4096E-55LLT
LP62S4096E-70LLT
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Write Cycle
tWC
Write Cycle Time
55
50
0
-
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW1
tAS
Chip Enable to End of Write
Address Setup Time
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1)
tRC
Address
tAA
OE
tOE
tOH
CE1
5
tOLZ
CE2
5
tOHZ
tACE1 , tACE2
tCLZ1 , tCLZ2
tCHZ1 , tCHZ2
DOUT
(January, 2002, Version 2.0)
6
AMIC Technology, Inc.
LP62S4096E-T Series
Timing Waveforms (continued)
Read Cycle 2 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 3 (1, 3, 4)
CS1
CS2
tACS1 , tACS2
tCLZ1 , tCLZ2
tCHZ1 , tCHZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE1 = VIL or CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
7
AMIC Technology, Inc.
LP62S4096E-T Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
CE1
tAW
3
tWR
tcw1 ,tcw2
(4)
CE2
1
2
tAS
tWP
WE
tDW
tDH
DIN
7
tWHZ
7
tOW
DOUT
(January, 2002, Version 2.0)
8
AMIC Technology, Inc.
LP62S4096E-T Series
Write Cycle 2(6)
(Chip Enable Controlled)
tWC
Address
tAW
1
3
tCW1 , tCW2
t
AS
tWR
CE1
(4)
CE2
2
t
WP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the
Write cycle.
4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE
transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
9
AMIC Technology, Inc.
LP62S4096E-T Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
CL
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ,
tOHZ, tOL, tCHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol
Parameter
VCC for Data Retention
Min.
Typ.
Max.
Unit
Conditions
VDR
2.0
-
3.6
V
CE1³ VCC - 0.2V, or
CE2 £ 0.2V
VCC = 2.0V,
CE1³ VCC - 0.2V, or
CE2 £ 0.2V
ICCDR
Data Retention Current
LL-Version
-
0.08
3*
mA
VIN £ 0V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention Voltage to
Operating Voltage
ms
*
LP62S4096E-55LLT / 70LLT
ICCDR: max. 1mA at TA = 0°C to + 40°C
(January, 2002, Version 2.0)
10
AMIC Technology, Inc.
LP62S4096E-T Series
Low VCC Data Retention Waveform (1) (
Controlled)
CE1
DATA RETENTION MODE
VCC
2.7V
2.7V
tCDR
tR
V
DR ³ 2V
tVR
CE1
V
IH
V
IH
CE1³ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
2.7V
tCDR
tR
VDR
³ 2V
tVR
VIL
VIL
CE2£ 0.2V
Ordering Information
Operating Current
Max.(mA)
Standby Current
Max.(uA)
Part No.
Access Time(ns)
Package
32L TSOP
32L TSSOP
36L CSP
LP62S4096EV-55LLT
LP62S4096EX-55LLT
LP62S4096EU-55LLT
LP62S4096EV-70LLT
LP62S4096EX-70LLT
LP62S4096EU-70LLT
55
55
55
70
70
70
30
30
30
30
30
30
10
10
10
10
10
10
32L TSOP
32L TSSOP
36L CSP
(January, 2002, Version 2.0)
11
AMIC Technology, Inc.
LP62S4096E-T Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
q
L
LE
HD
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
q
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(January, 2002, Version 2.0)
12
AMIC Technology, Inc.
LP62S4096E-T Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
q
L
LE
D1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
Dimensions in mm
1.25 Max.
A
A1
A2
b
0.049 Max.
0.002 Min.
0.05 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
0.528±0.008
0.465±0.004
0.02±0.008
0.0266 Min.
0.0109 TYP.
0.004 Max.
0° ~ 6°
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
c
E
e
D
D1
L
LE
S
y
q
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(January, 2002, Version 2.0)
13
AMIC Technology, Inc.
LP62S4096E-T Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
0.10
C
S
0.25 C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
4. BALL PAD OPENING OF SUBSTRATE IS F 0.25mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS F 0.25mm (NSMD)
(January, 2002, Version 2.0)
14
AMIC Technology, Inc.
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