A64S06161G-70I [AMICC]
SRAM;
| 型号： | A64S06161G-70I |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | SRAM 静态存储器 |
| 文件： | 总17页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A64S06161
Preliminary
1M X 16 Bit Low Voltage Super RAM
Features
● Memory cell : Dynamic memory( DRAM )
● Refresh: Completely free
1
2
3
A0
4
5
6
● Power Down: Control by CS2( No Data Retention )
● Byte Control : Capable of single byte operation
● Power Consumption: 70μA( Standby Current )
● Operating Temperature Range: -30’C~+85’C
● Composition:1,048,576Word X 16 Bit
● Supply Power Voltage:2.70V to 3.30V
● Access Time: 70nS
LB#
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
OE#
UB#
DQ10
DQ11
DQ12
DQ13
A19
A8
A1
A2
CS2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A
B
C
D
E
A3
A4
CE1#
DQ1
DQ3
DQ4
DQ5
WE#
A11
A5
A6
A7
● Access Time ( Page Access Read ): 30nS
● I/O Terminal :Input / Output Common 3-state output
A17
NC
Pin Description
A16
A15
A13
A10
Pin Name
CS1#
CS2
Description
Chip select 1 ( Low Active )
Chip select 2 ( High Active )
Write enable ( Low Active )
Output enable ( Low Active )
Address Input ( A0 to A1 : Page Address)
Lower Byte Input / Output
Upper Byte Input / Output
Lower Byte Control ( Low Active )
Upper Byte Control ( Low Active )
Power Supply
A14
A12
A9
F
WE#
G
H
OE#
A0 to A19
IO0-7
IO8-15
LB#
UB#
VCC
VSS
Ground ( 0V)
Description
A64S06161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need
not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you
can operate as same as the Asynchronous SRAM.
A64S06161 is a 1,048,576 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with
marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications.
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A64S06161
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
12
4096
Memory Cell
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
256X16
8
256
Column
Decoder
Column Gate
ATD
16
Control
Refresh
Control
CS1#,CS2
Control
CS1#
CS2
Input / Output Buffer
WE#
OE#
LB#
WE#,OE#
LB#,UB#
Control
UB#
I / O0 ．．．．．．．．．．．．．．
I / O15
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A64S06161
Functions
Truth Table
A0-19 CS1#
CS2
H
WE#
H
OE#
L
LB#
L
UB#
L
I/O0~7
Data-Out
Data-Out
High-Z
High-Z
High-Z
Data-In
Data-In
High-Z
High-Z
High-Z
I/O8~15
Data-Out
High-Z
Mode
Read
V
V
V
V
V
V
V
V
X
X
L
L
L
L
L
L
L
L
H
X
H
H
L
L
H
L
Read
H
H
L
H
H
X
Data-Out
High-Z
Read
H
H
X
H
X
Output Disable
Output Disable
Write
H
H
H
H
H
H
X
High-Z
H
L
L
L
Data-In
High-Z
H
L
L
H
L
Write
H
L
H
X
Data-In
High-Z
Write
H
X
X
Standby
Power Down*¹
L
X
X
X
X
High-Z
V : Valid Address. X : High or Low .*1 No Data Retention
Read Operation
It is possible to control data width by LB# and UB# pins.
(1)Reading data from lower byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and LB #=L.
(2)Reading data from upper byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and UB #=L.
(3)Reading date from both bytes
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H , LB #=L and UB #=L.
(4)Page access read
Date can be read by changing A0-A1 when A2-A19 is set while holding CS1#=L, CS2 #=H, WE #=H, OE #=L, LB #=L and UB
#=L.
Writing Operation
(1) Writing data into lower byte ( WE # control )
Data can be written by adding L pulse into WE # when the address is set while holding CS1#=L, CS2=H, OE #=H, LB #=L and
UB #=H.
The data on lower byte are latched up into the memory cell during WE # =L and LB # =L.
(2) Writing data into lower byte (LB # control)
Data can be written by adding L pulse into LB # when the address is set while holding CS1#=L, CS2 =H, OE#=H, UB# =H and
WE#=L.
The data on lower byte are latched up into the memory cell during WE# =L and LB# = L.
(3) Writing data into upper byte (WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
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A64S06161
UB #=L.
The data on upper byte are latched up into the memory cell during WE # =L and UB # = L.
(4) Writing data into upper byte (UB # control)
Data can be written by adding L pulse into UB # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
WE #=L.
The data on upper byte are latched up into the memory cell during WE #=L and UB #=L.
(5) Writing data into both byte ( WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2=H, OE #=H, LB #=L and
UB #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L.
(6) Writing data into both byte (LB #, UB # control)
Data can be written by adding L pulse into LB# and UB# when the address is set while holding CS1#=L, CS2=H, OE #=H and
WE #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L
Read or write with using both LB # and UB #, the timing edge of LB # and UB # must be same.
While I/O pins are in the output state, the data that is opposite to the output data should not be given.
Standby cycle
When CS1# is H, the device will be in the standby cycle. In this case data I/O pins are Hi-Z and all input pins are inhibited.
Power Down
When CS2 is L, the device will be in the power down. In this case, an internal refresh stops and the data might be lost.
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Parameter
Symbol
VCC
VI
Ratings
Unit
V
Supply voltage
-0.5 to 3.6
Input voltage
-0.5* to VCC+0.3
-0.5* to VCC+0.3
0.5
V
Input / Output voltage
Input / Output voltage
Operating temperature
Storage temperature
V I/O
PD
V
W
＇C
｀C
Topr
Tstg
-30 to 85
-65 to 150
* If pulse width is less than 5ns it is – 1.0V
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A64S06161
ELECTRICAL CHARACTERISTICS
DC Recommended Operating Conditions (Ta=-30~85＇C)
Parameter
Symbo1
Min
Max
Unit
VCC
VSS
VIH
VIL
2.70
0
3.30
0
V
V
V
V
Supply voltage
VCC-0.3
-0.3*
VCC+0.3
0.3
Input voltage
* If pulse width is less than 5ns it is –1.0V
DC ELECTRICAL CHARACTERISTICS
DC Characteristics (Ta=-30~85’C)
Typ*¹
Parameter
Symbol
Condition
Min
Max
Unit
﹣
﹣
µA
µA
Input leakage current
Output leakage current
ILI
VI=0V to VCC
-1
-1
1
1
ILO
LB and UB=H or CS1=H or WE=L or
OE=H or CS2=L VI/O=0V to VCC
IOH=-0.5ｍA
﹣
﹣
High level output
voltage
VOH
Vcc-0.3
V
IOL=0.5ｍA
CS2≦0.2V
﹣
﹣
﹣
﹣
﹣
﹣
﹣
Low level output voltage VOL
Power Down Current IDDPD
0.3
25
70
20
3
V
µA
VCC-0.2V≦CS1
I I/O=0ｍA, tcyc=70nS
I I/O=0ｍA, tcyc=1uS
µA
Standby Current
Operating current
IDDS
50
15
2.5
ｍA
ｍA
IDDA1
*1:Typical values are measured at Ta=25’C and VCC =3.0V
Terminal Capacitance
(Ta=25’C f=1MHz)
Parameter
Symbol
Conditions
Min
﹣
Max
Unit
Input Capacitance
I/O Capacitance
CI
VI=0V
8
pF
pF
﹣
C I/O
V I/O=0V
10
Note：This parameter is measured by sampling , not of all products.
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A64S06161
AC Electrical Characteristics
Read Cycle (Ta = - 30 ~ 85’C)
Parameter
Symbol
tRC
Teat Conditions
1
Min
70
Max
Unit
nS
Read cycle time
32000
Page read cycle time
Address access time
tRCP
tACC
tACCP
tACS
tOE
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
30
-
32000
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
70
30
70
40
25
-
Page address access time
CS1 # access time
-
-
OE # access time
-
LB # , UB # access time
Address set up to OE L #
Address set up to CS1 # L
Address hold time from CS1 #L
CS1# high pulse width
CS1 # output set time
tAB
-
tASO
tASC
tAHC
tC1H
tCLZ
tCHZ
tBLZ
tBHZ
tOLZ
tOHZ
tOH
-5
0
0
30
0
-
-
-
-
-
CS1 # output floating time
LB # , UB # output set time
LB # , UB # output floating tine
OE # output set time
15
-
0
-
15
-
0
-
OE # output floating time
Output hold time
15
-
5
Write Cycle (Ta= - 30~85’C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Write cycle time
Chip select time
tWC
tCW
tAW
tASC
tAHC
tAS
1
1
1
1
1
1
1
1
1
1
1
70
60
60
0
32000
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-
-
-
-
-
-
-
-
-
-
Address enable time
Address set up to CS1 # L
Address hold time from CS1 # H
Address set up time
Write pulse width
0
0
tWP
tBW
tWR
tDW
tDH
40
60
0
LB,UB select time
Address hold time
Data set up time
30
0
Data hold time
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A64S06161
Power Down Cycle(Ta= - 30~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # H set up time for Power Down entry
CS1 # H hold time before Power Down exit
CS2 L pulse width
tSSP
tSHP
1
1
1
1
0
0
-
-
-
-
nS
nS
nS
µS
TC2LP
tHPD
30
300
CS1 # H hold time after Power Down exit
Power Up Timing Requirement(Ta= - 30~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # CS2 set up time after Power Up
Standby hold time after Power Up
tSHU
tHPU
1
1
0
-
-
nS
µS
300
Data Retention Timing Requirement(Ta= - 30~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
A2 to A19 hold time during active
CS1# L hold time for A2 to A19 fix
tBAH
tCSH
1
1
0
-
-
nS
µS
300
Either tBAH or tCSH required for data retention.
Address Skew Timing Requirement(Ta= - 30~85＇C)
Parameter
Symbol
Test Conditions
Min
-
Max
10
Unit
nS
Maximum address skew
tSKEW
1
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A64S06161
Configuration Register
The configuration register (CR) defines how the A64S06161 operates and whether page mode read accesses are permitted. The
register is automatically loaded with default setting during power on and can be updated anytime while the device is operating in
a normal state.
CR Register Description
Reserved
PAGE
Reserved
A19 – A8
A7
A6 – A0
Bit(s)
Name
Reserved
A19 – A8, A6 – A0 Reserved
Reserved, All must be set to “0”
A7
Page Mode on/off
0 - Page Mode Disabled (Default)
1 - Page Mode Enabled
CR Register Update – Timing Waveform
tWC
A7 Define CR Register
Address
CS1#
tCW
tCS2CS1
tAW
tWR
tAS
tWP
WE#
CS2
tCS2WE
tCS2MIN
CR register update–Timing waveform
Notes:
1. VIH(max) = VCCQ + 0.2V for pulse durations less than 20ns.
2. VIL(min) = -1V for pulse duration less than 20ns.
3. Overshoot and undershoot specifications are characterized and are not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC =
VCC(typ.) and TA = 25°C.
CR Register Timings
Parameter
tCS2WE
Description
Min.
Max.
Unit
ns
CS2 LOW to WE# LOW
1000
tCS2MIN
Deep Power Down Mode Time
CS2 LOW to CE# LOW
32000
0
ns
tCS2CS1
1000
ns
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A64S06161
TEST CONDITION 1
Input pulse voltage level
VCC – 0.3V / 0.3V
Input ascend / descend time
Input output timing reference level
Output load
tr=tf=3nS
1/2VCC
CL=50pF(Includes Jig capacity)+1TTL
TEST CONDITION 2
Input pulse voltage level
Input ascend / descend time
Input output timing reference level
Output load
VCC – 0.3V / 0.3V
tr=tf=3nS
±100mV(The level change from stable voltage
CL=5pF(Includes Jig capacity)+1TTL
I / O
CL
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A64S06161
TIMING CHART
Read Cycle
tRC
Address
CS1#
tACC
tACS
tOH
tAHC
tCHZ
tASC
tAB
LB#/UB#
tASO
tBHZ
tOE
OE#
Dout
tOLZ
tOHZ
tBLZ
tCLZ
CS2 and WE # must be H level for entire read cycle.
Read Cycle ( Page Access [1] )
Address
No Change
tRCP
(A19-A2)
tRC
tRCP
Address
(A1-A0)
CS1#
OE#
tCHZ
tACS
tACCP
tACCP
tOH
tOH
tOH
tCLZ
Dout
CS2 and WE # must be H level for entire read cycle.
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A64S06161
Read Cycle ( Page Access [2] )
Address
No Change
tRCP
(A19-A2)
tRC
tRCP
Address
(A1-A0)
tACS
tOE
CS1#
OE#
tCHZ
tOH
tACCP
tACCP
tOH
tOH
tOLZ
Dout
CS2 and WE # must be H level for entire read cycle.
Write Cycle ( WE # Control )
tWC
Address
tAW
tCW
CS1#
tBW
LB# / UB#
WE#
tWR
tAS
tWP
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
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A64S06161
Write Cycle ( LB # / UB # Control )
tWC
Address
tAW
tCW
tAHC
CS1#
tASC
tAS
tWR
tBW
LB# / UB#
WE#
tWP
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
Standby
Address
tC1H
CS1#
tAHC
tASC
Active
Standby
Active
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A64S06161
Power Down Mode Entry / Exit
CS1#
tHPD
tSHP
tC2LP
CS2
tSSP
Power Up
CS1#
tSHU
tHPU
CS2
VCC(min)
VCC
Data Retention(1)
tBAH
Address
(A19-A2)
CS1#
This applies for both read and write.
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A64S06161
Data Retention (2)
tCSH
Address
No Change
(A19-A2)
CS1#
This applies for both read and write.
Address Skew(1)
A0-19
tSKEW
tRC / tWC
CS1#
tSKEW is from first address change to last address change
Address Skew(2)
A0-19
tRC / tWC
tSKEW
CS1#
tSKEW is from first address change to last address change
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A64S06161
Address Skew(3)
A0-19
tSKEW
CS1#
tSKEW is from first address change to stand-by
Reference External Wiring Diagram
Address Input
Control
Input / Output
I / O0
WE#
OE#
A0
I / O15
CS1#
A19
CS2
BU#
LB#
A64S06161
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A64S06161
Ordering Information
Power Down Mode
Standby Current
Max. (µA)
Operating Current
Max. (mA)
Part No.
Access Time (ns)
Package
A64S06161G-70I
70
20
25
48 Pins FBGA
Note: -I is for industrial operating temperature range
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A64S06161
48 Pins FBGA Package outline drawing
-A-
6.00
0.10
PIN#1
-B-
0.08
C
CAVITY
C
C
-C-
SOLDER BALL
SEATING PLANE
0.10
0.1
C
DETAIL : A
C
C
A
B
M
0.2
“A＂
0.1
M
SECTION C-C
3.75
0.75
H
G
B
F
E
D
C
B
A
A
1
2
DETAIL : B
“B＂
1 2 3 4 5 6
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